/*
 *******************************************************************************
 *
 * Copyright (c) 2017 Advanced Micro Devices, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 ******************************************************************************/

// *
// *
// *	 (c) 2014 AMD Inc.  (unpublished)
// *
// *	 All rights reserved.  This notice is intended as a precaution against
// *	 inadvertent publication and does not imply publication or any waiver
// *	 of confidentiality.  The year included in the foregoing notice is the
// *	 year of creation of the work.

#if !defined __SI__CI__VIoffset_HEADER
#define __SI__CI__VIoffset_HEADER

#define SI_CI_offset_HEADER__SI__CI
#define cfgADAPTER_ID                                   0x000B
#define cfgADAPTER_ID_W                                 0x0013
#define cfgBASE_ADDR_1                                  0x0004
#define cfgBASE_ADDR_2                                  0x0005
#define cfgBASE_ADDR_3                                  0x0006
#define cfgBASE_ADDR_4                                  0x0007
#define cfgBASE_ADDR_5                                  0x0008
#define cfgBASE_ADDR_6                                  0x0009
#define cfgBASE_CLASS                                   0x0002
#define cfgBIST                                         0x0003
#define cfgCACHE_LINE                                   0x0003
#define cfgCAP_PTR                                      0x000D
#define cfgCOMMAND                                      0x0001
#define cfgDEVICE_CAP                                   0x0017
#define cfgDEVICE_CAP2                                  0x001F
#define cfgDEVICE_CNTL                                  0x0018
#define cfgDEVICE_CNTL2                                 0x0020
#define cfgDEVICE_ID                                    0x0000
#define cfgDEVICE_STATUS                                0x0018
#define cfgDEVICE_STATUS2                               0x0020
#define cfgHEADER                                       0x0003
#define cfgINTERRUPT_LINE                               0x000F
#define cfgINTERRUPT_PIN                                0x000F
#define cfgLATENCY                                      0x0003
#define cfgLINK_CAP                                     0x0019
#define cfgLINK_CAP2                                    0x0021
#define cfgLINK_CNTL                                    0x001A
#define cfgLINK_CNTL2                                   0x0022
#define cfgLINK_STATUS                                  0x001A
#define cfgLINK_STATUS2                                 0x0022
#define cfgMAX_LATENCY                                  0x000F
#define cfgMIN_GRANT                                    0x000F
#define cfgMSI_CAP_LIST                                 0x0028
#define cfgMSI_MSG_ADDR_HI                              0x002A
#define cfgMSI_MSG_ADDR_LO                              0x0029
#define cfgMSI_MSG_CNTL                                 0x0028
#define cfgMSI_MSG_DATA                                 0x002A
#define cfgMSI_MSG_DATA_64                              0x002B
#define cfgPCIE_ACS_CAP__CI__VI                         0x00A9
#define cfgPCIE_ACS_CNTL__CI__VI                        0x00A9
#define cfgPCIE_ACS_ENH_CAP_LIST__CI__VI                0x00A8
#define cfgPCIE_ADV_ERR_CAP_CNTL                        0x005A
#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST                0x0054
#define cfgPCIE_ATS_CAP__CI__VI                         0x00AD
#define cfgPCIE_ATS_CNTL__CI__VI                        0x00AD
#define cfgPCIE_ATS_ENH_CAP_LIST__CI__VI                0x00AC
#define cfgPCIE_BAR1_CAP__CI__VI                        0x0081
#define cfgPCIE_BAR1_CNTL__CI__VI                       0x0082
#define cfgPCIE_BAR2_CAP__CI__VI                        0x0083
#define cfgPCIE_BAR2_CNTL__CI__VI                       0x0084
#define cfgPCIE_BAR3_CAP__CI__VI                        0x0085
#define cfgPCIE_BAR3_CNTL__CI__VI                       0x0086
#define cfgPCIE_BAR4_CAP__CI__VI                        0x0087
#define cfgPCIE_BAR4_CNTL__CI__VI                       0x0088
#define cfgPCIE_BAR5_CAP__CI__VI                        0x0089
#define cfgPCIE_BAR5_CNTL__CI__VI                       0x008A
#define cfgPCIE_BAR6_CAP__CI__VI                        0x008B
#define cfgPCIE_BAR6_CNTL__CI__VI                       0x008C
#define cfgPCIE_BAR_ENH_CAP_LIST__CI__VI                0x0080
#define cfgPCIE_CAP                                     0x0016
#define cfgPCIE_CAP_LIST                                0x0016
#define cfgPCIE_CORR_ERR_MASK                           0x0059
#define cfgPCIE_CORR_ERR_STATUS                         0x0058
#define cfgPCIE_DEV_SERIAL_NUM_DW1                      0x0051
#define cfgPCIE_DEV_SERIAL_NUM_DW2                      0x0052
#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST             0x0050
#define cfgPCIE_DPA_CAP__CI__VI                         0x0095
#define cfgPCIE_DPA_CNTL__CI__VI                        0x0097
#define cfgPCIE_DPA_ENH_CAP_LIST__CI__VI                0x0094
#define cfgPCIE_DPA_LATENCY_INDICATOR__CI__VI           0x0096
#define cfgPCIE_DPA_STATUS__CI__VI                      0x0097
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI        0x0098
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI        0x0098
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI        0x0098
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI        0x0098
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI        0x0099
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI        0x0099
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI        0x0099
#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI        0x0099
#define cfgPCIE_HDR_LOG0                                0x005B
#define cfgPCIE_HDR_LOG1                                0x005C
#define cfgPCIE_HDR_LOG2                                0x005D
#define cfgPCIE_HDR_LOG3                                0x005E
#define cfgPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI        0x009F
#define cfgPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI       0x00A4
#define cfgPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI       0x00A4
#define cfgPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI       0x00A5
#define cfgPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI       0x00A5
#define cfgPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI       0x00A6
#define cfgPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI       0x00A6
#define cfgPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI        0x009F
#define cfgPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI        0x00A0
#define cfgPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI        0x00A0
#define cfgPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI        0x00A1
#define cfgPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI        0x00A1
#define cfgPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI        0x00A2
#define cfgPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI        0x00A2
#define cfgPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI        0x00A3
#define cfgPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI        0x00A3
#define cfgPCIE_LANE_ERROR_STATUS__CI__VI               0x009E
#define cfgPCIE_LINK_CNTL3__CI__VI                      0x009D
#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI         0x00B3
#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI      0x00B2
#define cfgPCIE_PAGE_REQ_CNTL__CI__VI                   0x00B1
#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI           0x00B0
#define cfgPCIE_PAGE_REQ_STATUS__CI__VI                 0x00B1
#define cfgPCIE_PASID_CAP__CI__VI                       0x00B5
#define cfgPCIE_PASID_CNTL__CI__VI                      0x00B5
#define cfgPCIE_PASID_ENH_CAP_LIST__CI__VI              0x00B4
#define cfgPCIE_PORT_VC_CAP_REG1                        0x0045
#define cfgPCIE_PORT_VC_CAP_REG2                        0x0046
#define cfgPCIE_PORT_VC_CNTL                            0x0047
#define cfgPCIE_PORT_VC_STATUS                          0x0047
#define cfgPCIE_PWR_BUDGET_CAP__CI__VI                  0x0093
#define cfgPCIE_PWR_BUDGET_DATA_SELECT__CI__VI          0x0091
#define cfgPCIE_PWR_BUDGET_DATA__CI__VI                 0x0092
#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI         0x0090
#define cfgPCIE_SECONDARY_ENH_CAP_LIST__CI__VI          0x009C
#define cfgPCIE_TLP_PREFIX_LOG0__CI__VI                 0x0062
#define cfgPCIE_TLP_PREFIX_LOG1__CI__VI                 0x0063
#define cfgPCIE_TLP_PREFIX_LOG2__CI__VI                 0x0064
#define cfgPCIE_TLP_PREFIX_LOG3__CI__VI                 0x0065
#define cfgPCIE_UNCORR_ERR_MASK                         0x0056
#define cfgPCIE_UNCORR_ERR_SEVERITY                     0x0057
#define cfgPCIE_UNCORR_ERR_STATUS                       0x0055
#define cfgPCIE_VC0_RESOURCE_CAP                        0x0048
#define cfgPCIE_VC0_RESOURCE_CNTL                       0x0049
#define cfgPCIE_VC0_RESOURCE_STATUS                     0x004A
#define cfgPCIE_VC1_RESOURCE_CAP                        0x004B
#define cfgPCIE_VC1_RESOURCE_CNTL                       0x004C
#define cfgPCIE_VC1_RESOURCE_STATUS                     0x004D
#define cfgPCIE_VC_ENH_CAP_LIST                         0x0044
#define cfgPCIE_VENDOR_SPECIFIC1                        0x0042
#define cfgPCIE_VENDOR_SPECIFIC2                        0x0043
#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST            0x0040
#define cfgPCIE_VENDOR_SPECIFIC_HDR                     0x0041
#define cfgPMI_CAP                                      0x0014
#define cfgPMI_CAP_LIST                                 0x0014
#define cfgPMI_STATUS_CNTL                              0x0015
#define cfgPROG_INTERFACE                               0x0002
#define cfgREVISION_ID                                  0x0002
#define cfgROM_BASE_ADDR                                0x000C
#define cfgSTATUS                                       0x0001
#define cfgSUB_CLASS                                    0x0002
#define cfgVENDOR_CAP_LIST__CI__VI                      0x0012
#define cfgVENDOR_ID                                    0x0000
#define ioATTRDR__SI__VI                                0x00F0
#define ioATTRDW__SI__VI                                0x00F0
#define ioATTRX__SI__VI                                 0x00F0
#define ioBIF_RFE_SNOOP_REG__CI__VI                     0x0027
#define ioCRTC8_DATA__SI__VI                            0x00ED
#define ioCRTC8_IDX__SI__VI                             0x00ED
#define ioDAC_DATA__SI__VI                              0x00F2
#define ioDAC_MASK__SI__VI                              0x00F1
#define ioDAC_R_INDEX__SI__VI                           0x00F1
#define ioDAC_W_INDEX__SI__VI                           0x00F2
#define ioGENENB__SI__VI                                0x00F0
#define ioGENFC_RD__SI__VI                              0x00F2
#define ioGENFC_WT__SI__VI                              0x00EE
#define ioGENMO_RD__SI__VI                              0x00F3
#define ioGENMO_WT__SI__VI                              0x00F0
#define ioGENS0__SI__VI                                 0x00F0
#define ioGENS1__SI__VI                                 0x00EE
#define ioGRPH8_DATA__SI__VI                            0x00F3
#define ioGRPH8_IDX__SI__VI                             0x00F3
#define ioMM_DATA                                       0x0001
#define ioMM_INDEX                                      0x0000
#define ioMM_INDEX_HI__CI__VI                           0x0006
#define ioPCIE_DATA_2__CI__VI                           0x000D
#define ioPCIE_DATA__CI__VI                             0x000F
#define ioPCIE_DATA__SI                                 0x000D
#define ioPCIE_INDEX_2__CI__VI                          0x000C
#define ioPCIE_INDEX__CI__VI                            0x000E
#define ioPCIE_INDEX__SI                                0x000C
#define ioROM_DATA__SI                                  0x002B
#define ioROM_INDEX__SI                                 0x002A
#define ioSEQ8_DATA__SI__VI                             0x00F1
#define ioSEQ8_IDX__SI__VI                              0x00F1
#define ioVGA_MEM_READ_PAGE_ADDR__SI__VI                0x0013
#define ioVGA_MEM_WRITE_PAGE_ADDR__SI__VI               0x0012
#define mmABM_TEST_DEBUG_DATA__SI__VI                   0x169F
#define mmABM_TEST_DEBUG_INDEX__SI__VI                  0x169E
#define mmACP_CONFIG__CI                                0x0F95
#define mmAFMT_60958_0__SI                              0x1C41
#define mmAFMT_60958_1__SI                              0x1C42
#define mmAFMT_60958_2__SI                              0x1C48
#define mmAFMT_AUDIO_CRC_CONTROL__SI                    0x1C43
#define mmAFMT_AUDIO_CRC_RESULT__SI                     0x1C49
#define mmAFMT_AUDIO_INFO0__SI                          0x1C3F
#define mmAFMT_AUDIO_INFO1__SI                          0x1C40
#define mmAFMT_AUDIO_PACKET_CONTROL2__SI                0x1C17
#define mmAFMT_AUDIO_PACKET_CONTROL__SI                 0x1C4B
#define mmAFMT_AVI_INFO0__SI                            0x1C21
#define mmAFMT_AVI_INFO1__SI                            0x1C22
#define mmAFMT_AVI_INFO2__SI                            0x1C23
#define mmAFMT_AVI_INFO3__SI                            0x1C24
#define mmAFMT_INFOFRAME_CONTROL0__SI                   0x1C4D
#define mmAFMT_ISRC1_0__SI                              0x1C18
#define mmAFMT_ISRC1_1__SI                              0x1C19
#define mmAFMT_ISRC1_2__SI                              0x1C1A
#define mmAFMT_ISRC1_3__SI                              0x1C1B
#define mmAFMT_ISRC1_4__SI                              0x1C1C
#define mmAFMT_ISRC2_0__SI                              0x1C1D
#define mmAFMT_ISRC2_1__SI                              0x1C1E
#define mmAFMT_ISRC2_2__SI                              0x1C1F
#define mmAFMT_ISRC2_3__SI                              0x1C20
#define mmAFMT_MPEG_INFO0__SI                           0x1C25
#define mmAFMT_MPEG_INFO1__SI                           0x1C26
#define mmAFMT_RAMP_CONTROL0__SI                        0x1C44
#define mmAFMT_RAMP_CONTROL1__SI                        0x1C45
#define mmAFMT_RAMP_CONTROL2__SI                        0x1C46
#define mmAFMT_RAMP_CONTROL3__SI                        0x1C47
#define mmAFMT_STATUS__SI                               0x1C4A
#define mmAFMT_VBI_PACKET_CONTROL__SI                   0x1C4C
#define mmATC_ATS_CNTL__CI__VI                          0x0CC9
#define mmATC_ATS_DEBUG__CI__VI                         0x0CCA
#define mmATC_ATS_DEFAULT_PAGE_CNTL__CI__VI             0x0CD1
#define mmATC_ATS_DEFAULT_PAGE_LOW__CI__VI              0x0CD0
#define mmATC_ATS_FAULT_CNTL__CI__VI                    0x0CCD
#define mmATC_ATS_FAULT_DEBUG__CI__VI                   0x0CCB
#define mmATC_ATS_FAULT_STATUS_ADDR__CI__VI             0x0CCF
#define mmATC_ATS_FAULT_STATUS_INFO__CI__VI             0x0CCE
#define mmATC_ATS_STATUS__CI__VI                        0x0CCC
#define mmATC_L1RD_DEBUG_TLB__CI__VI                    0x0CDE
#define mmATC_L1RD_STATUS__CI__VI                       0x0CE0
#define mmATC_L1WR_DEBUG_TLB__CI__VI                    0x0CDF
#define mmATC_L1WR_STATUS__CI__VI                       0x0CE1
#define mmATC_L1_ADDRESS_OFFSET__CI__VI                 0x0CDD
#define mmATC_L1_CNTL__CI__VI                           0x0CDC
#define mmATC_L2_CNTL2__CI__VI                          0x0CD6
#define mmATC_L2_CNTL__CI__VI                           0x0CD5
#define mmATC_L2_DEBUG2__CI__VI                         0x0CD8
#define mmATC_L2_DEBUG__CI__VI                          0x0CD7
#define mmATC_MISC_CG__CI__VI                           0x0CD4
#define mmATC_PERFCOUNTER0_CFG__CI__VI                  0x07C8
#define mmATC_PERFCOUNTER1_CFG__CI__VI                  0x07C9
#define mmATC_PERFCOUNTER2_CFG__CI__VI                  0x07CA
#define mmATC_PERFCOUNTER3_CFG__CI__VI                  0x07CB
#define mmATC_PERFCOUNTER_HI__CI__VI                    0x07AF
#define mmATC_PERFCOUNTER_LO__CI__VI                    0x07A7
#define mmATC_PERFCOUNTER_RSLT_CNTL__CI__VI             0x07D5
#define mmATC_VMID0_PASID_MAPPING__CI__VI               0x0CE7
#define mmATC_VMID10_PASID_MAPPING__CI__VI              0x0CF1
#define mmATC_VMID11_PASID_MAPPING__CI__VI              0x0CF2
#define mmATC_VMID12_PASID_MAPPING__CI__VI              0x0CF3
#define mmATC_VMID13_PASID_MAPPING__CI__VI              0x0CF4
#define mmATC_VMID14_PASID_MAPPING__CI__VI              0x0CF5
#define mmATC_VMID15_PASID_MAPPING__CI__VI              0x0CF6
#define mmATC_VMID1_PASID_MAPPING__CI__VI               0x0CE8
#define mmATC_VMID2_PASID_MAPPING__CI__VI               0x0CE9
#define mmATC_VMID3_PASID_MAPPING__CI__VI               0x0CEA
#define mmATC_VMID4_PASID_MAPPING__CI__VI               0x0CEB
#define mmATC_VMID5_PASID_MAPPING__CI__VI               0x0CEC
#define mmATC_VMID6_PASID_MAPPING__CI__VI               0x0CED
#define mmATC_VMID7_PASID_MAPPING__CI__VI               0x0CEE
#define mmATC_VMID8_PASID_MAPPING__CI__VI               0x0CEF
#define mmATC_VMID9_PASID_MAPPING__CI__VI               0x0CF0
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI  0x0CE6
#define mmATC_VM_APERTURE0_CNTL2__CI__VI                0x0CC6
#define mmATC_VM_APERTURE0_CNTL__CI__VI                 0x0CC4
#define mmATC_VM_APERTURE0_HIGH_ADDR__CI__VI            0x0CC2
#define mmATC_VM_APERTURE0_LOW_ADDR__CI__VI             0x0CC0
#define mmATC_VM_APERTURE1_CNTL2__CI__VI                0x0CC7
#define mmATC_VM_APERTURE1_CNTL__CI__VI                 0x0CC5
#define mmATC_VM_APERTURE1_HIGH_ADDR__CI__VI            0x0CC3
#define mmATC_VM_APERTURE1_LOW_ADDR__CI__VI             0x0CC1
#define mmATTRDR__SI__VI                                0x00F0
#define mmATTRDW__SI__VI                                0x00F0
#define mmATTRX__SI__VI                                 0x00F0
#define mmAUXN_IMPCAL__SI                               0x194B
#define mmAUXP_IMPCAL__SI                               0x194A
#define mmAUX_ARB_CONTROL__SI                           0x1882
#define mmAUX_CONTROL__SI                               0x1880
#define mmAUX_DPHY_RX_CONTROL0__SI                      0x188A
#define mmAUX_DPHY_RX_CONTROL1__SI                      0x188B
#define mmAUX_DPHY_RX_STATUS__SI                        0x188D
#define mmAUX_DPHY_TX_CONTROL__SI                       0x1889
#define mmAUX_DPHY_TX_REF_CONTROL__SI                   0x1888
#define mmAUX_DPHY_TX_STATUS__SI                        0x188C
#define mmAUX_INTERRUPT_CONTROL__SI                     0x1883
#define mmAUX_LS_DATA__SI                               0x1887
#define mmAUX_LS_STATUS__SI                             0x1885
#define mmAUX_SW_CONTROL__SI                            0x1881
#define mmAUX_SW_DATA__SI                               0x1886
#define mmAUX_SW_STATUS__SI                             0x1884
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI 0x17F6
#define mmAZALIA_AUDIO_DTO_CONTROL__SI                  0x173D
#define mmAZALIA_AUDIO_DTO__SI                          0x173C
#define mmAZALIA_BDL_DMA_CONTROL__SI                    0x1730
#define mmAZALIA_CORB_DMA_CONTROL__SI                   0x172F
#define mmAZALIA_CUMULATIVE_LATENCY_COUNT__SI           0x1737
#define mmAZALIA_CUMULATIVE_REQUEST_COUNT__SI           0x1738
#define mmAZALIA_CYCLIC_BUFFER_SYNC__SI                 0x17F7
#define mmAZALIA_DATA_DMA_CONTROL__SI                   0x1731
#define mmAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI 0x174F
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI 0x174C
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI    0x174D
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI 0x1750
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI 0x1742
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI 0x1745
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI 0x1744
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI 0x1743
#define mmAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI 0x174B
#define mmAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI 0x1753
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI 0x173F
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI 0x173E
#define mmAZALIA_LATENCY_COUNTER_CONTROL__SI            0x1735
#define mmAZALIA_RIRB_AND_DP_CONTROL__SI                0x172D
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE__SI            0x1732
#define mmAZALIA_WORSTCASE_LATENCY_COUNT__SI            0x1736
#define mmAZ_TEST_DEBUG_DATA__SI                        0x1756
#define mmAZ_TEST_DEBUG_INDEX__SI                       0x1755
#define mmBACO_CNTL_MISC__CI__VI                        0x14DB
#define mmBACO_CNTL__CI__VI                             0x14E5
#define mmBCI_DEBUG_READ__CI__VI                        0x24EB
#define mmBCI_DEBUG_READ__SI                            0x24E3
#define mmBIF_BACO_DEBUG_LATCH__CI__VI                  0x14DC
#define mmBIF_BACO_DEBUG__CI__VI                        0x14DF
#define mmBIF_BACO_MSIC__CI                             0x1480
#define mmBIF_BUSNUM_CNTL1                              0x1525
#define mmBIF_BUSNUM_CNTL2                              0x152B
#define mmBIF_BUSNUM_LIST0                              0x1526
#define mmBIF_BUSNUM_LIST1                              0x1527
#define mmBIF_BUSY_DELAY_CNTR                           0x1529
#define mmBIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI           0x1455
#define mmBIF_CLK_PDWN_DELAY_TIMER__CI                  0x1483
#define mmBIF_CLK_PDWN_DELAY_TIMER__SI                  0x151F
#define mmBIF_DEBUG_CNTL                                0x151C
#define mmBIF_DEBUG_MUX                                 0x151D
#define mmBIF_DEBUG_OUT                                 0x151E
#define mmBIF_DEVFUNCNUM_LIST0__CI__VI                  0x14E8
#define mmBIF_DEVFUNCNUM_LIST1__CI__VI                  0x14E7
#define mmBIF_DOORBELL_CNTL__CI__VI                     0x14C3
#define mmBIF_FB_EN                                     0x1524
#define mmBIF_FEATURES_CONTROL_MISC__CI__VI             0x14C2
#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI 0x1454
#define mmBIF_IMPCTL_RXCNTL__CI__VI                     0x1451
#define mmBIF_IMPCTL_SMPLCNTL__CI__VI                   0x1450
#define mmBIF_IMPCTL_TXCNTL_pd__CI__VI                  0x1452
#define mmBIF_IMPCTL_TXCNTL_pu__CI__VI                  0x1453
#define mmBIF_LNCNT_RESET__CI                           0x1488
#define mmBIF_PERFCOUNTER0_RESULT__CI__VI               0x152D
#define mmBIF_PERFCOUNTER1_RESULT__CI__VI               0x152E
#define mmBIF_PERFMON_CNTL__CI__VI                      0x152C
#define mmBIF_PIF_TXCLK_SWITCH_TIMER__CI                0x1481
#define mmBIF_PWDN_COMMAND__CI__VI                      0x1444
#define mmBIF_PWDN_STATUS__CI__VI                       0x1445
#define mmBIF_RESET_CNTL__CI                            0x1486
#define mmBIF_RESET_EN__CI                              0x1482
#define mmBIF_RESET_EN__SI                              0x1511
#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI        0x1442
#define mmBIF_RFE_IMPRST_CNTL__CI__VI                   0x1458
#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER__CI__VI        0x1443
#define mmBIF_RFE_MMCFG_CNTL__CI__VI                    0x144C
#define mmBIF_RFE_MST_BU_CMDSTATUS__CI__VI              0x1446
#define mmBIF_RFE_MST_BX_CMDSTATUS__CI                  0x1448
#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI  0x1447
#define mmBIF_RFE_MST_TMOUT_STATUS__CI__VI              0x144B
#define mmBIF_RFE_SNOOP_REG__CI__VI                     0x0027
#define mmBIF_RFE_SOFTRST_CNTL__CI__VI                  0x1441
#define mmBIF_SCRATCH0                                  0x150E
#define mmBIF_SCRATCH1                                  0x150F
#define mmBIF_SLVARB_MODE__CI__VI                       0x14C4
#define mmBIF_SSA_DISP_LOWER__CI                        0x14D2
#define mmBIF_SSA_DISP_UPPER__CI                        0x14D3
#define mmBIF_SSA_GFX0_LOWER__CI                        0x14CA
#define mmBIF_SSA_GFX0_UPPER__CI                        0x14CB
#define mmBIF_SSA_GFX1_LOWER__CI                        0x14CC
#define mmBIF_SSA_GFX1_UPPER__CI                        0x14CD
#define mmBIF_SSA_GFX2_LOWER__CI                        0x14CE
#define mmBIF_SSA_GFX2_UPPER__CI                        0x14CF
#define mmBIF_SSA_GFX3_LOWER__CI                        0x14D0
#define mmBIF_SSA_GFX3_UPPER__CI                        0x14D1
#define mmBIF_SSA_MC_LOWER__CI                          0x14D4
#define mmBIF_SSA_MC_UPPER__CI                          0x14D5
#define mmBIF_SSA_PWR_STATUS__CI                        0x14C8
#define mmBIF_XDMA_HI__CI__VI                           0x14C1
#define mmBIF_XDMA_LO__CI__VI                           0x14C0
#define mmBIOS_SCRATCH_0                                0x05C9
#define mmBIOS_SCRATCH_1                                0x05CA
#define mmBIOS_SCRATCH_10                               0x05D3
#define mmBIOS_SCRATCH_11                               0x05D4
#define mmBIOS_SCRATCH_12                               0x05D5
#define mmBIOS_SCRATCH_13                               0x05D6
#define mmBIOS_SCRATCH_14                               0x05D7
#define mmBIOS_SCRATCH_15                               0x05D8
#define mmBIOS_SCRATCH_2                                0x05CB
#define mmBIOS_SCRATCH_3                                0x05CC
#define mmBIOS_SCRATCH_4                                0x05CD
#define mmBIOS_SCRATCH_5                                0x05CE
#define mmBIOS_SCRATCH_6                                0x05CF
#define mmBIOS_SCRATCH_7                                0x05D0
#define mmBIOS_SCRATCH_8                                0x05D1
#define mmBIOS_SCRATCH_9                                0x05D2
#define mmBL1_PWM_ABM_CNTL__SI__VI                      0x162E
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL__SI__VI           0x1628
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE__SI__VI         0x162F
#define mmBL1_PWM_CURRENT_ABM_LEVEL__SI__VI             0x162B
#define mmBL1_PWM_FINAL_DUTY_CYCLE__SI__VI              0x162C
#define mmBL1_PWM_GRP2_REG_LOCK__SI__VI                 0x1630
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE__SI__VI            0x162D
#define mmBL1_PWM_TARGET_ABM_LEVEL__SI__VI              0x162A
#define mmBL1_PWM_USER_LEVEL__SI__VI                    0x1629
#define mmBL_PWM_CNTL2__SI                              0x1968
#define mmBL_PWM_CNTL__SI                               0x1967
#define mmBL_PWM_GRP1_REG_LOCK__SI                      0x196A
#define mmBL_PWM_PERIOD_CNTL__SI                        0x1969
#define mmBUS_CNTL                                      0x1508
#define mmBX_RESET_EN__CI__VI                           0x1514
#define mmCAPTURE_HOST_BUSNUM                           0x153C
#define mmCB_BLEND0_CONTROL                             0xA1E0
#define mmCB_BLEND1_CONTROL                             0xA1E1
#define mmCB_BLEND2_CONTROL                             0xA1E2
#define mmCB_BLEND3_CONTROL                             0xA1E3
#define mmCB_BLEND4_CONTROL                             0xA1E4
#define mmCB_BLEND5_CONTROL                             0xA1E5
#define mmCB_BLEND6_CONTROL                             0xA1E6
#define mmCB_BLEND7_CONTROL                             0xA1E7
#define mmCB_BLEND_ALPHA                                0xA108
#define mmCB_BLEND_BLUE                                 0xA107
#define mmCB_BLEND_GREEN                                0xA106
#define mmCB_BLEND_RED                                  0xA105
#define mmCB_CGTT_SCLK_CTRL__CI__VI                     0xF0A8
#define mmCB_CGTT_SCLK_CTRL__SI                         0x2698
#define mmCB_COLOR0_ATTRIB                              0xA31D
#define mmCB_COLOR0_BASE                                0xA318
#define mmCB_COLOR0_CLEAR_WORD0                         0xA323
#define mmCB_COLOR0_CLEAR_WORD1                         0xA324
#define mmCB_COLOR0_CMASK                               0xA31F
#define mmCB_COLOR0_CMASK_SLICE                         0xA320
#define mmCB_COLOR0_FMASK                               0xA321
#define mmCB_COLOR0_FMASK_SLICE                         0xA322
#define mmCB_COLOR0_INFO                                0xA31C
#define mmCB_COLOR0_PITCH                               0xA319
#define mmCB_COLOR0_SLICE                               0xA31A
#define mmCB_COLOR0_VIEW                                0xA31B
#define mmCB_COLOR1_ATTRIB                              0xA32C
#define mmCB_COLOR1_BASE                                0xA327
#define mmCB_COLOR1_CLEAR_WORD0                         0xA332
#define mmCB_COLOR1_CLEAR_WORD1                         0xA333
#define mmCB_COLOR1_CMASK                               0xA32E
#define mmCB_COLOR1_CMASK_SLICE                         0xA32F
#define mmCB_COLOR1_FMASK                               0xA330
#define mmCB_COLOR1_FMASK_SLICE                         0xA331
#define mmCB_COLOR1_INFO                                0xA32B
#define mmCB_COLOR1_PITCH                               0xA328
#define mmCB_COLOR1_SLICE                               0xA329
#define mmCB_COLOR1_VIEW                                0xA32A
#define mmCB_COLOR2_ATTRIB                              0xA33B
#define mmCB_COLOR2_BASE                                0xA336
#define mmCB_COLOR2_CLEAR_WORD0                         0xA341
#define mmCB_COLOR2_CLEAR_WORD1                         0xA342
#define mmCB_COLOR2_CMASK                               0xA33D
#define mmCB_COLOR2_CMASK_SLICE                         0xA33E
#define mmCB_COLOR2_FMASK                               0xA33F
#define mmCB_COLOR2_FMASK_SLICE                         0xA340
#define mmCB_COLOR2_INFO                                0xA33A
#define mmCB_COLOR2_PITCH                               0xA337
#define mmCB_COLOR2_SLICE                               0xA338
#define mmCB_COLOR2_VIEW                                0xA339
#define mmCB_COLOR3_ATTRIB                              0xA34A
#define mmCB_COLOR3_BASE                                0xA345
#define mmCB_COLOR3_CLEAR_WORD0                         0xA350
#define mmCB_COLOR3_CLEAR_WORD1                         0xA351
#define mmCB_COLOR3_CMASK                               0xA34C
#define mmCB_COLOR3_CMASK_SLICE                         0xA34D
#define mmCB_COLOR3_FMASK                               0xA34E
#define mmCB_COLOR3_FMASK_SLICE                         0xA34F
#define mmCB_COLOR3_INFO                                0xA349
#define mmCB_COLOR3_PITCH                               0xA346
#define mmCB_COLOR3_SLICE                               0xA347
#define mmCB_COLOR3_VIEW                                0xA348
#define mmCB_COLOR4_ATTRIB                              0xA359
#define mmCB_COLOR4_BASE                                0xA354
#define mmCB_COLOR4_CLEAR_WORD0                         0xA35F
#define mmCB_COLOR4_CLEAR_WORD1                         0xA360
#define mmCB_COLOR4_CMASK                               0xA35B
#define mmCB_COLOR4_CMASK_SLICE                         0xA35C
#define mmCB_COLOR4_FMASK                               0xA35D
#define mmCB_COLOR4_FMASK_SLICE                         0xA35E
#define mmCB_COLOR4_INFO                                0xA358
#define mmCB_COLOR4_PITCH                               0xA355
#define mmCB_COLOR4_SLICE                               0xA356
#define mmCB_COLOR4_VIEW                                0xA357
#define mmCB_COLOR5_ATTRIB                              0xA368
#define mmCB_COLOR5_BASE                                0xA363
#define mmCB_COLOR5_CLEAR_WORD0                         0xA36E
#define mmCB_COLOR5_CLEAR_WORD1                         0xA36F
#define mmCB_COLOR5_CMASK                               0xA36A
#define mmCB_COLOR5_CMASK_SLICE                         0xA36B
#define mmCB_COLOR5_FMASK                               0xA36C
#define mmCB_COLOR5_FMASK_SLICE                         0xA36D
#define mmCB_COLOR5_INFO                                0xA367
#define mmCB_COLOR5_PITCH                               0xA364
#define mmCB_COLOR5_SLICE                               0xA365
#define mmCB_COLOR5_VIEW                                0xA366
#define mmCB_COLOR6_ATTRIB                              0xA377
#define mmCB_COLOR6_BASE                                0xA372
#define mmCB_COLOR6_CLEAR_WORD0                         0xA37D
#define mmCB_COLOR6_CLEAR_WORD1                         0xA37E
#define mmCB_COLOR6_CMASK                               0xA379
#define mmCB_COLOR6_CMASK_SLICE                         0xA37A
#define mmCB_COLOR6_FMASK                               0xA37B
#define mmCB_COLOR6_FMASK_SLICE                         0xA37C
#define mmCB_COLOR6_INFO                                0xA376
#define mmCB_COLOR6_PITCH                               0xA373
#define mmCB_COLOR6_SLICE                               0xA374
#define mmCB_COLOR6_VIEW                                0xA375
#define mmCB_COLOR7_ATTRIB                              0xA386
#define mmCB_COLOR7_BASE                                0xA381
#define mmCB_COLOR7_CLEAR_WORD0                         0xA38C
#define mmCB_COLOR7_CLEAR_WORD1                         0xA38D
#define mmCB_COLOR7_CMASK                               0xA388
#define mmCB_COLOR7_CMASK_SLICE                         0xA389
#define mmCB_COLOR7_FMASK                               0xA38A
#define mmCB_COLOR7_FMASK_SLICE                         0xA38B
#define mmCB_COLOR7_INFO                                0xA385
#define mmCB_COLOR7_PITCH                               0xA382
#define mmCB_COLOR7_SLICE                               0xA383
#define mmCB_COLOR7_VIEW                                0xA384
#define mmCB_COLOR_CONTROL                              0xA202
#define mmCB_DEBUG_BUS_1                                0x2699
#define mmCB_DEBUG_BUS_13                               0x26A5
#define mmCB_DEBUG_BUS_14                               0x26A6
#define mmCB_DEBUG_BUS_15                               0x26A7
#define mmCB_DEBUG_BUS_16                               0x26A8
#define mmCB_DEBUG_BUS_17                               0x26A9
#define mmCB_DEBUG_BUS_18                               0x26AA
#define mmCB_DEBUG_BUS_2                                0x269A
#define mmCB_HW_CONTROL                                 0x2684
#define mmCB_HW_CONTROL_1                               0x2685
#define mmCB_HW_CONTROL_2                               0x2686
#define mmCB_HW_CONTROL_3__CI__VI                       0x2683
#define mmCB_PERFCOUNTER0_HI__CI__VI                    0xD407
#define mmCB_PERFCOUNTER0_HI__SI                        0x2691
#define mmCB_PERFCOUNTER0_LO__CI__VI                    0xD406
#define mmCB_PERFCOUNTER0_LO__SI                        0x2690
#define mmCB_PERFCOUNTER0_SELECT0__SI                   0x2688
#define mmCB_PERFCOUNTER0_SELECT1__CI__VI               0xDC02
#define mmCB_PERFCOUNTER0_SELECT1__SI                   0x2689
#define mmCB_PERFCOUNTER0_SELECT__CI__VI                0xDC01
#define mmCB_PERFCOUNTER1_HI__CI__VI                    0xD409
#define mmCB_PERFCOUNTER1_HI__SI                        0x2693
#define mmCB_PERFCOUNTER1_LO__CI__VI                    0xD408
#define mmCB_PERFCOUNTER1_LO__SI                        0x2692
#define mmCB_PERFCOUNTER1_SELECT0__SI                   0x268A
#define mmCB_PERFCOUNTER1_SELECT1__SI                   0x268B
#define mmCB_PERFCOUNTER1_SELECT__CI__VI                0xDC03
#define mmCB_PERFCOUNTER2_HI__CI__VI                    0xD40B
#define mmCB_PERFCOUNTER2_HI__SI                        0x2695
#define mmCB_PERFCOUNTER2_LO__CI__VI                    0xD40A
#define mmCB_PERFCOUNTER2_LO__SI                        0x2694
#define mmCB_PERFCOUNTER2_SELECT0__SI                   0x268C
#define mmCB_PERFCOUNTER2_SELECT1__SI                   0x268D
#define mmCB_PERFCOUNTER2_SELECT__CI__VI                0xDC04
#define mmCB_PERFCOUNTER3_HI__CI__VI                    0xD40D
#define mmCB_PERFCOUNTER3_HI__SI                        0x2697
#define mmCB_PERFCOUNTER3_LO__CI__VI                    0xD40C
#define mmCB_PERFCOUNTER3_LO__SI                        0x2696
#define mmCB_PERFCOUNTER3_SELECT0__SI                   0x268E
#define mmCB_PERFCOUNTER3_SELECT1__SI                   0x268F
#define mmCB_PERFCOUNTER3_SELECT__CI__VI                0xDC05
#define mmCB_PERFCOUNTER_FILTER__CI__VI                 0xDC00
#define mmCB_SHADER_MASK                                0xA08F
#define mmCB_TARGET_MASK                                0xA08E
#define mmCC_DRM_ID_STRAPS                              0x1559
#define mmCC_GC_EDC_CONFIG__CI__VI                      0x3098
#define mmCC_GC_PRIM_CONFIG__CI__VI                     0x2240
#define mmCC_GC_SHADER_ARRAY_CONFIG                     0x226F
#define mmCC_MC_MAX_CHANNEL                             0x096E
#define mmCC_RB_BACKEND_DISABLE                         0x263D
#define mmCC_RB_DAISY_CHAIN                             0x2641
#define mmCC_RB_REDUNDANCY                              0x263C
#define mmCC_SQC_BANK_DISABLE                           0x2307
#define mmCC_SYS_RB_BACKEND_DISABLE                     0x03A0
#define mmCC_SYS_RB_REDUNDANCY                          0x039F
#define mmCGTS_CU0_LDS_SQ_CTRL_REG__CI__VI              0xF009
#define mmCGTS_CU0_SP0_CTRL_REG__CI__VI                 0xF008
#define mmCGTS_CU0_SP1_CTRL_REG__CI__VI                 0xF00B
#define mmCGTS_CU0_TA_SQC_CTRL_REG__CI__VI              0xF00A
#define mmCGTS_CU0_TD_TCP_CTRL_REG__CI__VI              0xF00C
#define mmCGTS_CU10_LDS_SQ_CTRL_REG__CI__VI             0xF03B
#define mmCGTS_CU10_SP0_CTRL_REG__CI__VI                0xF03A
#define mmCGTS_CU10_SP1_CTRL_REG__CI__VI                0xF03D
#define mmCGTS_CU10_TA_CTRL_REG__CI__VI                 0xF03C
#define mmCGTS_CU10_TD_TCP_CTRL_REG__CI__VI             0xF03E
#define mmCGTS_CU11_LDS_SQ_CTRL_REG__CI__VI             0xF040
#define mmCGTS_CU11_SP0_CTRL_REG__CI__VI                0xF03F
#define mmCGTS_CU11_SP1_CTRL_REG__CI__VI                0xF042
#define mmCGTS_CU11_TA_CTRL_REG__CI__VI                 0xF041
#define mmCGTS_CU11_TD_TCP_CTRL_REG__CI__VI             0xF043
#define mmCGTS_CU12_LDS_SQ_CTRL_REG__CI__VI             0xF045
#define mmCGTS_CU12_SP0_CTRL_REG__CI__VI                0xF044
#define mmCGTS_CU12_SP1_CTRL_REG__CI__VI                0xF047
#define mmCGTS_CU12_TA_SQC_CTRL_REG__CI__VI             0xF046
#define mmCGTS_CU12_TD_TCP_CTRL_REG__CI__VI             0xF048
#define mmCGTS_CU13_LDS_SQ_CTRL_REG__CI__VI             0xF04A
#define mmCGTS_CU13_SP0_CTRL_REG__CI__VI                0xF049
#define mmCGTS_CU13_SP1_CTRL_REG__CI__VI                0xF04C
#define mmCGTS_CU13_TA_CTRL_REG__CI__VI                 0xF04B
#define mmCGTS_CU13_TD_TCP_CTRL_REG__CI__VI             0xF04D
#define mmCGTS_CU14_LDS_SQ_CTRL_REG__CI__VI             0xF04F
#define mmCGTS_CU14_SP0_CTRL_REG__CI__VI                0xF04E
#define mmCGTS_CU14_SP1_CTRL_REG__CI__VI                0xF051
#define mmCGTS_CU14_TA_CTRL_REG__CI__VI                 0xF050
#define mmCGTS_CU14_TD_TCP_CTRL_REG__CI__VI             0xF052
#define mmCGTS_CU15_LDS_SQ_CTRL_REG__CI__VI             0xF054
#define mmCGTS_CU15_SP0_CTRL_REG__CI__VI                0xF053
#define mmCGTS_CU15_SP1_CTRL_REG__CI__VI                0xF056
#define mmCGTS_CU15_TA_CTRL_REG__CI__VI                 0xF055
#define mmCGTS_CU15_TD_TCP_CTRL_REG__CI__VI             0xF057
#define mmCGTS_CU1_LDS_SQ_CTRL_REG__CI__VI              0xF00E
#define mmCGTS_CU1_SP0_CTRL_REG__CI__VI                 0xF00D
#define mmCGTS_CU1_SP1_CTRL_REG__CI__VI                 0xF010
#define mmCGTS_CU1_TA_CTRL_REG__CI__VI                  0xF00F
#define mmCGTS_CU1_TD_TCP_CTRL_REG__CI__VI              0xF011
#define mmCGTS_CU2_LDS_SQ_CTRL_REG__CI__VI              0xF013
#define mmCGTS_CU2_SP0_CTRL_REG__CI__VI                 0xF012
#define mmCGTS_CU2_SP1_CTRL_REG__CI__VI                 0xF015
#define mmCGTS_CU2_TA_CTRL_REG__CI__VI                  0xF014
#define mmCGTS_CU2_TD_TCP_CTRL_REG__CI__VI              0xF016
#define mmCGTS_CU3_LDS_SQ_CTRL_REG__CI__VI              0xF018
#define mmCGTS_CU3_SP0_CTRL_REG__CI__VI                 0xF017
#define mmCGTS_CU3_SP1_CTRL_REG__CI__VI                 0xF01A
#define mmCGTS_CU3_TA_CTRL_REG__CI__VI                  0xF019
#define mmCGTS_CU3_TD_TCP_CTRL_REG__CI__VI              0xF01B
#define mmCGTS_CU4_LDS_SQ_CTRL_REG__CI__VI              0xF01D
#define mmCGTS_CU4_SP0_CTRL_REG__CI__VI                 0xF01C
#define mmCGTS_CU4_SP1_CTRL_REG__CI__VI                 0xF01F
#define mmCGTS_CU4_TA_SQC_CTRL_REG__CI__VI              0xF01E
#define mmCGTS_CU4_TD_TCP_CTRL_REG__CI__VI              0xF020
#define mmCGTS_CU5_LDS_SQ_CTRL_REG__CI__VI              0xF022
#define mmCGTS_CU5_SP0_CTRL_REG__CI__VI                 0xF021
#define mmCGTS_CU5_SP1_CTRL_REG__CI__VI                 0xF024
#define mmCGTS_CU5_TA_CTRL_REG__CI__VI                  0xF023
#define mmCGTS_CU5_TD_TCP_CTRL_REG__CI__VI              0xF025
#define mmCGTS_CU6_LDS_SQ_CTRL_REG__CI__VI              0xF027
#define mmCGTS_CU6_SP0_CTRL_REG__CI__VI                 0xF026
#define mmCGTS_CU6_SP1_CTRL_REG__CI__VI                 0xF029
#define mmCGTS_CU6_TA_CTRL_REG__CI__VI                  0xF028
#define mmCGTS_CU6_TD_TCP_CTRL_REG__CI__VI              0xF02A
#define mmCGTS_CU7_LDS_SQ_CTRL_REG__CI__VI              0xF02C
#define mmCGTS_CU7_SP0_CTRL_REG__CI__VI                 0xF02B
#define mmCGTS_CU7_SP1_CTRL_REG__CI__VI                 0xF02E
#define mmCGTS_CU7_TA_CTRL_REG__CI__VI                  0xF02D
#define mmCGTS_CU7_TD_TCP_CTRL_REG__CI__VI              0xF02F
#define mmCGTS_CU8_LDS_SQ_CTRL_REG__CI__VI              0xF031
#define mmCGTS_CU8_SP0_CTRL_REG__CI__VI                 0xF030
#define mmCGTS_CU8_SP1_CTRL_REG__CI__VI                 0xF033
#define mmCGTS_CU8_TA_SQC_CTRL_REG__CI__VI              0xF032
#define mmCGTS_CU8_TD_TCP_CTRL_REG__CI__VI              0xF034
#define mmCGTS_CU9_LDS_SQ_CTRL_REG__CI__VI              0xF036
#define mmCGTS_CU9_SP0_CTRL_REG__CI__VI                 0xF035
#define mmCGTS_CU9_SP1_CTRL_REG__CI__VI                 0xF038
#define mmCGTS_CU9_TA_CTRL_REG__CI__VI                  0xF037
#define mmCGTS_CU9_TD_TCP_CTRL_REG__CI__VI              0xF039
#define mmCGTS_RD_CTRL_REG__CI__VI                      0xF001
#define mmCGTS_RD_CTRL_REG__SI                          0x2455
#define mmCGTS_RD_REG__CI__VI                           0xF002
#define mmCGTS_RD_REG__SI                               0x2456
#define mmCGTS_SM_CTRL_REG__CI__VI                      0xF000
#define mmCGTS_SM_CTRL_REG__SI                          0x2454
#define mmCGTS_TCC_DISABLE__CI__VI                      0xF003
#define mmCGTS_TCC_DISABLE__SI                          0x2452
#define mmCGTS_USER_TCC_DISABLE__CI__VI                 0xF004
#define mmCGTS_USER_TCC_DISABLE__SI                     0x2453
#define mmCGTT_BCI_CLK_CTRL__CI__VI                     0xF082
#define mmCGTT_BCI_CLK_CTRL__SI                         0x24A9
#define mmCGTT_CPC_CLK_CTRL__CI__VI                     0xF0B2
#define mmCGTT_CPF_CLK_CTRL__CI__VI                     0xF0B1
#define mmCGTT_CP_CLK_CTRL__CI__VI                      0xF0B0
#define mmCGTT_CP_CLK_CTRL__SI                          0x3059
#define mmCGTT_GDS_CLK_CTRL__CI__VI                     0xF0A0
#define mmCGTT_GDS_CLK_CTRL__SI                         0x25DD
#define mmCGTT_IA_CLK_CTRL__CI__VI                      0xF085
#define mmCGTT_IA_CLK_CTRL__SI                          0x2261
#define mmCGTT_PA_CLK_CTRL__CI__VI                      0xF088
#define mmCGTT_PA_CLK_CTRL__SI                          0x2286
#define mmCGTT_PC_CLK_CTRL__CI__VI                      0xF081
#define mmCGTT_PC_CLK_CTRL__SI                          0x24A8
#define mmCGTT_RLC_CLK_CTRL__CI__VI                     0xF0B8
#define mmCGTT_RLC_CLK_CTRL__SI                         0x30E0
#define mmCGTT_ROM_CLK_CTRL0__SI                        0x0583
#define mmCGTT_SC_CLK_CTRL__CI__VI                      0xF089
#define mmCGTT_SC_CLK_CTRL__SI                          0x22CA
#define mmCGTT_SPI_CLK_CTRL__CI__VI                     0xF080
#define mmCGTT_SPI_CLK_CTRL__SI                         0x2451
#define mmCGTT_SQG_CLK_CTRL__CI__VI                     0xF08D
#define mmCGTT_SQG_CLK_CTRL__SI                         0x2363
#define mmCGTT_SQ_CLK_CTRL__CI__VI                      0xF08C
#define mmCGTT_SQ_CLK_CTRL__SI                          0x2362
#define mmCGTT_SX_CLK_CTRL0__CI__VI                     0xF094
#define mmCGTT_SX_CLK_CTRL0__SI                         0x240C
#define mmCGTT_SX_CLK_CTRL1__CI__VI                     0xF095
#define mmCGTT_SX_CLK_CTRL1__SI                         0x240D
#define mmCGTT_SX_CLK_CTRL2__CI__VI                     0xF096
#define mmCGTT_SX_CLK_CTRL2__SI                         0x240E
#define mmCGTT_SX_CLK_CTRL3__CI__VI                     0xF097
#define mmCGTT_SX_CLK_CTRL3__SI                         0x240F
#define mmCGTT_SX_CLK_CTRL4__CI__VI                     0xF098
#define mmCGTT_SX_CLK_CTRL4__SI                         0x2410
#define mmCGTT_TCI_CLK_CTRL__CI__VI                     0xF09F
#define mmCGTT_TCI_CLK_CTRL__SI                         0x2B60
#define mmCGTT_TCP_CLK_CTRL__CI__VI                     0xF09E
#define mmCGTT_TCP_CLK_CTRL__SI                         0x2B15
#define mmCGTT_VGT_CLK_CTRL__CI__VI                     0xF084
#define mmCGTT_VGT_CLK_CTRL__SI                         0x225F
#define mmCGTT_WD_CLK_CTRL__CI__VI                      0xF086
#define mmCG_CLKPIN_CNTL__SI                            0x0198
#define mmCG_DISPLAY_GAP_CNTL__SI                       0x020A
#define mmCG_FDO_CTRL0__SI                              0x01D5
#define mmCG_FDO_CTRL1__SI                              0x01D6
#define mmCG_FDO_CTRL2__SI                              0x01D7
#define mmCG_FPS_CNT__CI                                0x0194
#define mmCG_FREQ_TRAN_VOTING__SI                       0x01EF
#define mmCG_MULT_THERMAL_CTRL__SI                      0x01C4
#define mmCG_MULT_THERMAL_STATUS__SI                    0x01C5
#define mmCG_SPLL_FUNC_CNTL_2__SI                       0x0181
#define mmCG_SPLL_FUNC_CNTL_3__SI                       0x0182
#define mmCG_SPLL_FUNC_CNTL_4__SI                       0x0183
#define mmCG_SPLL_FUNC_CNTL_5__SI                       0x0184
#define mmCG_SPLL_FUNC_CNTL__SI                         0x0180
#define mmCG_SPLL_SPREAD_SPECTRUM_2__SI                 0x0189
#define mmCG_SPLL_SPREAD_SPECTRUM__SI                   0x0188
#define mmCG_STATIC_SCREEN_PARAMETER__SI                0x0203
#define mmCG_TACH_CTRL__SI                              0x01DC
#define mmCG_TACH_STATUS__SI                            0x01DD
#define mmCG_THERMAL_CTRL__SI                           0x01C0
#define mmCG_THERMAL_INT__SI                            0x01C2
#define mmCG_THERMAL_STATUS__SI                         0x01C1
#define mmCG_ULV_PARAMETER__SI                          0x021F
#define mmCHUB_ATC_PERFCOUNTER0_CFG__CI__VI             0x07D8
#define mmCHUB_ATC_PERFCOUNTER1_CFG__CI__VI             0x07D9
#define mmCHUB_ATC_PERFCOUNTER_HI__CI__VI               0x07D7
#define mmCHUB_ATC_PERFCOUNTER_LO__CI__VI               0x07D6
#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI        0x07DA
#define mmCLKREQB_PAD_CNTL__CI__VI                      0x1521
#define mmCOHER_DEST_BASE_0                             0xA092
#define mmCOHER_DEST_BASE_1                             0xA093
#define mmCOHER_DEST_BASE_2                             0xA07E
#define mmCOHER_DEST_BASE_3                             0xA07F
#define mmCOHER_DEST_BASE_HI_0__CI__VI                  0xA07A
#define mmCOHER_DEST_BASE_HI_1__CI__VI                  0xA07B
#define mmCOHER_DEST_BASE_HI_2__CI__VI                  0xA07C
#define mmCOHER_DEST_BASE_HI_3__CI__VI                  0xA07D
#define mmCOMPUTE_DIM_X                                 0x2E01
#define mmCOMPUTE_DIM_Y                                 0x2E02
#define mmCOMPUTE_DIM_Z                                 0x2E03
#define mmCOMPUTE_DISPATCH_INITIATOR                    0x2E00
#define mmCOMPUTE_MISC_RESERVED__CI__VI                 0x2E1F
#define mmCOMPUTE_NUM_THREAD_X                          0x2E07
#define mmCOMPUTE_NUM_THREAD_Y                          0x2E08
#define mmCOMPUTE_NUM_THREAD_Z                          0x2E09
#define mmCOMPUTE_PERFCOUNT_ENABLE__CI__VI              0x2E0B
#define mmCOMPUTE_PGM_HI                                0x2E0D
#define mmCOMPUTE_PGM_LO                                0x2E0C
#define mmCOMPUTE_PGM_RSRC1                             0x2E12
#define mmCOMPUTE_PGM_RSRC2                             0x2E13
#define mmCOMPUTE_PIPELINESTAT_ENABLE__CI__VI           0x2E0A
#define mmCOMPUTE_RESOURCE_LIMITS                       0x2E15
#define mmCOMPUTE_RESTART_X__CI__VI                     0x2E1B
#define mmCOMPUTE_RESTART_Y__CI__VI                     0x2E1C
#define mmCOMPUTE_RESTART_Z__CI__VI                     0x2E1D
#define mmCOMPUTE_START_X                               0x2E04
#define mmCOMPUTE_START_Y                               0x2E05
#define mmCOMPUTE_START_Z                               0x2E06
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                0x2E16
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                0x2E17
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI        0x2E19
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI        0x2E1A
#define mmCOMPUTE_TBA_HI                                0x2E0F
#define mmCOMPUTE_TBA_LO                                0x2E0E
#define mmCOMPUTE_THREAD_TRACE_ENABLE__CI__VI           0x2E1E
#define mmCOMPUTE_TMA_HI                                0x2E11
#define mmCOMPUTE_TMA_LO                                0x2E10
#define mmCOMPUTE_TMPRING_SIZE                          0x2E18
#define mmCOMPUTE_USER_DATA_0                           0x2E40
#define mmCOMPUTE_USER_DATA_1                           0x2E41
#define mmCOMPUTE_USER_DATA_10                          0x2E4A
#define mmCOMPUTE_USER_DATA_11                          0x2E4B
#define mmCOMPUTE_USER_DATA_12                          0x2E4C
#define mmCOMPUTE_USER_DATA_13                          0x2E4D
#define mmCOMPUTE_USER_DATA_14                          0x2E4E
#define mmCOMPUTE_USER_DATA_15                          0x2E4F
#define mmCOMPUTE_USER_DATA_2                           0x2E42
#define mmCOMPUTE_USER_DATA_3                           0x2E43
#define mmCOMPUTE_USER_DATA_4                           0x2E44
#define mmCOMPUTE_USER_DATA_5                           0x2E45
#define mmCOMPUTE_USER_DATA_6                           0x2E46
#define mmCOMPUTE_USER_DATA_7                           0x2E47
#define mmCOMPUTE_USER_DATA_8                           0x2E48
#define mmCOMPUTE_USER_DATA_9                           0x2E49
#define mmCOMPUTE_VMID                                  0x2E14
#define mmCONFIG_APER_SIZE                              0x150C
#define mmCONFIG_CNTL                                   0x1509
#define mmCONFIG_F0_BASE                                0x150B
#define mmCONFIG_MEMSIZE                                0x150A
#define mmCONFIG_REG_APER_SIZE                          0x150D
#define mmCPC1_CONFIG__CI                               0x0F97
#define mmCPC2_CONFIG__CI                               0x0F98
#define mmCPC_INT_CNTL__CI__VI                          0x30B4
#define mmCPC_INT_CNTX_ID__CI__VI                       0x30B7
#define mmCPC_INT_STATUS__CI__VI                        0x30B5
#define mmCPC_PERFCOUNTER0_HI__CI__VI                   0xD007
#define mmCPC_PERFCOUNTER0_LO__CI__VI                   0xD006
#define mmCPC_PERFCOUNTER0_SELECT1__CI__VI              0xD804
#define mmCPC_PERFCOUNTER0_SELECT__CI__VI               0xD809
#define mmCPC_PERFCOUNTER1_HI__CI__VI                   0xD005
#define mmCPC_PERFCOUNTER1_LO__CI__VI                   0xD004
#define mmCPC_PERFCOUNTER1_SELECT__CI__VI               0xD803
#define mmCPF_PERFCOUNTER0_HI__CI__VI                   0xD00B
#define mmCPF_PERFCOUNTER0_LO__CI__VI                   0xD00A
#define mmCPF_PERFCOUNTER0_SELECT1__CI__VI              0xD806
#define mmCPF_PERFCOUNTER0_SELECT__CI__VI               0xD807
#define mmCPF_PERFCOUNTER1_HI__CI__VI                   0xD009
#define mmCPF_PERFCOUNTER1_LO__CI__VI                   0xD008
#define mmCPF_PERFCOUNTER1_SELECT__CI__VI               0xD805
#define mmCPG_CONFIG__CI                                0x0F96
#define mmCPG_PERFCOUNTER0_HI__CI__VI                   0xD003
#define mmCPG_PERFCOUNTER0_LO__CI__VI                   0xD002
#define mmCPG_PERFCOUNTER0_SELECT1__CI__VI              0xD801
#define mmCPG_PERFCOUNTER0_SELECT__CI__VI               0xD802
#define mmCPG_PERFCOUNTER1_HI__CI__VI                   0xD001
#define mmCPG_PERFCOUNTER1_LO__CI__VI                   0xD000
#define mmCPG_PERFCOUNTER1_SELECT__CI__VI               0xD800
#define mmCP_APPEND_ADDR_HI__CI__VI                     0xC059
#define mmCP_APPEND_ADDR_HI__SI                         0x2159
#define mmCP_APPEND_ADDR_LO__CI__VI                     0xC058
#define mmCP_APPEND_ADDR_LO__SI                         0x2158
#define mmCP_APPEND_DATA__CI__VI                        0xC05A
#define mmCP_APPEND_DATA__SI                            0x215A
#define mmCP_APPEND_LAST_CS_FENCE__CI__VI               0xC05B
#define mmCP_APPEND_LAST_CS_FENCE__SI                   0x215B
#define mmCP_APPEND_LAST_PS_FENCE__CI__VI               0xC05C
#define mmCP_APPEND_LAST_PS_FENCE__SI                   0x215C
#define mmCP_ATOMIC_PREOP_HI__CI__VI                    0xC05E
#define mmCP_ATOMIC_PREOP_HI__SI                        0x215E
#define mmCP_ATOMIC_PREOP_LO__CI__VI                    0xC05D
#define mmCP_ATOMIC_PREOP_LO__SI                        0x215D
#define mmCP_BUSY_STAT                                  0x219F
#define mmCP_CEQ1_AVAIL                                 0x21E6
#define mmCP_CEQ2_AVAIL                                 0x21E7
#define mmCP_CE_COMPARE_COUNT__CI__VI                   0x20C0
#define mmCP_CE_COUNTER__CI__VI                         0xC09A
#define mmCP_CE_DE_COUNT__CI__VI                        0x20C1
#define mmCP_CE_HEADER_DUMP                             0x21A4
#define mmCP_CE_IB1_BASE_HI__CI__VI                     0xC0C7
#define mmCP_CE_IB1_BASE_HI__SI                         0x21C7
#define mmCP_CE_IB1_BASE_LO__CI__VI                     0xC0C6
#define mmCP_CE_IB1_BASE_LO__SI                         0x21C6
#define mmCP_CE_IB1_BUFSZ__CI__VI                       0xC0C8
#define mmCP_CE_IB1_BUFSZ__SI                           0x21C8
#define mmCP_CE_IB1_OFFSET__CI__VI                      0xC098
#define mmCP_CE_IB2_BASE_HI__CI__VI                     0xC0CA
#define mmCP_CE_IB2_BASE_HI__SI                         0x21CA
#define mmCP_CE_IB2_BASE_LO__CI__VI                     0xC0C9
#define mmCP_CE_IB2_BASE_LO__SI                         0x21C9
#define mmCP_CE_IB2_BUFSZ__CI__VI                       0xC0CB
#define mmCP_CE_IB2_BUFSZ__SI                           0x21CB
#define mmCP_CE_IB2_OFFSET__CI__VI                      0xC099
#define mmCP_CE_INIT_BASE_HI__CI__VI                    0xC0C4
#define mmCP_CE_INIT_BASE_HI__SI                        0x21C4
#define mmCP_CE_INIT_BASE_LO__CI__VI                    0xC0C3
#define mmCP_CE_INIT_BASE_LO__SI                        0x21C3
#define mmCP_CE_INIT_BUFSZ__CI__VI                      0xC0C5
#define mmCP_CE_INIT_BUFSZ__SI                          0x21C5
#define mmCP_CE_INTR_ROUTINE_START__CI__VI              0x30A8
#define mmCP_CE_PRGRM_CNTR_START__CI__VI                0x30A3
#define mmCP_CE_ROQ_IB1_STAT                            0x21E9
#define mmCP_CE_ROQ_IB2_STAT                            0x21EA
#define mmCP_CE_ROQ_RB_STAT                             0x21E8
#define mmCP_CMD_DATA                                   0x21DF
#define mmCP_CMD_INDEX                                  0x21DE
#define mmCP_CNTX_STAT                                  0x21B8
#define mmCP_COHER_BASE_HI__CI__VI                      0xC079
#define mmCP_COHER_BASE__CI__VI                         0xC07E
#define mmCP_COHER_BASE__SI                             0x217E
#define mmCP_COHER_CNTL__CI__VI                         0xC07C
#define mmCP_COHER_CNTL__SI                             0x217C
#define mmCP_COHER_SIZE_HI__CI__VI                      0xC08C
#define mmCP_COHER_SIZE__CI__VI                         0xC07D
#define mmCP_COHER_SIZE__SI                             0x217D
#define mmCP_COHER_START_DELAY__CI__VI                  0xC07B
#define mmCP_COHER_START_DELAY__SI                      0x217B
#define mmCP_COHER_STATUS__CI__VI                       0xC07F
#define mmCP_COHER_STATUS__SI                           0x217F
#define mmCP_CONFIG__SI                                 0x0F92
#define mmCP_CONTEXT_CNTL__CI__VI                       0x30AD
#define mmCP_CPC_BUSY_STAT__CI__VI                      0x2085
#define mmCP_CPC_GRBM_FREE_COUNT__CI__VI                0x208B
#define mmCP_CPC_HALT_HYST_COUNT__CI__VI                0x20A7
#define mmCP_CPC_MC_CNTL__CI                            0x208A
#define mmCP_CPC_SCRATCH_DATA__CI__VI                   0x2091
#define mmCP_CPC_SCRATCH_INDEX__CI__VI                  0x2090
#define mmCP_CPC_STALLED_STAT1__CI__VI                  0x2086
#define mmCP_CPC_STATUS__CI__VI                         0x2084
#define mmCP_CPF_BUSY_STAT__CI__VI                      0x2088
#define mmCP_CPF_STALLED_STAT1__CI__VI                  0x2089
#define mmCP_CPF_STATUS__CI__VI                         0x2087
#define mmCP_CSF_CNTL                                   0x21B5
#define mmCP_CSF_STAT                                   0x21B4
#define mmCP_DEBUG                                      0x307F
#define mmCP_DEVICE_ID__CI__VI                          0x304B
#define mmCP_DE_CE_COUNT__CI__VI                        0x20C2
#define mmCP_DE_DE_COUNT__CI__VI                        0x20C4
#define mmCP_DE_LAST_INVAL_COUNT__CI__VI                0x20C3
#define mmCP_DFY_ADDR_HI__CI__VI                        0x3022
#define mmCP_DFY_ADDR_LO__CI__VI                        0x3023
#define mmCP_DFY_CNTL__CI__VI                           0x3020
#define mmCP_DFY_DATA_0__CI__VI                         0x3024
#define mmCP_DFY_DATA_10__CI__VI                        0x302E
#define mmCP_DFY_DATA_11__CI__VI                        0x302F
#define mmCP_DFY_DATA_12__CI__VI                        0x3030
#define mmCP_DFY_DATA_13__CI__VI                        0x3031
#define mmCP_DFY_DATA_14__CI__VI                        0x3032
#define mmCP_DFY_DATA_15__CI__VI                        0x3033
#define mmCP_DFY_DATA_1__CI__VI                         0x3025
#define mmCP_DFY_DATA_2__CI__VI                         0x3026
#define mmCP_DFY_DATA_3__CI__VI                         0x3027
#define mmCP_DFY_DATA_4__CI__VI                         0x3028
#define mmCP_DFY_DATA_5__CI__VI                         0x3029
#define mmCP_DFY_DATA_6__CI__VI                         0x302A
#define mmCP_DFY_DATA_7__CI__VI                         0x302B
#define mmCP_DFY_DATA_8__CI__VI                         0x302C
#define mmCP_DFY_DATA_9__CI__VI                         0x302D
#define mmCP_DFY_STAT__CI__VI                           0x3021
#define mmCP_DMA_CNTL__CI__VI                           0xC08A
#define mmCP_DMA_CNTL__SI                               0x218A
#define mmCP_DMA_ME_COMMAND__CI__VI                     0xC084
#define mmCP_DMA_ME_COMMAND__SI                         0x2184
#define mmCP_DMA_ME_CONTROL__CI__VI                     0xC078
#define mmCP_DMA_ME_DST_ADDR_HI__CI__VI                 0xC083
#define mmCP_DMA_ME_DST_ADDR_HI__SI                     0x2183
#define mmCP_DMA_ME_DST_ADDR__CI__VI                    0xC082
#define mmCP_DMA_ME_DST_ADDR__SI                        0x2182
#define mmCP_DMA_ME_SRC_ADDR_HI__CI__VI                 0xC081
#define mmCP_DMA_ME_SRC_ADDR_HI__SI                     0x2181
#define mmCP_DMA_ME_SRC_ADDR__CI__VI                    0xC080
#define mmCP_DMA_ME_SRC_ADDR__SI                        0x2180
#define mmCP_DMA_PFP_COMMAND__CI__VI                    0xC089
#define mmCP_DMA_PFP_COMMAND__SI                        0x2189
#define mmCP_DMA_PFP_CONTROL__CI__VI                    0xC077
#define mmCP_DMA_PFP_DST_ADDR_HI__CI__VI                0xC088
#define mmCP_DMA_PFP_DST_ADDR_HI__SI                    0x2188
#define mmCP_DMA_PFP_DST_ADDR__CI__VI                   0xC087
#define mmCP_DMA_PFP_DST_ADDR__SI                       0x2187
#define mmCP_DMA_PFP_SRC_ADDR_HI__CI__VI                0xC086
#define mmCP_DMA_PFP_SRC_ADDR_HI__SI                    0x2186
#define mmCP_DMA_PFP_SRC_ADDR__CI__VI                   0xC085
#define mmCP_DMA_PFP_SRC_ADDR__SI                       0x2185
#define mmCP_DMA_READ_TAGS__CI__VI                      0xC08B
#define mmCP_DMA_READ_TAGS__SI                          0x218B
#define mmCP_ECC_FIRSTOCCURRENCE                        0x307A
#define mmCP_ECC_FIRSTOCCURRENCE_RING0                  0x307B
#define mmCP_ECC_FIRSTOCCURRENCE_RING1                  0x307C
#define mmCP_ECC_FIRSTOCCURRENCE_RING2                  0x307D
#define mmCP_ENDIAN_SWAP__CI__VI                        0x3050
#define mmCP_EOP_DONE_ADDR_HI__CI__VI                   0xC001
#define mmCP_EOP_DONE_ADDR_HI__SI                       0x2101
#define mmCP_EOP_DONE_ADDR_LO__CI__VI                   0xC000
#define mmCP_EOP_DONE_ADDR_LO__SI                       0x2100
#define mmCP_EOP_DONE_DATA_CNTL__CI__VI                 0xC0D6
#define mmCP_EOP_DONE_DATA_HI__CI__VI                   0xC003
#define mmCP_EOP_DONE_DATA_HI__SI                       0x2103
#define mmCP_EOP_DONE_DATA_LO__CI__VI                   0xC002
#define mmCP_EOP_DONE_DATA_LO__SI                       0x2102
#define mmCP_EOP_DONE_EVENT_CNTL__CI__VI                0xC0D5
#define mmCP_EOP_LAST_FENCE_HI__CI__VI                  0xC005
#define mmCP_EOP_LAST_FENCE_HI__SI                      0x2105
#define mmCP_EOP_LAST_FENCE_LO__CI__VI                  0xC004
#define mmCP_EOP_LAST_FENCE_LO__SI                      0x2104
#define mmCP_FETCHER_SOURCE__CI                         0x3082
#define mmCP_GDS_ATOMIC0_PREOP_HI__CI__VI               0xC060
#define mmCP_GDS_ATOMIC0_PREOP_HI__SI                   0x2160
#define mmCP_GDS_ATOMIC0_PREOP_LO__CI__VI               0xC05F
#define mmCP_GDS_ATOMIC0_PREOP_LO__SI                   0x215F
#define mmCP_GDS_ATOMIC1_PREOP_HI__CI__VI               0xC062
#define mmCP_GDS_ATOMIC1_PREOP_HI__SI                   0x2162
#define mmCP_GDS_ATOMIC1_PREOP_LO__CI__VI               0xC061
#define mmCP_GDS_ATOMIC1_PREOP_LO__SI                   0x2161
#define mmCP_GRBM_FREE_COUNT                            0x21A3
#define mmCP_HPD_EOP_BASE_ADDR_HI__CI                   0x3242
#define mmCP_HPD_EOP_BASE_ADDR__CI                      0x3241
#define mmCP_HPD_EOP_CONTROL__CI                        0x3244
#define mmCP_HPD_EOP_VMID__CI                           0x3243
#define mmCP_HPD_ROQ_OFFSETS__CI__VI                    0x3240
#define mmCP_HQD_ACTIVE__CI__VI                         0x3247
#define mmCP_HQD_ATOMIC0_PREOP_HI__CI__VI               0x3262
#define mmCP_HQD_ATOMIC0_PREOP_LO__CI__VI               0x3261
#define mmCP_HQD_ATOMIC1_PREOP_HI__CI__VI               0x3264
#define mmCP_HQD_ATOMIC1_PREOP_LO__CI__VI               0x3263
#define mmCP_HQD_DEQUEUE_REQUEST__CI__VI                0x325D
#define mmCP_HQD_DMA_OFFLOAD__CI__VI                    0x325E
#define mmCP_HQD_HQ_SCHEDULER0__CI__VI                  0x3265
#define mmCP_HQD_HQ_SCHEDULER1__CI__VI                  0x3266
#define mmCP_HQD_IB_BASE_ADDR_HI__CI__VI                0x3258
#define mmCP_HQD_IB_BASE_ADDR__CI__VI                   0x3257
#define mmCP_HQD_IB_CONTROL__CI__VI                     0x325A
#define mmCP_HQD_IB_RPTR__CI__VI                        0x3259
#define mmCP_HQD_IQ_RPTR__CI__VI                        0x325C
#define mmCP_HQD_IQ_TIMER__CI__VI                       0x325B
#define mmCP_HQD_MSG_TYPE__CI__VI                       0x3260
#define mmCP_HQD_PERSISTENT_STATE__CI__VI               0x3249
#define mmCP_HQD_PIPE_PRIORITY__CI__VI                  0x324A
#define mmCP_HQD_PQ_BASE_HI__CI__VI                     0x324E
#define mmCP_HQD_PQ_BASE__CI__VI                        0x324D
#define mmCP_HQD_PQ_CONTROL__CI__VI                     0x3256
#define mmCP_HQD_PQ_DOORBELL_CONTROL__CI__VI            0x3254
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI         0x3251
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI            0x3250
#define mmCP_HQD_PQ_RPTR__CI__VI                        0x324F
#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI           0x3253
#define mmCP_HQD_PQ_WPTR_POLL_ADDR__CI__VI              0x3252
#define mmCP_HQD_PQ_WPTR__CI__VI                        0x3255
#define mmCP_HQD_QUANTUM__CI__VI                        0x324C
#define mmCP_HQD_QUEUE_PRIORITY__CI__VI                 0x324B
#define mmCP_HQD_SEMA_CMD__CI__VI                       0x325F
#define mmCP_HQD_VMID__CI__VI                           0x3248
#define mmCP_IB1_BASE_HI__CI__VI                        0xC0CD
#define mmCP_IB1_BASE_HI__SI                            0x21CD
#define mmCP_IB1_BASE_LO__CI__VI                        0xC0CC
#define mmCP_IB1_BASE_LO__SI                            0x21CC
#define mmCP_IB1_BUFSZ__CI__VI                          0xC0CE
#define mmCP_IB1_BUFSZ__SI                              0x21CE
#define mmCP_IB1_OFFSET__CI__VI                         0xC092
#define mmCP_IB1_OFFSET__SI                             0x2192
#define mmCP_IB1_PREAMBLE_BEGIN__CI__VI                 0xC094
#define mmCP_IB1_PREAMBLE_BEGIN__SI                     0x2194
#define mmCP_IB1_PREAMBLE_END__CI__VI                   0xC095
#define mmCP_IB1_PREAMBLE_END__SI                       0x2195
#define mmCP_IB2_BASE_HI__CI__VI                        0xC0D0
#define mmCP_IB2_BASE_HI__SI                            0x21D0
#define mmCP_IB2_BASE_LO__CI__VI                        0xC0CF
#define mmCP_IB2_BASE_LO__SI                            0x21CF
#define mmCP_IB2_BUFSZ__CI__VI                          0xC0D1
#define mmCP_IB2_BUFSZ__SI                              0x21D1
#define mmCP_IB2_OFFSET__CI__VI                         0xC093
#define mmCP_IB2_OFFSET__SI                             0x2193
#define mmCP_IB2_PREAMBLE_BEGIN__CI__VI                 0xC096
#define mmCP_IB2_PREAMBLE_BEGIN__SI                     0x2196
#define mmCP_IB2_PREAMBLE_END__CI__VI                   0xC097
#define mmCP_IB2_PREAMBLE_END__SI                       0x2197
#define mmCP_INT_CNTL                                   0x3049
#define mmCP_INT_CNTL_RING0                             0x306A
#define mmCP_INT_CNTL_RING1                             0x306B
#define mmCP_INT_CNTL_RING2                             0x306C
#define mmCP_INT_STATUS                                 0x304A
#define mmCP_INT_STATUS_RING0                           0x306D
#define mmCP_INT_STATUS_RING1                           0x306E
#define mmCP_INT_STATUS_RING2                           0x306F
#define mmCP_INT_STAT_DEBUG                             0x21F7
#define mmCP_IQ_WAIT_TIME1__CI__VI                      0x30AF
#define mmCP_IQ_WAIT_TIME2__CI__VI                      0x30B0
#define mmCP_MAX_CONTEXT__CI__VI                        0x30AE
#define mmCP_MC_PACK_DELAY_CNT__SI__CI                  0x21A7
#define mmCP_MC_TAG_CNTL__CI                            0x21A8
#define mmCP_MC_TAG_DATA__CI                            0x21A9
#define mmCP_ME0_PIPE0_PRIORITY__CI__VI                 0x304D
#define mmCP_ME0_PIPE0_VMID__CI__VI                     0x3052
#define mmCP_ME0_PIPE1_PRIORITY__CI__VI                 0x304E
#define mmCP_ME0_PIPE1_VMID__CI__VI                     0x3053
#define mmCP_ME0_PIPE2_PRIORITY__CI__VI                 0x304F
#define mmCP_ME0_PIPE_PRIORITY_CNTS__CI__VI             0x304C
#define mmCP_ME1_INT_STAT_DEBUG__CI__VI                 0x3095
#define mmCP_ME1_PIPE0_INT_CNTL__CI__VI                 0x3085
#define mmCP_ME1_PIPE0_INT_STATUS__CI__VI               0x308D
#define mmCP_ME1_PIPE0_PRIORITY__CI__VI                 0x309A
#define mmCP_ME1_PIPE1_INT_CNTL__CI__VI                 0x3086
#define mmCP_ME1_PIPE1_INT_STATUS__CI__VI               0x308E
#define mmCP_ME1_PIPE1_PRIORITY__CI__VI                 0x309B
#define mmCP_ME1_PIPE2_INT_CNTL__CI__VI                 0x3087
#define mmCP_ME1_PIPE2_INT_STATUS__CI__VI               0x308F
#define mmCP_ME1_PIPE2_PRIORITY__CI__VI                 0x309C
#define mmCP_ME1_PIPE3_INT_CNTL__CI__VI                 0x3088
#define mmCP_ME1_PIPE3_INT_STATUS__CI__VI               0x3090
#define mmCP_ME1_PIPE3_PRIORITY__CI__VI                 0x309D
#define mmCP_ME1_PIPE_PRIORITY_CNTS__CI__VI             0x3099
#define mmCP_ME2_INT_STAT_DEBUG__CI__VI                 0x3096
#define mmCP_ME2_PIPE0_INT_CNTL__CI__VI                 0x3089
#define mmCP_ME2_PIPE0_INT_STATUS__CI__VI               0x3091
#define mmCP_ME2_PIPE0_PRIORITY__CI__VI                 0x309F
#define mmCP_ME2_PIPE1_INT_CNTL__CI__VI                 0x308A
#define mmCP_ME2_PIPE1_INT_STATUS__CI__VI               0x3092
#define mmCP_ME2_PIPE1_PRIORITY__CI__VI                 0x30A0
#define mmCP_ME2_PIPE2_INT_CNTL__CI__VI                 0x308B
#define mmCP_ME2_PIPE2_INT_STATUS__CI__VI               0x3093
#define mmCP_ME2_PIPE2_PRIORITY__CI__VI                 0x30A1
#define mmCP_ME2_PIPE3_INT_CNTL__CI__VI                 0x308C
#define mmCP_ME2_PIPE3_INT_STATUS__CI__VI               0x3094
#define mmCP_ME2_PIPE3_PRIORITY__CI__VI                 0x30A2
#define mmCP_ME2_PIPE_PRIORITY_CNTS__CI__VI             0x309E
#define mmCP_MEC1_INTR_ROUTINE_START__CI__VI            0x30AB
#define mmCP_MEC1_PRGRM_CNTR_START__CI__VI              0x30A6
#define mmCP_MEC2_INTR_ROUTINE_START__CI__VI            0x30AC
#define mmCP_MEC2_PRGRM_CNTR_START__CI__VI              0x30A7
#define mmCP_MEC_CNTL__CI__VI                           0x208D
#define mmCP_MEC_ME1_HEADER_DUMP__CI__VI                0x208E
#define mmCP_MEC_ME1_UCODE_ADDR__CI                     0x305C
#define mmCP_MEC_ME1_UCODE_DATA__CI                     0x305D
#define mmCP_MEC_ME2_HEADER_DUMP__CI__VI                0x208F
#define mmCP_MEC_ME2_UCODE_ADDR__CI                     0x305E
#define mmCP_MEC_ME2_UCODE_DATA__CI                     0x305F
#define mmCP_MEM_SLP_CNTL                               0x3079
#define mmCP_MEQ_AVAIL                                  0x21DD
#define mmCP_MEQ_STAT                                   0x21E5
#define mmCP_MEQ_STQ_THRESHOLD__CI__VI                  0x21BD
#define mmCP_MEQ_THRESHOLDS                             0x21D9
#define mmCP_ME_ATOMIC_PREOP_HI__CI__VI                 0xC05E
#define mmCP_ME_ATOMIC_PREOP_LO__CI__VI                 0xC05D
#define mmCP_ME_CNTL                                    0x21B6
#define mmCP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI            0xC060
#define mmCP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI            0xC05F
#define mmCP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI            0xC062
#define mmCP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI            0xC061
#define mmCP_ME_HEADER_DUMP                             0x21A1
#define mmCP_ME_INTR_ROUTINE_START__CI__VI              0x30AA
#define mmCP_ME_MC_RADDR_HI__CI__VI                     0xC06E
#define mmCP_ME_MC_RADDR_HI__SI                         0x216E
#define mmCP_ME_MC_RADDR_LO__CI__VI                     0xC06D
#define mmCP_ME_MC_RADDR_LO__SI                         0x216D
#define mmCP_ME_MC_WADDR_HI__CI__VI                     0xC06A
#define mmCP_ME_MC_WADDR_HI__SI                         0x216A
#define mmCP_ME_MC_WADDR_LO__CI__VI                     0xC069
#define mmCP_ME_MC_WADDR_LO__SI                         0x2169
#define mmCP_ME_MC_WDATA_HI__CI__VI                     0xC06C
#define mmCP_ME_MC_WDATA_HI__SI                         0x216C
#define mmCP_ME_MC_WDATA_LO__CI__VI                     0xC06B
#define mmCP_ME_MC_WDATA_LO__SI                         0x216B
#define mmCP_ME_PREEMPTION                              0x21B9
#define mmCP_ME_PRGRM_CNTR_START__CI__VI                0x30A5
#define mmCP_MQD_BASE_ADDR_HI__CI__VI                   0x3246
#define mmCP_MQD_BASE_ADDR__CI__VI                      0x3245
#define mmCP_MQD_CONTROL__CI__VI                        0x3267
#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI__CI__VI          0xC00B
#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI__SI              0x210B
#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO__CI__VI          0xC00A
#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO__SI              0x210A
#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI__CI__VI          0xC00F
#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI__SI              0x210F
#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO__CI__VI          0xC00E
#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO__SI              0x210E
#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI__CI__VI          0xC013
#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI__SI              0x2113
#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO__CI__VI          0xC012
#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO__SI              0x2112
#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI__CI__VI          0xC017
#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI__SI              0x2117
#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO__CI__VI          0xC016
#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO__SI              0x2116
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI__CI__VI         0xC009
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI__SI             0x2109
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO__CI__VI         0xC008
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO__SI             0x2108
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI__CI__VI         0xC00D
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI__SI             0x210D
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO__CI__VI         0xC00C
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO__SI             0x210C
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI__CI__VI         0xC011
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI__SI             0x2111
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO__CI__VI         0xC010
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO__SI             0x2110
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI__CI__VI         0xC015
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI__SI             0x2115
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO__CI__VI         0xC014
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO__SI             0x2114
#define mmCP_PA_CINVOC_COUNT_HI__CI__VI                 0xC029
#define mmCP_PA_CINVOC_COUNT_HI__SI                     0x2129
#define mmCP_PA_CINVOC_COUNT_LO__CI__VI                 0xC028
#define mmCP_PA_CINVOC_COUNT_LO__SI                     0x2128
#define mmCP_PA_CPRIM_COUNT_HI__CI__VI                  0xC02B
#define mmCP_PA_CPRIM_COUNT_HI__SI                      0x212B
#define mmCP_PA_CPRIM_COUNT_LO__CI__VI                  0xC02A
#define mmCP_PA_CPRIM_COUNT_LO__SI                      0x212A
#define mmCP_PERFCOUNTER_HI__SI                         0x21FE
#define mmCP_PERFCOUNTER_LO__SI                         0x21FD
#define mmCP_PERFCOUNTER_SELECT__SI                     0x21FC
#define mmCP_PERFMON_CNTL__CI__VI                       0xD808
#define mmCP_PERFMON_CNTL__SI                           0x21FF
#define mmCP_PERFMON_CNTX_CNTL                          0xA0D8
#define mmCP_PFP_ATOMIC_PREOP_HI__CI__VI                0xC053
#define mmCP_PFP_ATOMIC_PREOP_LO__CI__VI                0xC052
#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI           0xC055
#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI           0xC054
#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI           0xC057
#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI           0xC056
#define mmCP_PFP_HEADER_DUMP                            0x21A2
#define mmCP_PFP_IB_CONTROL__CI__VI                     0xC08D
#define mmCP_PFP_IB_CONTROL__SI                         0x218D
#define mmCP_PFP_INTR_ROUTINE_START__CI__VI             0x30A9
#define mmCP_PFP_LOAD_CONTROL__CI__VI                   0xC08E
#define mmCP_PFP_LOAD_CONTROL__SI                       0x218E
#define mmCP_PFP_PRGRM_CNTR_START__CI__VI               0x30A4
#define mmCP_PIPEID__CI__VI                             0xA0D9
#define mmCP_PIPE_STATS_ADDR_HI__CI__VI                 0xC019
#define mmCP_PIPE_STATS_ADDR_HI__SI                     0x2119
#define mmCP_PIPE_STATS_ADDR_LO__CI__VI                 0xC018
#define mmCP_PIPE_STATS_ADDR_LO__SI                     0x2118
#define mmCP_PQ_WPTR_POLL_CNTL1__CI__VI                 0x3084
#define mmCP_PQ_WPTR_POLL_CNTL__CI__VI                  0x3083
#define mmCP_PRT_LOD_STATS_CNTL0__CI__VI                0x20AD
#define mmCP_PRT_LOD_STATS_CNTL1__CI__VI                0x20AE
#define mmCP_PRT_LOD_STATS_CNTL2__CI__VI                0x20AF
#define mmCP_PWR_CNTL                                   0x3078
#define mmCP_QUEUE_THRESHOLDS                           0x21D8
#define mmCP_RB0_BASE                                   0x3040
#define mmCP_RB0_BASE_HI__CI__VI                        0x30B1
#define mmCP_RB0_CNTL                                   0x3041
#define mmCP_RB0_RPTR                                   0x21C0
#define mmCP_RB0_RPTR_ADDR                              0x3043
#define mmCP_RB0_RPTR_ADDR_HI                           0x3044
#define mmCP_RB0_WPTR                                   0x3045
#define mmCP_RB1_BASE                                   0x3060
#define mmCP_RB1_BASE_HI__CI__VI                        0x30B2
#define mmCP_RB1_CNTL                                   0x3061
#define mmCP_RB1_RPTR                                   0x21BF
#define mmCP_RB1_RPTR_ADDR                              0x3062
#define mmCP_RB1_RPTR_ADDR_HI                           0x3063
#define mmCP_RB1_WPTR                                   0x3064
#define mmCP_RB2_BASE                                   0x3065
#define mmCP_RB2_CNTL                                   0x3066
#define mmCP_RB2_RPTR                                   0x21BE
#define mmCP_RB2_RPTR_ADDR                              0x3067
#define mmCP_RB2_RPTR_ADDR_HI                           0x3068
#define mmCP_RB2_WPTR                                   0x3069
#define mmCP_RB_BASE                                    0x3040
#define mmCP_RB_CNTL                                    0x3041
#define mmCP_RB_OFFSET__CI__VI                          0xC091
#define mmCP_RB_OFFSET__SI                              0x2191
#define mmCP_RB_RPTR                                    0x21C0
#define mmCP_RB_RPTR_ADDR                               0x3043
#define mmCP_RB_RPTR_ADDR_HI                            0x3044
#define mmCP_RB_RPTR_WR                                 0x3042
#define mmCP_RB_VMID                                    0x3051
#define mmCP_RB_WPTR                                    0x3045
#define mmCP_RB_WPTR_DELAY                              0x21C1
#define mmCP_RB_WPTR_POLL_ADDR_HI                       0x3047
#define mmCP_RB_WPTR_POLL_ADDR_LO                       0x3046
#define mmCP_RB_WPTR_POLL_CNTL                          0x21C2
#define mmCP_RING0_PRIORITY                             0x304D
#define mmCP_RING1_PRIORITY                             0x304E
#define mmCP_RING2_PRIORITY                             0x304F
#define mmCP_RINGID                                     0xA0D9
#define mmCP_RING_PRIORITY_CNTS                         0x304C
#define mmCP_ROQ1_THRESHOLDS                            0x21D5
#define mmCP_ROQ2_AVAIL                                 0x21DC
#define mmCP_ROQ2_THRESHOLDS                            0x21D6
#define mmCP_ROQ_AVAIL                                  0x21DA
#define mmCP_ROQ_IB1_STAT                               0x21E1
#define mmCP_ROQ_IB2_STAT                               0x21E2
#define mmCP_ROQ_RB_STAT                                0x21E0
#define mmCP_ROQ_THRESHOLDS__CI__VI                     0x21BC
#define mmCP_SCRATCH_DATA__CI__VI                       0xC090
#define mmCP_SCRATCH_DATA__SI                           0x2190
#define mmCP_SCRATCH_INDEX__CI__VI                      0xC08F
#define mmCP_SCRATCH_INDEX__SI                          0x218F
#define mmCP_SC_PSINVOC_COUNT0_HI__CI__VI               0xC02D
#define mmCP_SC_PSINVOC_COUNT0_HI__SI                   0x212D
#define mmCP_SC_PSINVOC_COUNT0_LO__CI__VI               0xC02C
#define mmCP_SC_PSINVOC_COUNT0_LO__SI                   0x212C
#define mmCP_SC_PSINVOC_COUNT1_HI__CI__VI               0xC02F
#define mmCP_SC_PSINVOC_COUNT1_HI__SI                   0x212F
#define mmCP_SC_PSINVOC_COUNT1_LO__CI__VI               0xC02E
#define mmCP_SC_PSINVOC_COUNT1_LO__SI                   0x212E
#define mmCP_SEM_WAIT_TIMER__CI__VI                     0xC06F
#define mmCP_SEM_WAIT_TIMER__SI                         0x216F
#define mmCP_SIG_SEM_ADDR_HI__CI__VI                    0xC071
#define mmCP_SIG_SEM_ADDR_HI__SI                        0x2171
#define mmCP_SIG_SEM_ADDR_LO__CI__VI                    0xC070
#define mmCP_SIG_SEM_ADDR_LO__SI                        0x2170
#define mmCP_STALLED_STAT1                              0x219D
#define mmCP_STALLED_STAT2                              0x219E
#define mmCP_STALLED_STAT3                              0x219C
#define mmCP_STAT                                       0x21A0
#define mmCP_STQ_AVAIL                                  0x21DB
#define mmCP_STQ_STAT                                   0x21E3
#define mmCP_STQ_THRESHOLDS                             0x21D7
#define mmCP_STQ_WR_STAT__CI__VI                        0x21E4
#define mmCP_STREAM_OUT_ADDR_HI__CI__VI                 0xC007
#define mmCP_STREAM_OUT_ADDR_HI__SI                     0x2107
#define mmCP_STREAM_OUT_ADDR_LO__CI__VI                 0xC006
#define mmCP_STREAM_OUT_ADDR_LO__SI                     0x2106
#define mmCP_STRMOUT_CNTL__CI__VI                       0xC03F
#define mmCP_STRMOUT_CNTL__SI                           0x213F
#define mmCP_ST_BASE_HI__CI__VI                         0xC0D3
#define mmCP_ST_BASE_HI__SI                             0x21D3
#define mmCP_ST_BASE_LO__CI__VI                         0xC0D2
#define mmCP_ST_BASE_LO__SI                             0x21D2
#define mmCP_ST_BUFSZ__CI__VI                           0xC0D4
#define mmCP_ST_BUFSZ__SI                               0x21D4
#define mmCP_VGT_CSINVOC_COUNT_HI__CI__VI               0xC031
#define mmCP_VGT_CSINVOC_COUNT_HI__SI                   0x2131
#define mmCP_VGT_CSINVOC_COUNT_LO__CI__VI               0xC030
#define mmCP_VGT_CSINVOC_COUNT_LO__SI                   0x2130
#define mmCP_VGT_DSINVOC_COUNT_HI__CI__VI               0xC027
#define mmCP_VGT_DSINVOC_COUNT_HI__SI                   0x2127
#define mmCP_VGT_DSINVOC_COUNT_LO__CI__VI               0xC026
#define mmCP_VGT_DSINVOC_COUNT_LO__SI                   0x2126
#define mmCP_VGT_GSINVOC_COUNT_HI__CI__VI               0xC023
#define mmCP_VGT_GSINVOC_COUNT_HI__SI                   0x2123
#define mmCP_VGT_GSINVOC_COUNT_LO__CI__VI               0xC022
#define mmCP_VGT_GSINVOC_COUNT_LO__SI                   0x2122
#define mmCP_VGT_GSPRIM_COUNT_HI__CI__VI                0xC01F
#define mmCP_VGT_GSPRIM_COUNT_HI__SI                    0x211F
#define mmCP_VGT_GSPRIM_COUNT_LO__CI__VI                0xC01E
#define mmCP_VGT_GSPRIM_COUNT_LO__SI                    0x211E
#define mmCP_VGT_HSINVOC_COUNT_HI__CI__VI               0xC025
#define mmCP_VGT_HSINVOC_COUNT_HI__SI                   0x2125
#define mmCP_VGT_HSINVOC_COUNT_LO__CI__VI               0xC024
#define mmCP_VGT_HSINVOC_COUNT_LO__SI                   0x2124
#define mmCP_VGT_IAPRIM_COUNT_HI__CI__VI                0xC01D
#define mmCP_VGT_IAPRIM_COUNT_HI__SI                    0x211D
#define mmCP_VGT_IAPRIM_COUNT_LO__CI__VI                0xC01C
#define mmCP_VGT_IAPRIM_COUNT_LO__SI                    0x211C
#define mmCP_VGT_IAVERT_COUNT_HI__CI__VI                0xC01B
#define mmCP_VGT_IAVERT_COUNT_HI__SI                    0x211B
#define mmCP_VGT_IAVERT_COUNT_LO__CI__VI                0xC01A
#define mmCP_VGT_IAVERT_COUNT_LO__SI                    0x211A
#define mmCP_VGT_VSINVOC_COUNT_HI__CI__VI               0xC021
#define mmCP_VGT_VSINVOC_COUNT_HI__SI                   0x2121
#define mmCP_VGT_VSINVOC_COUNT_LO__CI__VI               0xC020
#define mmCP_VGT_VSINVOC_COUNT_LO__SI                   0x2120
#define mmCP_VMID                                       0xA0DA
#define mmCP_VMID_PREEMPT__CI__VI                       0x30B6
#define mmCP_VMID_RESET__CI__VI                         0x30B3
#define mmCP_WAIT_REG_MEM_TIMEOUT__CI__VI               0xC074
#define mmCP_WAIT_REG_MEM_TIMEOUT__SI                   0x2174
#define mmCP_WAIT_SEM_ADDR_HI__CI__VI                   0xC076
#define mmCP_WAIT_SEM_ADDR_HI__SI                       0x2176
#define mmCP_WAIT_SEM_ADDR_LO__CI__VI                   0xC075
#define mmCP_WAIT_SEM_ADDR_LO__SI                       0x2175
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__SI__VI       0x1BC3
#define mmCRTC0_CRTC_BLACK_COLOR__SI                    0x1BA2
#define mmCRTC0_CRTC_BLANK_CONTROL                      0x1B9D
#define mmCRTC0_CRTC_BLANK_DATA_COLOR__SI               0x1BA1
#define mmCRTC0_CRTC_CONTROL__SI__VI                    0x1B9C
#define mmCRTC0_CRTC_COUNT_CONTROL__SI__VI              0x1BA9
#define mmCRTC0_CRTC_COUNT_RESET__SI__VI                0x1BAA
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL__SI__VI      0x1BB6
#define mmCRTC0_CRTC_DTMTEST_CNTL__SI__VI               0x1B92
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION__SI__VI    0x1B93
#define mmCRTC0_CRTC_FLOW_CONTROL__SI__VI               0x1B99
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL__SI__VI       0x1B98
#define mmCRTC0_CRTC_H_BLANK_START_END__SI__VI          0x1B81
#define mmCRTC0_CRTC_H_SYNC_A_CNTL__SI__VI              0x1B83
#define mmCRTC0_CRTC_H_SYNC_A__SI__VI                   0x1B82
#define mmCRTC0_CRTC_H_SYNC_B_CNTL__SI__VI              0x1B85
#define mmCRTC0_CRTC_H_SYNC_B__SI__VI                   0x1B84
#define mmCRTC0_CRTC_H_TOTAL__SI__VI                    0x1B80
#define mmCRTC0_CRTC_INTERLACE_CONTROL__SI__VI          0x1B9E
#define mmCRTC0_CRTC_INTERLACE_STATUS__SI__VI           0x1B9F
#define mmCRTC0_CRTC_INTERRUPT_CONTROL__SI__VI          0x1BB4
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI 0x1BAB
#define mmCRTC0_CRTC_MASTER_EN__SI__VI                  0x1BC2
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI 0x1BC0
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT__SI__VI     0x1BBF
#define mmCRTC0_CRTC_MVP_STATUS__SI__VI                 0x1BC1
#define mmCRTC0_CRTC_NOM_VERT_POSITION__SI__VI          0x1BA5
#define mmCRTC0_CRTC_OVERSCAN_COLOR__SI                 0x1BA0
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK__SI            0x1B9A
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL__SI__VI           0x1BB0
#define mmCRTC0_CRTC_SNAPSHOT_FRAME__SI__VI             0x1BB2
#define mmCRTC0_CRTC_SNAPSHOT_POSITION__SI__VI          0x1BB1
#define mmCRTC0_CRTC_SNAPSHOT_STATUS__SI__VI            0x1BAF
#define mmCRTC0_CRTC_START_LINE_CONTROL__SI__VI         0x1BB3
#define mmCRTC0_CRTC_STATUS                             0x1BA3
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT__SI__VI         0x1BA6
#define mmCRTC0_CRTC_STATUS_HV_COUNT__SI__VI            0x1BA8
#define mmCRTC0_CRTC_STATUS_POSITION                    0x1BA4
#define mmCRTC0_CRTC_STATUS_VF_COUNT__SI__VI            0x1BA7
#define mmCRTC0_CRTC_STEREO_CONTROL__SI__VI             0x1BAE
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE__SI          0x1B9B
#define mmCRTC0_CRTC_STEREO_STATUS__SI__VI              0x1BAD
#define mmCRTC0_CRTC_TEST_DEBUG_DATA__SI__VI            0x1BC7
#define mmCRTC0_CRTC_TEST_DEBUG_INDEX__SI__VI           0x1BC6
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR__SI__VI         0x1BBC
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL__SI__VI       0x1BBA
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS__SI__VI    0x1BBB
#define mmCRTC0_CRTC_TRIGA_CNTL__SI__VI                 0x1B94
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG__SI__VI          0x1B95
#define mmCRTC0_CRTC_TRIGB_CNTL__SI__VI                 0x1B96
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG__SI__VI          0x1B97
#define mmCRTC0_CRTC_UPDATE_LOCK__SI__VI                0x1BB5
#define mmCRTC0_CRTC_VBI_END__SI__VI                    0x1B86
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL__SI__VI          0x1BAC
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI 0x1BB7
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS__SI__VI       0x1B8C
#define mmCRTC0_CRTC_V_BLANK_START_END__SI__VI          0x1B8D
#define mmCRTC0_CRTC_V_SYNC_A_CNTL__SI__VI              0x1B8F
#define mmCRTC0_CRTC_V_SYNC_A__SI__VI                   0x1B8E
#define mmCRTC0_CRTC_V_SYNC_B_CNTL__SI__VI              0x1B91
#define mmCRTC0_CRTC_V_SYNC_B__SI__VI                   0x1B90
#define mmCRTC0_CRTC_V_TOTAL_CONTROL__SI__VI            0x1B8A
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS__SI__VI         0x1B8B
#define mmCRTC0_CRTC_V_TOTAL_MAX__SI__VI                0x1B89
#define mmCRTC0_CRTC_V_TOTAL_MIN__SI__VI                0x1B88
#define mmCRTC0_CRTC_V_TOTAL__SI__VI                    0x1B87
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS__SI__VI        0x1BC4
#define mmCRTC0_MASTER_UPDATE_LOCK__SI__VI              0x1BBD
#define mmCRTC0_MASTER_UPDATE_MODE                      0x1BBE
#define mmCRTC0_PIXEL_RATE_CNTL__SI                     0x0120
#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__SI           0x1EC3
#define mmCRTC1_CRTC_BLACK_COLOR__SI                    0x1EA2
#define mmCRTC1_CRTC_BLANK_DATA_COLOR__SI               0x1EA1
#define mmCRTC1_CRTC_CONTROL__SI                        0x1E9C
#define mmCRTC1_CRTC_COUNT_CONTROL__SI                  0x1EA9
#define mmCRTC1_CRTC_COUNT_RESET__SI                    0x1EAA
#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL__SI          0x1EB6
#define mmCRTC1_CRTC_DTMTEST_CNTL__SI                   0x1E92
#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION__SI        0x1E93
#define mmCRTC1_CRTC_FLOW_CONTROL__SI                   0x1E99
#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL__SI           0x1E98
#define mmCRTC1_CRTC_H_BLANK_START_END__SI              0x1E81
#define mmCRTC1_CRTC_H_SYNC_A_CNTL__SI                  0x1E83
#define mmCRTC1_CRTC_H_SYNC_A__SI                       0x1E82
#define mmCRTC1_CRTC_H_SYNC_B_CNTL__SI                  0x1E85
#define mmCRTC1_CRTC_H_SYNC_B__SI                       0x1E84
#define mmCRTC1_CRTC_H_TOTAL__SI                        0x1E80
#define mmCRTC1_CRTC_INTERLACE_CONTROL__SI              0x1E9E
#define mmCRTC1_CRTC_INTERLACE_STATUS__SI               0x1E9F
#define mmCRTC1_CRTC_INTERRUPT_CONTROL__SI              0x1EB4
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI   0x1EAB
#define mmCRTC1_CRTC_MASTER_EN__SI                      0x1EC2
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI   0x1EC0
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT__SI         0x1EBF
#define mmCRTC1_CRTC_MVP_STATUS__SI                     0x1EC1
#define mmCRTC1_CRTC_NOM_VERT_POSITION__SI              0x1EA5
#define mmCRTC1_CRTC_OVERSCAN_COLOR__SI                 0x1EA0
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK__SI            0x1E9A
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL__SI               0x1EB0
#define mmCRTC1_CRTC_SNAPSHOT_FRAME__SI                 0x1EB2
#define mmCRTC1_CRTC_SNAPSHOT_POSITION__SI              0x1EB1
#define mmCRTC1_CRTC_SNAPSHOT_STATUS__SI                0x1EAF
#define mmCRTC1_CRTC_START_LINE_CONTROL__SI             0x1EB3
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT__SI             0x1EA6
#define mmCRTC1_CRTC_STATUS_HV_COUNT__SI                0x1EA8
#define mmCRTC1_CRTC_STATUS_VF_COUNT__SI                0x1EA7
#define mmCRTC1_CRTC_STEREO_CONTROL__SI                 0x1EAE
#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE__SI          0x1E9B
#define mmCRTC1_CRTC_STEREO_STATUS__SI                  0x1EAD
#define mmCRTC1_CRTC_TEST_DEBUG_DATA__SI                0x1EC7
#define mmCRTC1_CRTC_TEST_DEBUG_INDEX__SI               0x1EC6
#define mmCRTC1_CRTC_TEST_PATTERN_COLOR__SI             0x1EBC
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL__SI           0x1EBA
#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS__SI        0x1EBB
#define mmCRTC1_CRTC_TRIGA_CNTL__SI                     0x1E94
#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG__SI              0x1E95
#define mmCRTC1_CRTC_TRIGB_CNTL__SI                     0x1E96
#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG__SI              0x1E97
#define mmCRTC1_CRTC_UPDATE_LOCK__SI                    0x1EB5
#define mmCRTC1_CRTC_VBI_END__SI                        0x1E86
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL__SI              0x1EAC
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI     0x1EB7
#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS__SI           0x1E8C
#define mmCRTC1_CRTC_V_BLANK_START_END__SI              0x1E8D
#define mmCRTC1_CRTC_V_SYNC_A_CNTL__SI                  0x1E8F
#define mmCRTC1_CRTC_V_SYNC_A__SI                       0x1E8E
#define mmCRTC1_CRTC_V_SYNC_B_CNTL__SI                  0x1E91
#define mmCRTC1_CRTC_V_SYNC_B__SI                       0x1E90
#define mmCRTC1_CRTC_V_TOTAL_CONTROL__SI                0x1E8A
#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS__SI             0x1E8B
#define mmCRTC1_CRTC_V_TOTAL_MAX__SI                    0x1E89
#define mmCRTC1_CRTC_V_TOTAL_MIN__SI                    0x1E88
#define mmCRTC1_CRTC_V_TOTAL__SI                        0x1E87
#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS__SI            0x1EC4
#define mmCRTC1_MASTER_UPDATE_LOCK__SI                  0x1EBD
#define mmCRTC1_PIXEL_RATE_CNTL__SI                     0x0121
#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__SI           0x41C3
#define mmCRTC2_CRTC_BLACK_COLOR__SI                    0x41A2
#define mmCRTC2_CRTC_BLANK_DATA_COLOR__SI               0x41A1
#define mmCRTC2_CRTC_CONTROL__SI                        0x419C
#define mmCRTC2_CRTC_COUNT_CONTROL__SI                  0x41A9
#define mmCRTC2_CRTC_COUNT_RESET__SI                    0x41AA
#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL__SI          0x41B6
#define mmCRTC2_CRTC_DTMTEST_CNTL__SI                   0x4192
#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION__SI        0x4193
#define mmCRTC2_CRTC_FLOW_CONTROL__SI                   0x4199
#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL__SI           0x4198
#define mmCRTC2_CRTC_H_BLANK_START_END__SI              0x4181
#define mmCRTC2_CRTC_H_SYNC_A_CNTL__SI                  0x4183
#define mmCRTC2_CRTC_H_SYNC_A__SI                       0x4182
#define mmCRTC2_CRTC_H_SYNC_B_CNTL__SI                  0x4185
#define mmCRTC2_CRTC_H_SYNC_B__SI                       0x4184
#define mmCRTC2_CRTC_H_TOTAL__SI                        0x4180
#define mmCRTC2_CRTC_INTERLACE_CONTROL__SI              0x419E
#define mmCRTC2_CRTC_INTERLACE_STATUS__SI               0x419F
#define mmCRTC2_CRTC_INTERRUPT_CONTROL__SI              0x41B4
#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI   0x41AB
#define mmCRTC2_CRTC_MASTER_EN__SI                      0x41C2
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI   0x41C0
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT__SI         0x41BF
#define mmCRTC2_CRTC_MVP_STATUS__SI                     0x41C1
#define mmCRTC2_CRTC_NOM_VERT_POSITION__SI              0x41A5
#define mmCRTC2_CRTC_OVERSCAN_COLOR__SI                 0x41A0
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK__SI            0x419A
#define mmCRTC2_CRTC_SNAPSHOT_CONTROL__SI               0x41B0
#define mmCRTC2_CRTC_SNAPSHOT_FRAME__SI                 0x41B2
#define mmCRTC2_CRTC_SNAPSHOT_POSITION__SI              0x41B1
#define mmCRTC2_CRTC_SNAPSHOT_STATUS__SI                0x41AF
#define mmCRTC2_CRTC_START_LINE_CONTROL__SI             0x41B3
#define mmCRTC2_CRTC_STATUS_FRAME_COUNT__SI             0x41A6
#define mmCRTC2_CRTC_STATUS_HV_COUNT__SI                0x41A8
#define mmCRTC2_CRTC_STATUS_VF_COUNT__SI                0x41A7
#define mmCRTC2_CRTC_STEREO_CONTROL__SI                 0x41AE
#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE__SI          0x419B
#define mmCRTC2_CRTC_STEREO_STATUS__SI                  0x41AD
#define mmCRTC2_CRTC_TEST_DEBUG_DATA__SI                0x41C7
#define mmCRTC2_CRTC_TEST_DEBUG_INDEX__SI               0x41C6
#define mmCRTC2_CRTC_TEST_PATTERN_COLOR__SI             0x41BC
#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL__SI           0x41BA
#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS__SI        0x41BB
#define mmCRTC2_CRTC_TRIGA_CNTL__SI                     0x4194
#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG__SI              0x4195
#define mmCRTC2_CRTC_TRIGB_CNTL__SI                     0x4196
#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG__SI              0x4197
#define mmCRTC2_CRTC_UPDATE_LOCK__SI                    0x41B5
#define mmCRTC2_CRTC_VBI_END__SI                        0x4186
#define mmCRTC2_CRTC_VERT_SYNC_CONTROL__SI              0x41AC
#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI     0x41B7
#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS__SI           0x418C
#define mmCRTC2_CRTC_V_BLANK_START_END__SI              0x418D
#define mmCRTC2_CRTC_V_SYNC_A_CNTL__SI                  0x418F
#define mmCRTC2_CRTC_V_SYNC_A__SI                       0x418E
#define mmCRTC2_CRTC_V_SYNC_B_CNTL__SI                  0x4191
#define mmCRTC2_CRTC_V_SYNC_B__SI                       0x4190
#define mmCRTC2_CRTC_V_TOTAL_CONTROL__SI                0x418A
#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS__SI             0x418B
#define mmCRTC2_CRTC_V_TOTAL_MAX__SI                    0x4189
#define mmCRTC2_CRTC_V_TOTAL_MIN__SI                    0x4188
#define mmCRTC2_CRTC_V_TOTAL__SI                        0x4187
#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS__SI            0x41C4
#define mmCRTC2_MASTER_UPDATE_LOCK__SI                  0x41BD
#define mmCRTC2_PIXEL_RATE_CNTL__SI                     0x0122
#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__SI           0x44C3
#define mmCRTC3_CRTC_BLACK_COLOR__SI                    0x44A2
#define mmCRTC3_CRTC_BLANK_DATA_COLOR__SI               0x44A1
#define mmCRTC3_CRTC_CONTROL__SI                        0x449C
#define mmCRTC3_CRTC_COUNT_CONTROL__SI                  0x44A9
#define mmCRTC3_CRTC_COUNT_RESET__SI                    0x44AA
#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL__SI          0x44B6
#define mmCRTC3_CRTC_DTMTEST_CNTL__SI                   0x4492
#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION__SI        0x4493
#define mmCRTC3_CRTC_FLOW_CONTROL__SI                   0x4499
#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL__SI           0x4498
#define mmCRTC3_CRTC_H_BLANK_START_END__SI              0x4481
#define mmCRTC3_CRTC_H_SYNC_A_CNTL__SI                  0x4483
#define mmCRTC3_CRTC_H_SYNC_A__SI                       0x4482
#define mmCRTC3_CRTC_H_SYNC_B_CNTL__SI                  0x4485
#define mmCRTC3_CRTC_H_SYNC_B__SI                       0x4484
#define mmCRTC3_CRTC_H_TOTAL__SI                        0x4480
#define mmCRTC3_CRTC_INTERLACE_CONTROL__SI              0x449E
#define mmCRTC3_CRTC_INTERLACE_STATUS__SI               0x449F
#define mmCRTC3_CRTC_INTERRUPT_CONTROL__SI              0x44B4
#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI   0x44AB
#define mmCRTC3_CRTC_MASTER_EN__SI                      0x44C2
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI   0x44C0
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT__SI         0x44BF
#define mmCRTC3_CRTC_MVP_STATUS__SI                     0x44C1
#define mmCRTC3_CRTC_NOM_VERT_POSITION__SI              0x44A5
#define mmCRTC3_CRTC_OVERSCAN_COLOR__SI                 0x44A0
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK__SI            0x449A
#define mmCRTC3_CRTC_SNAPSHOT_CONTROL__SI               0x44B0
#define mmCRTC3_CRTC_SNAPSHOT_FRAME__SI                 0x44B2
#define mmCRTC3_CRTC_SNAPSHOT_POSITION__SI              0x44B1
#define mmCRTC3_CRTC_SNAPSHOT_STATUS__SI                0x44AF
#define mmCRTC3_CRTC_START_LINE_CONTROL__SI             0x44B3
#define mmCRTC3_CRTC_STATUS_FRAME_COUNT__SI             0x44A6
#define mmCRTC3_CRTC_STATUS_HV_COUNT__SI                0x44A8
#define mmCRTC3_CRTC_STATUS_VF_COUNT__SI                0x44A7
#define mmCRTC3_CRTC_STEREO_CONTROL__SI                 0x44AE
#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE__SI          0x449B
#define mmCRTC3_CRTC_STEREO_STATUS__SI                  0x44AD
#define mmCRTC3_CRTC_TEST_DEBUG_DATA__SI                0x44C7
#define mmCRTC3_CRTC_TEST_DEBUG_INDEX__SI               0x44C6
#define mmCRTC3_CRTC_TEST_PATTERN_COLOR__SI             0x44BC
#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL__SI           0x44BA
#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS__SI        0x44BB
#define mmCRTC3_CRTC_TRIGA_CNTL__SI                     0x4494
#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG__SI              0x4495
#define mmCRTC3_CRTC_TRIGB_CNTL__SI                     0x4496
#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG__SI              0x4497
#define mmCRTC3_CRTC_UPDATE_LOCK__SI                    0x44B5
#define mmCRTC3_CRTC_VBI_END__SI                        0x4486
#define mmCRTC3_CRTC_VERT_SYNC_CONTROL__SI              0x44AC
#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI     0x44B7
#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS__SI           0x448C
#define mmCRTC3_CRTC_V_BLANK_START_END__SI              0x448D
#define mmCRTC3_CRTC_V_SYNC_A_CNTL__SI                  0x448F
#define mmCRTC3_CRTC_V_SYNC_A__SI                       0x448E
#define mmCRTC3_CRTC_V_SYNC_B_CNTL__SI                  0x4491
#define mmCRTC3_CRTC_V_SYNC_B__SI                       0x4490
#define mmCRTC3_CRTC_V_TOTAL_CONTROL__SI                0x448A
#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS__SI             0x448B
#define mmCRTC3_CRTC_V_TOTAL_MAX__SI                    0x4489
#define mmCRTC3_CRTC_V_TOTAL_MIN__SI                    0x4488
#define mmCRTC3_CRTC_V_TOTAL__SI                        0x4487
#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS__SI            0x44C4
#define mmCRTC3_MASTER_UPDATE_LOCK__SI                  0x44BD
#define mmCRTC3_PIXEL_RATE_CNTL__SI                     0x0123
#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__SI           0x47C3
#define mmCRTC4_CRTC_BLACK_COLOR__SI                    0x47A2
#define mmCRTC4_CRTC_BLANK_DATA_COLOR__SI               0x47A1
#define mmCRTC4_CRTC_CONTROL__SI                        0x479C
#define mmCRTC4_CRTC_COUNT_CONTROL__SI                  0x47A9
#define mmCRTC4_CRTC_COUNT_RESET__SI                    0x47AA
#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL__SI          0x47B6
#define mmCRTC4_CRTC_DTMTEST_CNTL__SI                   0x4792
#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION__SI        0x4793
#define mmCRTC4_CRTC_FLOW_CONTROL__SI                   0x4799
#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL__SI           0x4798
#define mmCRTC4_CRTC_H_BLANK_START_END__SI              0x4781
#define mmCRTC4_CRTC_H_SYNC_A_CNTL__SI                  0x4783
#define mmCRTC4_CRTC_H_SYNC_A__SI                       0x4782
#define mmCRTC4_CRTC_H_SYNC_B_CNTL__SI                  0x4785
#define mmCRTC4_CRTC_H_SYNC_B__SI                       0x4784
#define mmCRTC4_CRTC_H_TOTAL__SI                        0x4780
#define mmCRTC4_CRTC_INTERLACE_CONTROL__SI              0x479E
#define mmCRTC4_CRTC_INTERLACE_STATUS__SI               0x479F
#define mmCRTC4_CRTC_INTERRUPT_CONTROL__SI              0x47B4
#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI   0x47AB
#define mmCRTC4_CRTC_MASTER_EN__SI                      0x47C2
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI   0x47C0
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT__SI         0x47BF
#define mmCRTC4_CRTC_MVP_STATUS__SI                     0x47C1
#define mmCRTC4_CRTC_NOM_VERT_POSITION__SI              0x47A5
#define mmCRTC4_CRTC_OVERSCAN_COLOR__SI                 0x47A0
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK__SI            0x479A
#define mmCRTC4_CRTC_SNAPSHOT_CONTROL__SI               0x47B0
#define mmCRTC4_CRTC_SNAPSHOT_FRAME__SI                 0x47B2
#define mmCRTC4_CRTC_SNAPSHOT_POSITION__SI              0x47B1
#define mmCRTC4_CRTC_SNAPSHOT_STATUS__SI                0x47AF
#define mmCRTC4_CRTC_START_LINE_CONTROL__SI             0x47B3
#define mmCRTC4_CRTC_STATUS_FRAME_COUNT__SI             0x47A6
#define mmCRTC4_CRTC_STATUS_HV_COUNT__SI                0x47A8
#define mmCRTC4_CRTC_STATUS_VF_COUNT__SI                0x47A7
#define mmCRTC4_CRTC_STEREO_CONTROL__SI                 0x47AE
#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE__SI          0x479B
#define mmCRTC4_CRTC_STEREO_STATUS__SI                  0x47AD
#define mmCRTC4_CRTC_TEST_DEBUG_DATA__SI                0x47C7
#define mmCRTC4_CRTC_TEST_DEBUG_INDEX__SI               0x47C6
#define mmCRTC4_CRTC_TEST_PATTERN_COLOR__SI             0x47BC
#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL__SI           0x47BA
#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS__SI        0x47BB
#define mmCRTC4_CRTC_TRIGA_CNTL__SI                     0x4794
#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG__SI              0x4795
#define mmCRTC4_CRTC_TRIGB_CNTL__SI                     0x4796
#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG__SI              0x4797
#define mmCRTC4_CRTC_UPDATE_LOCK__SI                    0x47B5
#define mmCRTC4_CRTC_VBI_END__SI                        0x4786
#define mmCRTC4_CRTC_VERT_SYNC_CONTROL__SI              0x47AC
#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI     0x47B7
#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS__SI           0x478C
#define mmCRTC4_CRTC_V_BLANK_START_END__SI              0x478D
#define mmCRTC4_CRTC_V_SYNC_A_CNTL__SI                  0x478F
#define mmCRTC4_CRTC_V_SYNC_A__SI                       0x478E
#define mmCRTC4_CRTC_V_SYNC_B_CNTL__SI                  0x4791
#define mmCRTC4_CRTC_V_SYNC_B__SI                       0x4790
#define mmCRTC4_CRTC_V_TOTAL_CONTROL__SI                0x478A
#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS__SI             0x478B
#define mmCRTC4_CRTC_V_TOTAL_MAX__SI                    0x4789
#define mmCRTC4_CRTC_V_TOTAL_MIN__SI                    0x4788
#define mmCRTC4_CRTC_V_TOTAL__SI                        0x4787
#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS__SI            0x47C4
#define mmCRTC4_MASTER_UPDATE_LOCK__SI                  0x47BD
#define mmCRTC4_PIXEL_RATE_CNTL__SI                     0x0124
#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__SI           0x4AC3
#define mmCRTC5_CRTC_BLACK_COLOR__SI                    0x4AA2
#define mmCRTC5_CRTC_BLANK_DATA_COLOR__SI               0x4AA1
#define mmCRTC5_CRTC_CONTROL__SI                        0x4A9C
#define mmCRTC5_CRTC_COUNT_CONTROL__SI                  0x4AA9
#define mmCRTC5_CRTC_COUNT_RESET__SI                    0x4AAA
#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL__SI          0x4AB6
#define mmCRTC5_CRTC_DTMTEST_CNTL__SI                   0x4A92
#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION__SI        0x4A93
#define mmCRTC5_CRTC_FLOW_CONTROL__SI                   0x4A99
#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL__SI           0x4A98
#define mmCRTC5_CRTC_H_BLANK_START_END__SI              0x4A81
#define mmCRTC5_CRTC_H_SYNC_A_CNTL__SI                  0x4A83
#define mmCRTC5_CRTC_H_SYNC_A__SI                       0x4A82
#define mmCRTC5_CRTC_H_SYNC_B_CNTL__SI                  0x4A85
#define mmCRTC5_CRTC_H_SYNC_B__SI                       0x4A84
#define mmCRTC5_CRTC_H_TOTAL__SI                        0x4A80
#define mmCRTC5_CRTC_INTERLACE_CONTROL__SI              0x4A9E
#define mmCRTC5_CRTC_INTERLACE_STATUS__SI               0x4A9F
#define mmCRTC5_CRTC_INTERRUPT_CONTROL__SI              0x4AB4
#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI   0x4AAB
#define mmCRTC5_CRTC_MASTER_EN__SI                      0x4AC2
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI   0x4AC0
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT__SI         0x4ABF
#define mmCRTC5_CRTC_MVP_STATUS__SI                     0x4AC1
#define mmCRTC5_CRTC_NOM_VERT_POSITION__SI              0x4AA5
#define mmCRTC5_CRTC_OVERSCAN_COLOR__SI                 0x4AA0
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK__SI            0x4A9A
#define mmCRTC5_CRTC_SNAPSHOT_CONTROL__SI               0x4AB0
#define mmCRTC5_CRTC_SNAPSHOT_FRAME__SI                 0x4AB2
#define mmCRTC5_CRTC_SNAPSHOT_POSITION__SI              0x4AB1
#define mmCRTC5_CRTC_SNAPSHOT_STATUS__SI                0x4AAF
#define mmCRTC5_CRTC_START_LINE_CONTROL__SI             0x4AB3
#define mmCRTC5_CRTC_STATUS_FRAME_COUNT__SI             0x4AA6
#define mmCRTC5_CRTC_STATUS_HV_COUNT__SI                0x4AA8
#define mmCRTC5_CRTC_STATUS_VF_COUNT__SI                0x4AA7
#define mmCRTC5_CRTC_STEREO_CONTROL__SI                 0x4AAE
#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE__SI          0x4A9B
#define mmCRTC5_CRTC_STEREO_STATUS__SI                  0x4AAD
#define mmCRTC5_CRTC_TEST_DEBUG_DATA__SI                0x4AC7
#define mmCRTC5_CRTC_TEST_DEBUG_INDEX__SI               0x4AC6
#define mmCRTC5_CRTC_TEST_PATTERN_COLOR__SI             0x4ABC
#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL__SI           0x4ABA
#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS__SI        0x4ABB
#define mmCRTC5_CRTC_TRIGA_CNTL__SI                     0x4A94
#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG__SI              0x4A95
#define mmCRTC5_CRTC_TRIGB_CNTL__SI                     0x4A96
#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG__SI              0x4A97
#define mmCRTC5_CRTC_UPDATE_LOCK__SI                    0x4AB5
#define mmCRTC5_CRTC_VBI_END__SI                        0x4A86
#define mmCRTC5_CRTC_VERT_SYNC_CONTROL__SI              0x4AAC
#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI     0x4AB7
#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS__SI           0x4A8C
#define mmCRTC5_CRTC_V_BLANK_START_END__SI              0x4A8D
#define mmCRTC5_CRTC_V_SYNC_A_CNTL__SI                  0x4A8F
#define mmCRTC5_CRTC_V_SYNC_A__SI                       0x4A8E
#define mmCRTC5_CRTC_V_SYNC_B_CNTL__SI                  0x4A91
#define mmCRTC5_CRTC_V_SYNC_B__SI                       0x4A90
#define mmCRTC5_CRTC_V_TOTAL_CONTROL__SI                0x4A8A
#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS__SI             0x4A8B
#define mmCRTC5_CRTC_V_TOTAL_MAX__SI                    0x4A89
#define mmCRTC5_CRTC_V_TOTAL_MIN__SI                    0x4A88
#define mmCRTC5_CRTC_V_TOTAL__SI                        0x4A87
#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS__SI            0x4AC4
#define mmCRTC5_MASTER_UPDATE_LOCK__SI                  0x4ABD
#define mmCRTC5_PIXEL_RATE_CNTL__SI                     0x0125
#define mmCRTC8_DATA__SI__VI                            0x00ED
#define mmCRTC8_IDX__SI__VI                             0x00ED
#define mmCRTC_ALLOW_STOP_OFF_V_CNT__SI__VI             0x1BC3
#define mmCRTC_BLACK_COLOR__SI                          0x1BA2
#define mmCRTC_BLANK_CONTROL                            0x1B9D
#define mmCRTC_BLANK_DATA_COLOR__SI                     0x1BA1
#define mmCRTC_CONTROL__SI__VI                          0x1B9C
#define mmCRTC_COUNT_CONTROL__SI__VI                    0x1BA9
#define mmCRTC_COUNT_RESET__SI__VI                      0x1BAA
#define mmCRTC_DOUBLE_BUFFER_CONTROL__SI__VI            0x1BB6
#define mmCRTC_DTMTEST_CNTL__SI__VI                     0x1B92
#define mmCRTC_DTMTEST_STATUS_POSITION__SI__VI          0x1B93
#define mmCRTC_FLOW_CONTROL__SI__VI                     0x1B99
#define mmCRTC_FORCE_COUNT_NOW_CNTL__SI__VI             0x1B98
#define mmCRTC_H_BLANK_START_END__SI__VI                0x1B81
#define mmCRTC_H_SYNC_A_CNTL__SI__VI                    0x1B83
#define mmCRTC_H_SYNC_A__SI__VI                         0x1B82
#define mmCRTC_H_SYNC_B_CNTL__SI__VI                    0x1B85
#define mmCRTC_H_SYNC_B__SI__VI                         0x1B84
#define mmCRTC_H_TOTAL__SI__VI                          0x1B80
#define mmCRTC_INTERLACE_CONTROL__SI__VI                0x1B9E
#define mmCRTC_INTERLACE_STATUS__SI__VI                 0x1B9F
#define mmCRTC_INTERRUPT_CONTROL__SI__VI                0x1BB4
#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI     0x1BAB
#define mmCRTC_MASTER_EN__SI__VI                        0x1BC2
#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI     0x1BC0
#define mmCRTC_MVP_INBAND_CNTL_INSERT__SI__VI           0x1BBF
#define mmCRTC_MVP_STATUS__SI__VI                       0x1BC1
#define mmCRTC_NOM_VERT_POSITION__SI__VI                0x1BA5
#define mmCRTC_OVERSCAN_COLOR__SI                       0x1BA0
#define mmCRTC_PIXEL_DATA_READBACK__SI                  0x1B9A
#define mmCRTC_SNAPSHOT_CONTROL__SI__VI                 0x1BB0
#define mmCRTC_SNAPSHOT_FRAME__SI__VI                   0x1BB2
#define mmCRTC_SNAPSHOT_POSITION__SI__VI                0x1BB1
#define mmCRTC_SNAPSHOT_STATUS__SI__VI                  0x1BAF
#define mmCRTC_START_LINE_CONTROL__SI__VI               0x1BB3
#define mmCRTC_STATUS                                   0x1BA3
#define mmCRTC_STATUS_FRAME_COUNT__SI__VI               0x1BA6
#define mmCRTC_STATUS_HV_COUNT__SI__VI                  0x1BA8
#define mmCRTC_STATUS_POSITION__SI__VI                  0x1BA4
#define mmCRTC_STATUS_VF_COUNT__SI__VI                  0x1BA7
#define mmCRTC_STEREO_CONTROL__SI__VI                   0x1BAE
#define mmCRTC_STEREO_FORCE_NEXT_EYE__SI                0x1B9B
#define mmCRTC_STEREO_STATUS__SI__VI                    0x1BAD
#define mmCRTC_TEST_DEBUG_DATA__SI__VI                  0x1BC7
#define mmCRTC_TEST_DEBUG_INDEX__SI__VI                 0x1BC6
#define mmCRTC_TEST_PATTERN_COLOR__SI__VI               0x1BBC
#define mmCRTC_TEST_PATTERN_CONTROL__SI__VI             0x1BBA
#define mmCRTC_TEST_PATTERN_PARAMETERS__SI__VI          0x1BBB
#define mmCRTC_TRIGA_CNTL__SI__VI                       0x1B94
#define mmCRTC_TRIGA_MANUAL_TRIG__SI__VI                0x1B95
#define mmCRTC_TRIGB_CNTL__SI__VI                       0x1B96
#define mmCRTC_TRIGB_MANUAL_TRIG__SI__VI                0x1B97
#define mmCRTC_UPDATE_LOCK__SI__VI                      0x1BB5
#define mmCRTC_VBI_END__SI__VI                          0x1B86
#define mmCRTC_VERT_SYNC_CONTROL__SI__VI                0x1BAC
#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI       0x1BB7
#define mmCRTC_VSYNC_NOM_INT_STATUS__SI__VI             0x1B8C
#define mmCRTC_V_BLANK_START_END__SI__VI                0x1B8D
#define mmCRTC_V_SYNC_A_CNTL__SI__VI                    0x1B8F
#define mmCRTC_V_SYNC_A__SI__VI                         0x1B8E
#define mmCRTC_V_SYNC_B_CNTL__SI__VI                    0x1B91
#define mmCRTC_V_SYNC_B__SI__VI                         0x1B90
#define mmCRTC_V_TOTAL_CONTROL__SI__VI                  0x1B8A
#define mmCRTC_V_TOTAL_INT_STATUS__SI__VI               0x1B8B
#define mmCRTC_V_TOTAL_MAX__SI__VI                      0x1B89
#define mmCRTC_V_TOTAL_MIN__SI__VI                      0x1B88
#define mmCRTC_V_TOTAL__SI__VI                          0x1B87
#define mmCRTC_V_UPDATE_INT_STATUS__SI__VI              0x1BC4
#define mmCS_COPY_STATE                                 0xA1F3
#define mmCUR_COLOR1__SI__VI                            0x1A6C
#define mmCUR_COLOR2__SI__VI                            0x1A6D
#define mmCUR_CONTROL__SI__VI                           0x1A66
#define mmCUR_HOT_SPOT__SI__VI                          0x1A6B
#define mmCUR_POSITION__SI__VI                          0x1A6A
#define mmCUR_SIZE__SI__VI                              0x1A68
#define mmCUR_SURFACE_ADDRESS_HIGH__SI__VI              0x1A69
#define mmCUR_SURFACE_ADDRESS__SI__VI                   0x1A67
#define mmCUR_UPDATE__SI__VI                            0x1A6E
#define mmD1VGA_CONTROL__SI__VI                         0x00CC
#define mmD2VGA_CONTROL__SI__VI                         0x00CE
#define mmD3VGA_CONTROL__SI__VI                         0x00F8
#define mmD4VGA_CONTROL__SI__VI                         0x00F9
#define mmD5VGA_CONTROL__SI__VI                         0x00FA
#define mmD6VGA_CONTROL__SI__VI                         0x00FB
#define mmDAC_AUTODETECT_CONTROL2__SI                   0x19AF
#define mmDAC_AUTODETECT_CONTROL3__SI                   0x19B0
#define mmDAC_AUTODETECT_CONTROL__SI                    0x19AE
#define mmDAC_AUTODETECT_INT_CONTROL__SI                0x19B2
#define mmDAC_AUTODETECT_STATUS__SI                     0x19B1
#define mmDAC_COMPARATOR_ENABLE__SI                     0x19B7
#define mmDAC_COMPARATOR_OUTPUT__SI                     0x19B8
#define mmDAC_CONTROL__SI                               0x19B6
#define mmDAC_CRC_CONTROL__SI                           0x19A7
#define mmDAC_CRC_EN__SI                                0x19A6
#define mmDAC_CRC_SIG_CONTROL_MASK__SI                  0x19A9
#define mmDAC_CRC_SIG_CONTROL__SI                       0x19AB
#define mmDAC_CRC_SIG_RGB_MASK__SI                      0x19A8
#define mmDAC_CRC_SIG_RGB__SI                           0x19AA
#define mmDAC_DATA__SI__VI                              0x00F2
#define mmDAC_DFT_CONFIG__SI                            0x19BA
#define mmDAC_ENABLE__SI                                0x19A4
#define mmDAC_FORCE_DATA__SI                            0x19B4
#define mmDAC_FORCE_OUTPUT_CNTL__SI                     0x19B3
#define mmDAC_MACRO_CNTL__SI                            0x1939
#define mmDAC_MASK__SI__VI                              0x00F1
#define mmDAC_POWERDOWN__SI                             0x19B5
#define mmDAC_PWR_CNTL__SI                              0x19B9
#define mmDAC_R_INDEX__SI__VI                           0x00F1
#define mmDAC_SOURCE_SELECT__SI                         0x19A5
#define mmDAC_STEREOSYNC_SELECT__SI                     0x19AD
#define mmDAC_SYNC_TRISTATE_CONTROL__SI                 0x19AC
#define mmDAC_W_INDEX__SI__VI                           0x00F2
#define mmDATA_FORMAT__SI                               0x1AC0
#define mmDBG_BYPASS_SRBM_ACCESS__CI                    0x14EB
#define mmDB_ALPHA_TO_MASK                              0xA2DC
#define mmDB_CGTT_CLK_CTRL_0__CI__VI                    0xF0A4
#define mmDB_CGTT_CLK_CTRL_0__SI                        0x261A
#define mmDB_COUNT_CONTROL                              0xA001
#define mmDB_CREDIT_LIMIT                               0x2614
#define mmDB_DEBUG                                      0x260C
#define mmDB_DEBUG2                                     0x260D
#define mmDB_DEBUG3                                     0x260E
#define mmDB_DEBUG4                                     0x260F
#define mmDB_DEPTH_BOUNDS_MAX                           0xA009
#define mmDB_DEPTH_BOUNDS_MIN                           0xA008
#define mmDB_DEPTH_CLEAR                                0xA00B
#define mmDB_DEPTH_CONTROL                              0xA200
#define mmDB_DEPTH_INFO                                 0xA00F
#define mmDB_DEPTH_SIZE                                 0xA016
#define mmDB_DEPTH_SLICE                                0xA017
#define mmDB_DEPTH_VIEW                                 0xA002
#define mmDB_EQAA                                       0xA201
#define mmDB_FIFO_DEPTH1                                0x2618
#define mmDB_FIFO_DEPTH2                                0x2619
#define mmDB_FREE_CACHELINES                            0x2617
#define mmDB_HTILE_DATA_BASE                            0xA005
#define mmDB_HTILE_SURFACE                              0xA2AF
#define mmDB_OCCLUSION_COUNT0_HI__CI__VI                0xC3C1
#define mmDB_OCCLUSION_COUNT0_LOW__CI__VI               0xC3C0
#define mmDB_OCCLUSION_COUNT1_HI__CI__VI                0xC3C3
#define mmDB_OCCLUSION_COUNT1_LOW__CI__VI               0xC3C2
#define mmDB_OCCLUSION_COUNT2_HI__CI__VI                0xC3C5
#define mmDB_OCCLUSION_COUNT2_LOW__CI__VI               0xC3C4
#define mmDB_OCCLUSION_COUNT3_HI__CI__VI                0xC3C7
#define mmDB_OCCLUSION_COUNT3_LOW__CI__VI               0xC3C6
#define mmDB_PERFCOUNTER0_HI__CI__VI                    0xD441
#define mmDB_PERFCOUNTER0_HI__SI                        0x2602
#define mmDB_PERFCOUNTER0_LO__CI__VI                    0xD440
#define mmDB_PERFCOUNTER0_LO__SI                        0x2601
#define mmDB_PERFCOUNTER0_SELECT1__CI__VI               0xDC41
#define mmDB_PERFCOUNTER0_SELECT__CI__VI                0xDC40
#define mmDB_PERFCOUNTER0_SELECT__SI                    0x2600
#define mmDB_PERFCOUNTER1_HI__CI__VI                    0xD443
#define mmDB_PERFCOUNTER1_HI__SI                        0x2605
#define mmDB_PERFCOUNTER1_LO__CI__VI                    0xD442
#define mmDB_PERFCOUNTER1_LO__SI                        0x2604
#define mmDB_PERFCOUNTER1_SELECT1__CI__VI               0xDC43
#define mmDB_PERFCOUNTER1_SELECT__CI__VI                0xDC42
#define mmDB_PERFCOUNTER1_SELECT__SI                    0x2603
#define mmDB_PERFCOUNTER2_HI__CI__VI                    0xD445
#define mmDB_PERFCOUNTER2_HI__SI                        0x2608
#define mmDB_PERFCOUNTER2_LO__CI__VI                    0xD444
#define mmDB_PERFCOUNTER2_LO__SI                        0x2607
#define mmDB_PERFCOUNTER2_SELECT__CI__VI                0xDC44
#define mmDB_PERFCOUNTER2_SELECT__SI                    0x2606
#define mmDB_PERFCOUNTER3_HI__CI__VI                    0xD447
#define mmDB_PERFCOUNTER3_HI__SI                        0x260B
#define mmDB_PERFCOUNTER3_LO__CI__VI                    0xD446
#define mmDB_PERFCOUNTER3_LO__SI                        0x260A
#define mmDB_PERFCOUNTER3_SELECT__CI__VI                0xDC46
#define mmDB_PERFCOUNTER3_SELECT__SI                    0x2609
#define mmDB_PRELOAD_CONTROL                            0xA2B2
#define mmDB_READ_DEBUG_0                               0x2620
#define mmDB_READ_DEBUG_1                               0x2621
#define mmDB_READ_DEBUG_2                               0x2622
#define mmDB_READ_DEBUG_3                               0x2623
#define mmDB_READ_DEBUG_4                               0x2624
#define mmDB_READ_DEBUG_5                               0x2625
#define mmDB_READ_DEBUG_6                               0x2626
#define mmDB_READ_DEBUG_7                               0x2627
#define mmDB_READ_DEBUG_8                               0x2628
#define mmDB_READ_DEBUG_9                               0x2629
#define mmDB_READ_DEBUG_A                               0x262A
#define mmDB_READ_DEBUG_B                               0x262B
#define mmDB_READ_DEBUG_C                               0x262C
#define mmDB_READ_DEBUG_D                               0x262D
#define mmDB_READ_DEBUG_E                               0x262E
#define mmDB_READ_DEBUG_F                               0x262F
#define mmDB_RENDER_CONTROL                             0xA000
#define mmDB_RENDER_OVERRIDE                            0xA003
#define mmDB_RENDER_OVERRIDE2                           0xA004
#define mmDB_RING_CONTROL__CI__VI                       0x261B
#define mmDB_SHADER_CONTROL                             0xA203
#define mmDB_SRESULTS_COMPARE_STATE0                    0xA2B0
#define mmDB_SRESULTS_COMPARE_STATE1                    0xA2B1
#define mmDB_STENCILREFMASK                             0xA10C
#define mmDB_STENCILREFMASK_BF                          0xA10D
#define mmDB_STENCIL_CLEAR                              0xA00A
#define mmDB_STENCIL_CONTROL                            0xA10B
#define mmDB_STENCIL_INFO                               0xA011
#define mmDB_STENCIL_READ_BASE                          0xA013
#define mmDB_STENCIL_WRITE_BASE                         0xA015
#define mmDB_SUBTILE_CONTROL                            0x2616
#define mmDB_WATERMARKS                                 0x2615
#define mmDB_ZPASS_COUNT_HI__CI__VI                     0xC3FF
#define mmDB_ZPASS_COUNT_HI__SI                         0x261D
#define mmDB_ZPASS_COUNT_LOW__CI__VI                    0xC3FE
#define mmDB_ZPASS_COUNT_LOW__SI                        0x261C
#define mmDB_Z_INFO                                     0xA010
#define mmDB_Z_READ_BASE                                0xA012
#define mmDB_Z_WRITE_BASE                               0xA014
#define mmDCCG_AUDIO_DTO0_MODULE__SI                    0x0154
#define mmDCCG_AUDIO_DTO0_PHASE__SI                     0x0153
#define mmDCCG_GATE_DISABLE_CNTL__SI                    0x011F
#define mmDCCG_TEST_CLK_SEL__SI                         0x0147
#define mmDCCG_TEST_DEBUG_DATA__SI                      0x0159
#define mmDCCG_TEST_DEBUG_INDEX__SI                     0x0158
#define mmDCCG_VPCLK_CNTL__SI                           0x015E
#define mmDCDEBUG_BUS_CLK1_SEL__SI                      0x1860
#define mmDCDEBUG_BUS_CLK2_SEL__SI                      0x1861
#define mmDCDEBUG_BUS_CLK3_SEL__SI                      0x1862
#define mmDCDEBUG_BUS_CLK4_SEL__SI                      0x1863
#define mmDCDEBUG_OUT_CNTL__SI                          0x186B
#define mmDCDEBUG_OUT_PIN_OVERRIDE__SI                  0x186A
#define mmDCIO_DEBUG__SI                                0x196F
#define mmDCIO_IMPCAL_CNTL_AB__SI                       0x194C
#define mmDCIO_IMPCAL_CNTL_CD__SI                       0x194F
#define mmDCIO_IMPCAL_CNTL_EF__SI                       0x1952
#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION__SI  0x1984
#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT__SI       0x1986
#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION__SI  0x1990
#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT__SI       0x1992
#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION__SI  0x199C
#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT__SI       0x199E
#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION__SI  0x19C4
#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT__SI       0x19C6
#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION__SI  0x19D0
#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT__SI       0x19D2
#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION__SI  0x19DC
#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT__SI       0x19DE
#define mmDCI_TEST_DEBUG_DATA__SI                       0x0321
#define mmDCI_TEST_DEBUG_INDEX__SI                      0x0320
#define mmDCP0_CUR_COLOR1__SI__VI                       0x1A6C
#define mmDCP0_CUR_COLOR2__SI__VI                       0x1A6D
#define mmDCP0_CUR_CONTROL__SI__VI                      0x1A66
#define mmDCP0_CUR_HOT_SPOT__SI__VI                     0x1A6B
#define mmDCP0_CUR_POSITION__SI__VI                     0x1A6A
#define mmDCP0_CUR_SIZE__SI__VI                         0x1A68
#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH__SI__VI         0x1A69
#define mmDCP0_CUR_SURFACE_ADDRESS__SI__VI              0x1A67
#define mmDCP0_CUR_UPDATE__SI__VI                       0x1A6E
#define mmDCP0_DCP_CRC_CONTROL__SI__VI                  0x1A87
#define mmDCP0_DCP_CRC_CURRENT__SI__VI                  0x1A89
#define mmDCP0_DCP_CRC_LAST__SI__VI                     0x1A8B
#define mmDCP0_DCP_CRC_MASK__SI__VI                     0x1A88
#define mmDCP0_DCP_DEBUG__SI__VI                        0x1A8D
#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI    0x1A91
#define mmDCP0_DCP_TEST_DEBUG_DATA__SI__VI              0x1A96
#define mmDCP0_DCP_TEST_DEBUG_INDEX__SI__VI             0x1A95
#define mmDCP0_DC_LUT_30_COLOR__SI__VI                  0x1A7C
#define mmDCP0_DC_LUT_AUTOFILL__SI__VI                  0x1A7F
#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE__SI__VI         0x1A81
#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN__SI__VI        0x1A82
#define mmDCP0_DC_LUT_BLACK_OFFSET_RED__SI__VI          0x1A83
#define mmDCP0_DC_LUT_CONTROL__SI__VI                   0x1A80
#define mmDCP0_DC_LUT_PWL_DATA__SI__VI                  0x1A7B
#define mmDCP0_DC_LUT_RW_INDEX__SI__VI                  0x1A79
#define mmDCP0_DC_LUT_RW_MODE__SI__VI                   0x1A78
#define mmDCP0_DC_LUT_SEQ_COLOR__SI__VI                 0x1A7A
#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE__SI__VI         0x1A84
#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN__SI__VI        0x1A85
#define mmDCP0_DC_LUT_WHITE_OFFSET_RED__SI__VI          0x1A86
#define mmDCP0_DC_LUT_WRITE_EN_MASK__SI__VI             0x1A7E
#define mmDCP0_GRPH_COMPRESS_PITCH__SI__VI              0x1A1A
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI 0x1A1B
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS__SI__VI    0x1A19
#define mmDCP0_GRPH_CONTROL                             0x1A01
#define mmDCP0_GRPH_DFQ_CONTROL__SI__VI                 0x1A14
#define mmDCP0_GRPH_DFQ_STATUS__SI__VI                  0x1A15
#define mmDCP0_GRPH_ENABLE__SI__VI                      0x1A00
#define mmDCP0_GRPH_FLIP_CONTROL                        0x1A12
#define mmDCP0_GRPH_INTERRUPT_CONTROL__SI__VI           0x1A17
#define mmDCP0_GRPH_INTERRUPT_STATUS__SI__VI            0x1A16
#define mmDCP0_GRPH_LUT_10BIT_BYPASS__SI__VI            0x1A02
#define mmDCP0_GRPH_PITCH                               0x1A06
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS             0x1A04
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH        0x1A07
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI 0x1A08
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS__SI__VI   0x1A05
#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI  0x1A18
#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE__SI__VI       0x1A13
#define mmDCP0_GRPH_SURFACE_OFFSET_X__SI__VI            0x1A09
#define mmDCP0_GRPH_SURFACE_OFFSET_Y__SI__VI            0x1A0A
#define mmDCP0_GRPH_SWAP_CNTL__SI__VI                   0x1A03
#define mmDCP0_GRPH_UPDATE                              0x1A11
#define mmDCP0_GRPH_X_END__SI__VI                       0x1A0D
#define mmDCP0_GRPH_X_START__SI__VI                     0x1A0B
#define mmDCP0_GRPH_Y_END__SI__VI                       0x1A0E
#define mmDCP0_GRPH_Y_START__SI__VI                     0x1A0C
#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL__SI__VI           0x1A2C
#define mmDCP0_OVL_CONTROL1__SI__VI                     0x1A1D
#define mmDCP0_OVL_CONTROL2__SI__VI                     0x1A1E
#define mmDCP0_OVL_DFQ_CONTROL__SI__VI                  0x1A29
#define mmDCP0_OVL_DFQ_STATUS__SI__VI                   0x1A2A
#define mmDCP0_OVL_ENABLE__SI__VI                       0x1A1C
#define mmDCP0_OVL_END__SI__VI                          0x1A26
#define mmDCP0_OVL_PITCH__SI__VI                        0x1A21
#define mmDCP0_OVL_START__SI__VI                        0x1A25
#define mmDCP0_OVL_SURFACE_ADDRESS                      0x1A20
#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH                 0x1A22
#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI   0x1A2B
#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE__SI__VI        0x1A28
#define mmDCP0_OVL_SURFACE_OFFSET_X__SI__VI             0x1A23
#define mmDCP0_OVL_SURFACE_OFFSET_Y__SI__VI             0x1A24
#define mmDCP0_OVL_SWAP_CNTL__SI__VI                    0x1A1F
#define mmDCP0_OVL_UPDATE__SI__VI                       0x1A27
#define mmDCP1_CUR_COLOR1__SI                           0x1D6C
#define mmDCP1_CUR_COLOR2__SI                           0x1D6D
#define mmDCP1_CUR_CONTROL__SI                          0x1D66
#define mmDCP1_CUR_HOT_SPOT__SI                         0x1D6B
#define mmDCP1_CUR_POSITION__SI                         0x1D6A
#define mmDCP1_CUR_SIZE__SI                             0x1D68
#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH__SI             0x1D69
#define mmDCP1_CUR_SURFACE_ADDRESS__SI                  0x1D67
#define mmDCP1_CUR_UPDATE__SI                           0x1D6E
#define mmDCP1_DCP_CRC_CONTROL__SI                      0x1D87
#define mmDCP1_DCP_CRC_CURRENT__SI                      0x1D89
#define mmDCP1_DCP_CRC_LAST__SI                         0x1D8B
#define mmDCP1_DCP_CRC_MASK__SI                         0x1D88
#define mmDCP1_DCP_DEBUG__SI                            0x1D8D
#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI        0x1D91
#define mmDCP1_DCP_TEST_DEBUG_DATA__SI                  0x1D96
#define mmDCP1_DCP_TEST_DEBUG_INDEX__SI                 0x1D95
#define mmDCP1_DC_LUT_30_COLOR__SI                      0x1D7C
#define mmDCP1_DC_LUT_AUTOFILL__SI                      0x1D7F
#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE__SI             0x1D81
#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN__SI            0x1D82
#define mmDCP1_DC_LUT_BLACK_OFFSET_RED__SI              0x1D83
#define mmDCP1_DC_LUT_CONTROL__SI                       0x1D80
#define mmDCP1_DC_LUT_PWL_DATA__SI                      0x1D7B
#define mmDCP1_DC_LUT_RW_INDEX__SI                      0x1D79
#define mmDCP1_DC_LUT_RW_MODE__SI                       0x1D78
#define mmDCP1_DC_LUT_SEQ_COLOR__SI                     0x1D7A
#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE__SI             0x1D84
#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN__SI            0x1D85
#define mmDCP1_DC_LUT_WHITE_OFFSET_RED__SI              0x1D86
#define mmDCP1_DC_LUT_WRITE_EN_MASK__SI                 0x1D7E
#define mmDCP1_GRPH_COMPRESS_PITCH__SI                  0x1D1A
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI   0x1D1B
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS__SI        0x1D19
#define mmDCP1_GRPH_DFQ_CONTROL__SI                     0x1D14
#define mmDCP1_GRPH_DFQ_STATUS__SI                      0x1D15
#define mmDCP1_GRPH_ENABLE__SI                          0x1D00
#define mmDCP1_GRPH_INTERRUPT_CONTROL__SI               0x1D17
#define mmDCP1_GRPH_INTERRUPT_STATUS__SI                0x1D16
#define mmDCP1_GRPH_LUT_10BIT_BYPASS__SI                0x1D02
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI    0x1D07
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI  0x1D08
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS__SI       0x1D05
#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI      0x1D18
#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE__SI           0x1D13
#define mmDCP1_GRPH_SURFACE_OFFSET_X__SI                0x1D09
#define mmDCP1_GRPH_SURFACE_OFFSET_Y__SI                0x1D0A
#define mmDCP1_GRPH_SWAP_CNTL__SI                       0x1D03
#define mmDCP1_GRPH_X_END__SI                           0x1D0D
#define mmDCP1_GRPH_X_START__SI                         0x1D0B
#define mmDCP1_GRPH_Y_END__SI                           0x1D0E
#define mmDCP1_GRPH_Y_START__SI                         0x1D0C
#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL__SI               0x1D2C
#define mmDCP1_OVL_CONTROL1__SI                         0x1D1D
#define mmDCP1_OVL_CONTROL2__SI                         0x1D1E
#define mmDCP1_OVL_DFQ_CONTROL__SI                      0x1D29
#define mmDCP1_OVL_DFQ_STATUS__SI                       0x1D2A
#define mmDCP1_OVL_ENABLE__SI                           0x1D1C
#define mmDCP1_OVL_END__SI                              0x1D26
#define mmDCP1_OVL_PITCH__SI                            0x1D21
#define mmDCP1_OVL_START__SI                            0x1D25
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI       0x1D2B
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH__SI             0x1D22
#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE__SI            0x1D28
#define mmDCP1_OVL_SURFACE_OFFSET_X__SI                 0x1D23
#define mmDCP1_OVL_SURFACE_OFFSET_Y__SI                 0x1D24
#define mmDCP1_OVL_SWAP_CNTL__SI                        0x1D1F
#define mmDCP1_OVL_UPDATE__SI                           0x1D27
#define mmDCP2_CUR_COLOR1__SI                           0x406C
#define mmDCP2_CUR_COLOR2__SI                           0x406D
#define mmDCP2_CUR_CONTROL__SI                          0x4066
#define mmDCP2_CUR_HOT_SPOT__SI                         0x406B
#define mmDCP2_CUR_POSITION__SI                         0x406A
#define mmDCP2_CUR_SIZE__SI                             0x4068
#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH__SI             0x4069
#define mmDCP2_CUR_SURFACE_ADDRESS__SI                  0x4067
#define mmDCP2_CUR_UPDATE__SI                           0x406E
#define mmDCP2_DCP_CRC_CONTROL__SI                      0x4087
#define mmDCP2_DCP_CRC_CURRENT__SI                      0x4089
#define mmDCP2_DCP_CRC_LAST__SI                         0x408B
#define mmDCP2_DCP_CRC_MASK__SI                         0x4088
#define mmDCP2_DCP_DEBUG__SI                            0x408D
#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI        0x4091
#define mmDCP2_DCP_TEST_DEBUG_DATA__SI                  0x4096
#define mmDCP2_DCP_TEST_DEBUG_INDEX__SI                 0x4095
#define mmDCP2_DC_LUT_30_COLOR__SI                      0x407C
#define mmDCP2_DC_LUT_AUTOFILL__SI                      0x407F
#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE__SI             0x4081
#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN__SI            0x4082
#define mmDCP2_DC_LUT_BLACK_OFFSET_RED__SI              0x4083
#define mmDCP2_DC_LUT_CONTROL__SI                       0x4080
#define mmDCP2_DC_LUT_PWL_DATA__SI                      0x407B
#define mmDCP2_DC_LUT_RW_INDEX__SI                      0x4079
#define mmDCP2_DC_LUT_RW_MODE__SI                       0x4078
#define mmDCP2_DC_LUT_SEQ_COLOR__SI                     0x407A
#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE__SI             0x4084
#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN__SI            0x4085
#define mmDCP2_DC_LUT_WHITE_OFFSET_RED__SI              0x4086
#define mmDCP2_DC_LUT_WRITE_EN_MASK__SI                 0x407E
#define mmDCP2_GRPH_COMPRESS_PITCH__SI                  0x401A
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI   0x401B
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS__SI        0x4019
#define mmDCP2_GRPH_DFQ_CONTROL__SI                     0x4014
#define mmDCP2_GRPH_DFQ_STATUS__SI                      0x4015
#define mmDCP2_GRPH_ENABLE__SI                          0x4000
#define mmDCP2_GRPH_INTERRUPT_CONTROL__SI               0x4017
#define mmDCP2_GRPH_INTERRUPT_STATUS__SI                0x4016
#define mmDCP2_GRPH_LUT_10BIT_BYPASS__SI                0x4002
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI    0x4007
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI  0x4008
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS__SI       0x4005
#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI      0x4018
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE__SI           0x4013
#define mmDCP2_GRPH_SURFACE_OFFSET_X__SI                0x4009
#define mmDCP2_GRPH_SURFACE_OFFSET_Y__SI                0x400A
#define mmDCP2_GRPH_SWAP_CNTL__SI                       0x4003
#define mmDCP2_GRPH_X_END__SI                           0x400D
#define mmDCP2_GRPH_X_START__SI                         0x400B
#define mmDCP2_GRPH_Y_END__SI                           0x400E
#define mmDCP2_GRPH_Y_START__SI                         0x400C
#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL__SI               0x402C
#define mmDCP2_OVL_CONTROL1__SI                         0x401D
#define mmDCP2_OVL_CONTROL2__SI                         0x401E
#define mmDCP2_OVL_DFQ_CONTROL__SI                      0x4029
#define mmDCP2_OVL_DFQ_STATUS__SI                       0x402A
#define mmDCP2_OVL_ENABLE__SI                           0x401C
#define mmDCP2_OVL_END__SI                              0x4026
#define mmDCP2_OVL_PITCH__SI                            0x4021
#define mmDCP2_OVL_START__SI                            0x4025
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI       0x402B
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH__SI             0x4022
#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE__SI            0x4028
#define mmDCP2_OVL_SURFACE_OFFSET_X__SI                 0x4023
#define mmDCP2_OVL_SURFACE_OFFSET_Y__SI                 0x4024
#define mmDCP2_OVL_SWAP_CNTL__SI                        0x401F
#define mmDCP2_OVL_UPDATE__SI                           0x4027
#define mmDCP3_CUR_COLOR1__SI                           0x436C
#define mmDCP3_CUR_COLOR2__SI                           0x436D
#define mmDCP3_CUR_CONTROL__SI                          0x4366
#define mmDCP3_CUR_HOT_SPOT__SI                         0x436B
#define mmDCP3_CUR_POSITION__SI                         0x436A
#define mmDCP3_CUR_SIZE__SI                             0x4368
#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH__SI             0x4369
#define mmDCP3_CUR_SURFACE_ADDRESS__SI                  0x4367
#define mmDCP3_CUR_UPDATE__SI                           0x436E
#define mmDCP3_DCP_CRC_CONTROL__SI                      0x4387
#define mmDCP3_DCP_CRC_CURRENT__SI                      0x4389
#define mmDCP3_DCP_CRC_LAST__SI                         0x438B
#define mmDCP3_DCP_CRC_MASK__SI                         0x4388
#define mmDCP3_DCP_DEBUG__SI                            0x438D
#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI        0x4391
#define mmDCP3_DCP_TEST_DEBUG_DATA__SI                  0x4396
#define mmDCP3_DCP_TEST_DEBUG_INDEX__SI                 0x4395
#define mmDCP3_DC_LUT_30_COLOR__SI                      0x437C
#define mmDCP3_DC_LUT_AUTOFILL__SI                      0x437F
#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE__SI             0x4381
#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN__SI            0x4382
#define mmDCP3_DC_LUT_BLACK_OFFSET_RED__SI              0x4383
#define mmDCP3_DC_LUT_CONTROL__SI                       0x4380
#define mmDCP3_DC_LUT_PWL_DATA__SI                      0x437B
#define mmDCP3_DC_LUT_RW_INDEX__SI                      0x4379
#define mmDCP3_DC_LUT_RW_MODE__SI                       0x4378
#define mmDCP3_DC_LUT_SEQ_COLOR__SI                     0x437A
#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE__SI             0x4384
#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN__SI            0x4385
#define mmDCP3_DC_LUT_WHITE_OFFSET_RED__SI              0x4386
#define mmDCP3_DC_LUT_WRITE_EN_MASK__SI                 0x437E
#define mmDCP3_GRPH_COMPRESS_PITCH__SI                  0x431A
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI   0x431B
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS__SI        0x4319
#define mmDCP3_GRPH_DFQ_CONTROL__SI                     0x4314
#define mmDCP3_GRPH_DFQ_STATUS__SI                      0x4315
#define mmDCP3_GRPH_ENABLE__SI                          0x4300
#define mmDCP3_GRPH_INTERRUPT_CONTROL__SI               0x4317
#define mmDCP3_GRPH_INTERRUPT_STATUS__SI                0x4316
#define mmDCP3_GRPH_LUT_10BIT_BYPASS__SI                0x4302
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI    0x4307
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI  0x4308
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS__SI       0x4305
#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI      0x4318
#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE__SI           0x4313
#define mmDCP3_GRPH_SURFACE_OFFSET_X__SI                0x4309
#define mmDCP3_GRPH_SURFACE_OFFSET_Y__SI                0x430A
#define mmDCP3_GRPH_SWAP_CNTL__SI                       0x4303
#define mmDCP3_GRPH_X_END__SI                           0x430D
#define mmDCP3_GRPH_X_START__SI                         0x430B
#define mmDCP3_GRPH_Y_END__SI                           0x430E
#define mmDCP3_GRPH_Y_START__SI                         0x430C
#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL__SI               0x432C
#define mmDCP3_OVL_CONTROL1__SI                         0x431D
#define mmDCP3_OVL_CONTROL2__SI                         0x431E
#define mmDCP3_OVL_DFQ_CONTROL__SI                      0x4329
#define mmDCP3_OVL_DFQ_STATUS__SI                       0x432A
#define mmDCP3_OVL_ENABLE__SI                           0x431C
#define mmDCP3_OVL_END__SI                              0x4326
#define mmDCP3_OVL_PITCH__SI                            0x4321
#define mmDCP3_OVL_START__SI                            0x4325
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI       0x432B
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH__SI             0x4322
#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE__SI            0x4328
#define mmDCP3_OVL_SURFACE_OFFSET_X__SI                 0x4323
#define mmDCP3_OVL_SURFACE_OFFSET_Y__SI                 0x4324
#define mmDCP3_OVL_SWAP_CNTL__SI                        0x431F
#define mmDCP3_OVL_UPDATE__SI                           0x4327
#define mmDCP4_CUR_COLOR1__SI                           0x466C
#define mmDCP4_CUR_COLOR2__SI                           0x466D
#define mmDCP4_CUR_CONTROL__SI                          0x4666
#define mmDCP4_CUR_HOT_SPOT__SI                         0x466B
#define mmDCP4_CUR_POSITION__SI                         0x466A
#define mmDCP4_CUR_SIZE__SI                             0x4668
#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH__SI             0x4669
#define mmDCP4_CUR_SURFACE_ADDRESS__SI                  0x4667
#define mmDCP4_CUR_UPDATE__SI                           0x466E
#define mmDCP4_DCP_CRC_CONTROL__SI                      0x4687
#define mmDCP4_DCP_CRC_CURRENT__SI                      0x4689
#define mmDCP4_DCP_CRC_LAST__SI                         0x468B
#define mmDCP4_DCP_CRC_MASK__SI                         0x4688
#define mmDCP4_DCP_DEBUG__SI                            0x468D
#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI        0x4691
#define mmDCP4_DCP_TEST_DEBUG_DATA__SI                  0x4696
#define mmDCP4_DCP_TEST_DEBUG_INDEX__SI                 0x4695
#define mmDCP4_DC_LUT_30_COLOR__SI                      0x467C
#define mmDCP4_DC_LUT_AUTOFILL__SI                      0x467F
#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE__SI             0x4681
#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN__SI            0x4682
#define mmDCP4_DC_LUT_BLACK_OFFSET_RED__SI              0x4683
#define mmDCP4_DC_LUT_CONTROL__SI                       0x4680
#define mmDCP4_DC_LUT_PWL_DATA__SI                      0x467B
#define mmDCP4_DC_LUT_RW_INDEX__SI                      0x4679
#define mmDCP4_DC_LUT_RW_MODE__SI                       0x4678
#define mmDCP4_DC_LUT_SEQ_COLOR__SI                     0x467A
#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE__SI             0x4684
#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN__SI            0x4685
#define mmDCP4_DC_LUT_WHITE_OFFSET_RED__SI              0x4686
#define mmDCP4_DC_LUT_WRITE_EN_MASK__SI                 0x467E
#define mmDCP4_GRPH_COMPRESS_PITCH__SI                  0x461A
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI   0x461B
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS__SI        0x4619
#define mmDCP4_GRPH_DFQ_CONTROL__SI                     0x4614
#define mmDCP4_GRPH_DFQ_STATUS__SI                      0x4615
#define mmDCP4_GRPH_ENABLE__SI                          0x4600
#define mmDCP4_GRPH_INTERRUPT_CONTROL__SI               0x4617
#define mmDCP4_GRPH_INTERRUPT_STATUS__SI                0x4616
#define mmDCP4_GRPH_LUT_10BIT_BYPASS__SI                0x4602
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI    0x4607
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI  0x4608
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS__SI       0x4605
#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI      0x4618
#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE__SI           0x4613
#define mmDCP4_GRPH_SURFACE_OFFSET_X__SI                0x4609
#define mmDCP4_GRPH_SURFACE_OFFSET_Y__SI                0x460A
#define mmDCP4_GRPH_SWAP_CNTL__SI                       0x4603
#define mmDCP4_GRPH_X_END__SI                           0x460D
#define mmDCP4_GRPH_X_START__SI                         0x460B
#define mmDCP4_GRPH_Y_END__SI                           0x460E
#define mmDCP4_GRPH_Y_START__SI                         0x460C
#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL__SI               0x462C
#define mmDCP4_OVL_CONTROL1__SI                         0x461D
#define mmDCP4_OVL_CONTROL2__SI                         0x461E
#define mmDCP4_OVL_DFQ_CONTROL__SI                      0x4629
#define mmDCP4_OVL_DFQ_STATUS__SI                       0x462A
#define mmDCP4_OVL_ENABLE__SI                           0x461C
#define mmDCP4_OVL_END__SI                              0x4626
#define mmDCP4_OVL_PITCH__SI                            0x4621
#define mmDCP4_OVL_START__SI                            0x4625
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI       0x462B
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH__SI             0x4622
#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE__SI            0x4628
#define mmDCP4_OVL_SURFACE_OFFSET_X__SI                 0x4623
#define mmDCP4_OVL_SURFACE_OFFSET_Y__SI                 0x4624
#define mmDCP4_OVL_SWAP_CNTL__SI                        0x461F
#define mmDCP4_OVL_UPDATE__SI                           0x4627
#define mmDCP5_CUR_COLOR1__SI                           0x496C
#define mmDCP5_CUR_COLOR2__SI                           0x496D
#define mmDCP5_CUR_CONTROL__SI                          0x4966
#define mmDCP5_CUR_HOT_SPOT__SI                         0x496B
#define mmDCP5_CUR_POSITION__SI                         0x496A
#define mmDCP5_CUR_SIZE__SI                             0x4968
#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH__SI             0x4969
#define mmDCP5_CUR_SURFACE_ADDRESS__SI                  0x4967
#define mmDCP5_CUR_UPDATE__SI                           0x496E
#define mmDCP5_DCP_CRC_CONTROL__SI                      0x4987
#define mmDCP5_DCP_CRC_CURRENT__SI                      0x4989
#define mmDCP5_DCP_CRC_LAST__SI                         0x498B
#define mmDCP5_DCP_CRC_MASK__SI                         0x4988
#define mmDCP5_DCP_DEBUG__SI                            0x498D
#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI        0x4991
#define mmDCP5_DCP_TEST_DEBUG_DATA__SI                  0x4996
#define mmDCP5_DCP_TEST_DEBUG_INDEX__SI                 0x4995
#define mmDCP5_DC_LUT_30_COLOR__SI                      0x497C
#define mmDCP5_DC_LUT_AUTOFILL__SI                      0x497F
#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE__SI             0x4981
#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN__SI            0x4982
#define mmDCP5_DC_LUT_BLACK_OFFSET_RED__SI              0x4983
#define mmDCP5_DC_LUT_CONTROL__SI                       0x4980
#define mmDCP5_DC_LUT_PWL_DATA__SI                      0x497B
#define mmDCP5_DC_LUT_RW_INDEX__SI                      0x4979
#define mmDCP5_DC_LUT_RW_MODE__SI                       0x4978
#define mmDCP5_DC_LUT_SEQ_COLOR__SI                     0x497A
#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE__SI             0x4984
#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN__SI            0x4985
#define mmDCP5_DC_LUT_WHITE_OFFSET_RED__SI              0x4986
#define mmDCP5_DC_LUT_WRITE_EN_MASK__SI                 0x497E
#define mmDCP5_GRPH_COMPRESS_PITCH__SI                  0x491A
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI   0x491B
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS__SI        0x4919
#define mmDCP5_GRPH_DFQ_CONTROL__SI                     0x4914
#define mmDCP5_GRPH_DFQ_STATUS__SI                      0x4915
#define mmDCP5_GRPH_ENABLE__SI                          0x4900
#define mmDCP5_GRPH_INTERRUPT_CONTROL__SI               0x4917
#define mmDCP5_GRPH_INTERRUPT_STATUS__SI                0x4916
#define mmDCP5_GRPH_LUT_10BIT_BYPASS__SI                0x4902
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI    0x4907
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI  0x4908
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS__SI       0x4905
#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI      0x4918
#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE__SI           0x4913
#define mmDCP5_GRPH_SURFACE_OFFSET_X__SI                0x4909
#define mmDCP5_GRPH_SURFACE_OFFSET_Y__SI                0x490A
#define mmDCP5_GRPH_SWAP_CNTL__SI                       0x4903
#define mmDCP5_GRPH_X_END__SI                           0x490D
#define mmDCP5_GRPH_X_START__SI                         0x490B
#define mmDCP5_GRPH_Y_END__SI                           0x490E
#define mmDCP5_GRPH_Y_START__SI                         0x490C
#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL__SI               0x492C
#define mmDCP5_OVL_CONTROL1__SI                         0x491D
#define mmDCP5_OVL_CONTROL2__SI                         0x491E
#define mmDCP5_OVL_DFQ_CONTROL__SI                      0x4929
#define mmDCP5_OVL_DFQ_STATUS__SI                       0x492A
#define mmDCP5_OVL_ENABLE__SI                           0x491C
#define mmDCP5_OVL_END__SI                              0x4926
#define mmDCP5_OVL_PITCH__SI                            0x4921
#define mmDCP5_OVL_START__SI                            0x4925
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI       0x492B
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH__SI             0x4922
#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE__SI            0x4928
#define mmDCP5_OVL_SURFACE_OFFSET_X__SI                 0x4923
#define mmDCP5_OVL_SURFACE_OFFSET_Y__SI                 0x4924
#define mmDCP5_OVL_SWAP_CNTL__SI                        0x491F
#define mmDCP5_OVL_UPDATE__SI                           0x4927
#define mmDCP_CRC_CONTROL__SI__VI                       0x1A87
#define mmDCP_CRC_CURRENT__SI__VI                       0x1A89
#define mmDCP_CRC_LAST__SI__VI                          0x1A8B
#define mmDCP_CRC_MASK__SI__VI                          0x1A88
#define mmDCP_DEBUG__SI__VI                             0x1A8D
#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI         0x1A91
#define mmDCP_TEST_DEBUG_DATA__SI__VI                   0x1A96
#define mmDCP_TEST_DEBUG_INDEX__SI__VI                  0x1A95
#define mmDC_ABM1_ACE_CNTL_MISC__SI__VI                 0x1641
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0__SI__VI            0x163A
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1__SI__VI            0x163B
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2__SI__VI            0x163C
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3__SI__VI            0x163D
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4__SI__VI            0x163E
#define mmDC_ABM1_ACE_THRES_12__SI__VI                  0x163F
#define mmDC_ABM1_ACE_THRES_34__SI__VI                  0x1640
#define mmDC_ABM1_BL_MASTER_LOCK__SI__VI                0x169C
#define mmDC_ABM1_CNTL__SI__VI                          0x1638
#define mmDC_ABM1_DEBUG_MISC__SI__VI                    0x1649
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS__SI__VI        0x164A
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI__VI      0x1659
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI__VI        0x1656
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI__VI        0x1657
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI__VI      0x165A
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI__VI       0x1658
#define mmDC_ABM1_HG_MISC_CTRL__SI__VI                  0x164B
#define mmDC_ABM1_HG_RESULT_10__SI__VI                  0x1664
#define mmDC_ABM1_HG_RESULT_11__SI__VI                  0x1665
#define mmDC_ABM1_HG_RESULT_12__SI__VI                  0x1666
#define mmDC_ABM1_HG_RESULT_13__SI__VI                  0x1667
#define mmDC_ABM1_HG_RESULT_14__SI__VI                  0x1668
#define mmDC_ABM1_HG_RESULT_15__SI__VI                  0x1669
#define mmDC_ABM1_HG_RESULT_16__SI__VI                  0x166A
#define mmDC_ABM1_HG_RESULT_17__SI__VI                  0x166B
#define mmDC_ABM1_HG_RESULT_18__SI__VI                  0x166C
#define mmDC_ABM1_HG_RESULT_19__SI__VI                  0x166D
#define mmDC_ABM1_HG_RESULT_1__SI__VI                   0x165B
#define mmDC_ABM1_HG_RESULT_20__SI__VI                  0x166E
#define mmDC_ABM1_HG_RESULT_21__SI__VI                  0x166F
#define mmDC_ABM1_HG_RESULT_22__SI__VI                  0x1670
#define mmDC_ABM1_HG_RESULT_23__SI__VI                  0x1671
#define mmDC_ABM1_HG_RESULT_24__SI__VI                  0x1672
#define mmDC_ABM1_HG_RESULT_2__SI__VI                   0x165C
#define mmDC_ABM1_HG_RESULT_3__SI__VI                   0x165D
#define mmDC_ABM1_HG_RESULT_4__SI__VI                   0x165E
#define mmDC_ABM1_HG_RESULT_5__SI__VI                   0x165F
#define mmDC_ABM1_HG_RESULT_6__SI__VI                   0x1660
#define mmDC_ABM1_HG_RESULT_7__SI__VI                   0x1661
#define mmDC_ABM1_HG_RESULT_8__SI__VI                   0x1662
#define mmDC_ABM1_HG_RESULT_9__SI__VI                   0x1663
#define mmDC_ABM1_HG_SAMPLE_RATE__SI__VI                0x1654
#define mmDC_ABM1_IPCSC_COEFF_SEL__SI__VI               0x1639
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI__VI      0x164E
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI__VI      0x1653
#define mmDC_ABM1_LS_MIN_MAX_LUMA__SI__VI               0x164D
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI__VI  0x1651
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI__VI      0x1652
#define mmDC_ABM1_LS_OVR_SCAN_BIN__SI__VI               0x1650
#define mmDC_ABM1_LS_PIXEL_COUNT__SI__VI                0x164F
#define mmDC_ABM1_LS_SAMPLE_RATE__SI__VI                0x1655
#define mmDC_ABM1_LS_SUM_OF_LUMA__SI__VI                0x164C
#define mmDC_DMCU_SCRATCH__SI__VI                       0x1618
#define mmDC_GENERICA__SI                               0x1900
#define mmDC_GENERICB__SI                               0x1901
#define mmDC_GPIO_DDC1_A__SI                            0x190D
#define mmDC_GPIO_DDC1_EN__SI                           0x190E
#define mmDC_GPIO_DDC1_MASK__SI                         0x190C
#define mmDC_GPIO_DDC1_Y__SI                            0x190F
#define mmDC_GPIO_DDC2_A__SI                            0x1911
#define mmDC_GPIO_DDC2_EN__SI                           0x1912
#define mmDC_GPIO_DDC2_MASK__SI                         0x1910
#define mmDC_GPIO_DDC2_Y__SI                            0x1913
#define mmDC_GPIO_DDC3_A__SI                            0x1915
#define mmDC_GPIO_DDC3_EN__SI                           0x1916
#define mmDC_GPIO_DDC3_MASK__SI                         0x1914
#define mmDC_GPIO_DDC3_Y__SI                            0x1917
#define mmDC_GPIO_DDC4_A__SI                            0x1919
#define mmDC_GPIO_DDC4_EN__SI                           0x191A
#define mmDC_GPIO_DDC4_MASK__SI                         0x1918
#define mmDC_GPIO_DDC4_Y__SI                            0x191B
#define mmDC_GPIO_DDC5_A__SI                            0x191D
#define mmDC_GPIO_DDC5_EN__SI                           0x191E
#define mmDC_GPIO_DDC5_MASK__SI                         0x191C
#define mmDC_GPIO_DDC5_Y__SI                            0x191F
#define mmDC_GPIO_DDC6_A__SI                            0x1921
#define mmDC_GPIO_DDC6_EN__SI                           0x1922
#define mmDC_GPIO_DDC6_MASK__SI                         0x1920
#define mmDC_GPIO_DDC6_Y__SI                            0x1923
#define mmDC_GPIO_DEBUG__SI                             0x1946
#define mmDC_GPIO_DVODATA_A__SI                         0x1909
#define mmDC_GPIO_DVODATA_EN__SI                        0x190A
#define mmDC_GPIO_DVODATA_MASK__SI                      0x1908
#define mmDC_GPIO_DVODATA_Y__SI                         0x190B
#define mmDC_GPIO_GENERIC_A__SI                         0x1905
#define mmDC_GPIO_GENERIC_EN__SI                        0x1906
#define mmDC_GPIO_GENERIC_MASK__SI                      0x1904
#define mmDC_GPIO_GENERIC_Y__SI                         0x1907
#define mmDC_GPIO_HPD_A__SI                             0x192D
#define mmDC_GPIO_HPD_EN__SI                            0x192E
#define mmDC_GPIO_HPD_MASK__SI                          0x192C
#define mmDC_GPIO_HPD_Y__SI                             0x192F
#define mmDC_GPIO_PAD_STRENGTH_1__SI                    0x1944
#define mmDC_GPIO_PAD_STRENGTH_2__SI                    0x1945
#define mmDC_GPIO_PWRSEQ_A__SI                          0x1941
#define mmDC_GPIO_PWRSEQ_EN__SI                         0x1942
#define mmDC_GPIO_PWRSEQ_MASK__SI                       0x1940
#define mmDC_GPIO_PWRSEQ_Y__SI                          0x1943
#define mmDC_GPIO_SYNCA_A__SI                           0x1925
#define mmDC_GPIO_SYNCA_EN__SI                          0x1926
#define mmDC_GPIO_SYNCA_MASK__SI                        0x1924
#define mmDC_GPIO_SYNCA_Y__SI                           0x1927
#define mmDC_GPU_TIMER_READ_CNTL__SI                    0x1972
#define mmDC_GPU_TIMER_READ__SI                         0x1971
#define mmDC_GPU_TIMER_START_POSITION__SI               0x1970
#define mmDC_HPD1_CONTROL__SI                           0x1809
#define mmDC_HPD1_INT_CONTROL__SI                       0x1808
#define mmDC_HPD1_INT_STATUS__SI                        0x1807
#define mmDC_HPD2_CONTROL__SI                           0x180C
#define mmDC_HPD2_INT_CONTROL__SI                       0x180B
#define mmDC_HPD2_INT_STATUS__SI                        0x180A
#define mmDC_HPD3_CONTROL__SI                           0x180F
#define mmDC_HPD3_INT_CONTROL__SI                       0x180E
#define mmDC_HPD3_INT_STATUS__SI                        0x180D
#define mmDC_HPD4_CONTROL__SI                           0x1812
#define mmDC_HPD4_INT_CONTROL__SI                       0x1811
#define mmDC_HPD4_INT_STATUS__SI                        0x1810
#define mmDC_HPD5_CONTROL__SI                           0x1815
#define mmDC_HPD5_INT_CONTROL__SI                       0x1814
#define mmDC_HPD5_INT_STATUS__SI                        0x1813
#define mmDC_HPD6_CONTROL__SI                           0x1818
#define mmDC_HPD6_INT_CONTROL__SI                       0x1817
#define mmDC_HPD6_INT_STATUS__SI                        0x1816
#define mmDC_I2C_ARBITRATION__SI                        0x181A
#define mmDC_I2C_CONTROL__SI                            0x1819
#define mmDC_I2C_DATA__SI                               0x1833
#define mmDC_I2C_DDC1_HW_STATUS__SI                     0x181D
#define mmDC_I2C_DDC1_SETUP__SI                         0x1824
#define mmDC_I2C_DDC1_SPEED__SI                         0x1823
#define mmDC_I2C_DDC2_HW_STATUS__SI                     0x181E
#define mmDC_I2C_DDC2_SETUP__SI                         0x1826
#define mmDC_I2C_DDC2_SPEED__SI                         0x1825
#define mmDC_I2C_DDC3_HW_STATUS__SI                     0x181F
#define mmDC_I2C_DDC3_SETUP__SI                         0x1828
#define mmDC_I2C_DDC3_SPEED__SI                         0x1827
#define mmDC_I2C_DDC4_HW_STATUS__SI                     0x1820
#define mmDC_I2C_DDC4_SETUP__SI                         0x182A
#define mmDC_I2C_DDC4_SPEED__SI                         0x1829
#define mmDC_I2C_DDC5_HW_STATUS__SI                     0x1821
#define mmDC_I2C_DDC5_SETUP__SI                         0x182C
#define mmDC_I2C_DDC5_SPEED__SI                         0x182B
#define mmDC_I2C_DDC6_HW_STATUS__SI                     0x1822
#define mmDC_I2C_DDC6_SETUP__SI                         0x182E
#define mmDC_I2C_DDC6_SPEED__SI                         0x182D
#define mmDC_I2C_INTERRUPT_CONTROL__SI                  0x181B
#define mmDC_I2C_SW_STATUS__SI                          0x181C
#define mmDC_I2C_TRANSACTION0__SI                       0x182F
#define mmDC_I2C_TRANSACTION1__SI                       0x1830
#define mmDC_I2C_TRANSACTION2__SI                       0x1831
#define mmDC_I2C_TRANSACTION3__SI                       0x1832
#define mmDC_LUT_30_COLOR__SI__VI                       0x1A7C
#define mmDC_LUT_AUTOFILL__SI__VI                       0x1A7F
#define mmDC_LUT_BLACK_OFFSET_BLUE__SI__VI              0x1A81
#define mmDC_LUT_BLACK_OFFSET_GREEN__SI__VI             0x1A82
#define mmDC_LUT_BLACK_OFFSET_RED__SI__VI               0x1A83
#define mmDC_LUT_CONTROL__SI__VI                        0x1A80
#define mmDC_LUT_PWL_DATA__SI__VI                       0x1A7B
#define mmDC_LUT_RW_INDEX__SI__VI                       0x1A79
#define mmDC_LUT_RW_MODE__SI__VI                        0x1A78
#define mmDC_LUT_SEQ_COLOR__SI__VI                      0x1A7A
#define mmDC_LUT_WHITE_OFFSET_BLUE__SI__VI              0x1A84
#define mmDC_LUT_WHITE_OFFSET_GREEN__SI__VI             0x1A85
#define mmDC_LUT_WHITE_OFFSET_RED__SI__VI               0x1A86
#define mmDC_LUT_WRITE_EN_MASK__SI__VI                  0x1A7E
#define mmDC_MVP_LB_CONTROL__SI                         0x1ADB
#define mmDC_PAD_EXTERN_SIG__SI                         0x1902
#define mmDC_PINSTRAPS__SI                              0x1954
#define mmDC_REF_CLK_CNTL__SI                           0x1903
#define mmDC_TEST_DEBUG_DATA__SI                        0x186D
#define mmDC_TEST_DEBUG_INDEX__SI                       0x186C
#define mmDEBUG_DATA                                    0x203D
#define mmDEBUG_INDEX                                   0x203C
#define mmDENTIST_DISPCLK_CNTL__SI                      0x015F
#define mmDESKTOP_HEIGHT__SI                            0x1AC1
#define mmDIDT_IND_DATA__CI__VI                         0x3281
#define mmDIDT_IND_INDEX__CI__VI                        0x3280
#define mmDIG0_AFMT_60958_0__SI                         0x1C41
#define mmDIG0_AFMT_60958_1__SI                         0x1C42
#define mmDIG0_AFMT_60958_2__SI                         0x1C48
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL__SI               0x1C43
#define mmDIG0_AFMT_AUDIO_CRC_RESULT__SI                0x1C49
#define mmDIG0_AFMT_AUDIO_INFO0__SI                     0x1C3F
#define mmDIG0_AFMT_AUDIO_INFO1__SI                     0x1C40
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2__SI           0x1C17
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL__SI            0x1C4B
#define mmDIG0_AFMT_AVI_INFO0__SI                       0x1C21
#define mmDIG0_AFMT_AVI_INFO1__SI                       0x1C22
#define mmDIG0_AFMT_AVI_INFO2__SI                       0x1C23
#define mmDIG0_AFMT_AVI_INFO3__SI                       0x1C24
#define mmDIG0_AFMT_INFOFRAME_CONTROL0__SI              0x1C4D
#define mmDIG0_AFMT_ISRC1_0__SI                         0x1C18
#define mmDIG0_AFMT_ISRC1_1__SI                         0x1C19
#define mmDIG0_AFMT_ISRC1_2__SI                         0x1C1A
#define mmDIG0_AFMT_ISRC1_3__SI                         0x1C1B
#define mmDIG0_AFMT_ISRC1_4__SI                         0x1C1C
#define mmDIG0_AFMT_ISRC2_0__SI                         0x1C1D
#define mmDIG0_AFMT_ISRC2_1__SI                         0x1C1E
#define mmDIG0_AFMT_ISRC2_2__SI                         0x1C1F
#define mmDIG0_AFMT_ISRC2_3__SI                         0x1C20
#define mmDIG0_AFMT_MPEG_INFO0__SI                      0x1C25
#define mmDIG0_AFMT_MPEG_INFO1__SI                      0x1C26
#define mmDIG0_AFMT_RAMP_CONTROL0__SI                   0x1C44
#define mmDIG0_AFMT_RAMP_CONTROL1__SI                   0x1C45
#define mmDIG0_AFMT_RAMP_CONTROL2__SI                   0x1C46
#define mmDIG0_AFMT_RAMP_CONTROL3__SI                   0x1C47
#define mmDIG0_AFMT_STATUS__SI                          0x1C4A
#define mmDIG0_AFMT_VBI_PACKET_CONTROL__SI              0x1C4C
#define mmDIG0_DIG_CLOCK_PATTERN__SI                    0x1C03
#define mmDIG0_DIG_OUTPUT_CRC_CNTL__SI                  0x1C01
#define mmDIG0_DIG_OUTPUT_CRC_RESULT__SI                0x1C02
#define mmDIG0_DIG_RANDOM_PATTERN_SEED__SI              0x1C05
#define mmDIG0_DIG_TEST_PATTERN__SI                     0x1C04
#define mmDIG0_HDMI_ACR_32_0__SI                        0x1C37
#define mmDIG0_HDMI_ACR_32_1__SI                        0x1C38
#define mmDIG0_HDMI_ACR_44_0__SI                        0x1C39
#define mmDIG0_HDMI_ACR_44_1__SI                        0x1C3A
#define mmDIG0_HDMI_ACR_48_0__SI                        0x1C3B
#define mmDIG0_HDMI_ACR_48_1__SI                        0x1C3C
#define mmDIG0_HDMI_ACR_PACKET_CONTROL__SI              0x1C0F
#define mmDIG0_HDMI_ACR_STATUS_0__SI                    0x1C3D
#define mmDIG0_HDMI_ACR_STATUS_1__SI                    0x1C3E
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL__SI            0x1C0E
#define mmDIG0_HDMI_CONTROL__SI                         0x1C0C
#define mmDIG0_HDMI_GC__SI                              0x1C16
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL__SI          0x1C13
#define mmDIG0_HDMI_INFOFRAME_CONTROL0__SI              0x1C11
#define mmDIG0_HDMI_INFOFRAME_CONTROL1__SI              0x1C12
#define mmDIG0_HDMI_STATUS__SI                          0x1C0D
#define mmDIG0_HDMI_VBI_PACKET_CONTROL__SI              0x1C10
#define mmDIG0_LVDS_DATA_CNTL__SI                       0x1C8C
#define mmDIG0_TMDS_CNTL__SI                            0x1C7C
#define mmDIG0_TMDS_CONTROL0_FEEDBACK__SI               0x1C7E
#define mmDIG0_TMDS_CONTROL_CHAR__SI                    0x1C7D
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL__SI                 0x1C86
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL__SI                 0x1C87
#define mmDIG0_TMDS_CTL_BITS__SI                        0x1C83
#define mmDIG0_TMDS_DCBALANCER_CONTROL__SI              0x1C84
#define mmDIG0_TMDS_DEBUG__SI                           0x1C82
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL__SI              0x1C7F
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1__SI           0x1C80
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3__SI           0x1C81
#define mmDIG1_AFMT_60958_0__SI                         0x1F41
#define mmDIG1_AFMT_60958_1__SI                         0x1F42
#define mmDIG1_AFMT_60958_2__SI                         0x1F48
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL__SI               0x1F43
#define mmDIG1_AFMT_AUDIO_CRC_RESULT__SI                0x1F49
#define mmDIG1_AFMT_AUDIO_INFO0__SI                     0x1F3F
#define mmDIG1_AFMT_AUDIO_INFO1__SI                     0x1F40
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2__SI           0x1F17
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL__SI            0x1F4B
#define mmDIG1_AFMT_AVI_INFO0__SI                       0x1F21
#define mmDIG1_AFMT_AVI_INFO1__SI                       0x1F22
#define mmDIG1_AFMT_AVI_INFO2__SI                       0x1F23
#define mmDIG1_AFMT_AVI_INFO3__SI                       0x1F24
#define mmDIG1_AFMT_INFOFRAME_CONTROL0__SI              0x1F4D
#define mmDIG1_AFMT_ISRC1_0__SI                         0x1F18
#define mmDIG1_AFMT_ISRC1_1__SI                         0x1F19
#define mmDIG1_AFMT_ISRC1_2__SI                         0x1F1A
#define mmDIG1_AFMT_ISRC1_3__SI                         0x1F1B
#define mmDIG1_AFMT_ISRC1_4__SI                         0x1F1C
#define mmDIG1_AFMT_ISRC2_0__SI                         0x1F1D
#define mmDIG1_AFMT_ISRC2_1__SI                         0x1F1E
#define mmDIG1_AFMT_ISRC2_2__SI                         0x1F1F
#define mmDIG1_AFMT_ISRC2_3__SI                         0x1F20
#define mmDIG1_AFMT_MPEG_INFO0__SI                      0x1F25
#define mmDIG1_AFMT_MPEG_INFO1__SI                      0x1F26
#define mmDIG1_AFMT_RAMP_CONTROL0__SI                   0x1F44
#define mmDIG1_AFMT_RAMP_CONTROL1__SI                   0x1F45
#define mmDIG1_AFMT_RAMP_CONTROL2__SI                   0x1F46
#define mmDIG1_AFMT_RAMP_CONTROL3__SI                   0x1F47
#define mmDIG1_AFMT_STATUS__SI                          0x1F4A
#define mmDIG1_AFMT_VBI_PACKET_CONTROL__SI              0x1F4C
#define mmDIG1_DIG_CLOCK_PATTERN__SI                    0x1F03
#define mmDIG1_DIG_OUTPUT_CRC_CNTL__SI                  0x1F01
#define mmDIG1_DIG_OUTPUT_CRC_RESULT__SI                0x1F02
#define mmDIG1_DIG_RANDOM_PATTERN_SEED__SI              0x1F05
#define mmDIG1_DIG_TEST_PATTERN__SI                     0x1F04
#define mmDIG1_HDMI_ACR_32_0__SI                        0x1F37
#define mmDIG1_HDMI_ACR_32_1__SI                        0x1F38
#define mmDIG1_HDMI_ACR_44_0__SI                        0x1F39
#define mmDIG1_HDMI_ACR_44_1__SI                        0x1F3A
#define mmDIG1_HDMI_ACR_48_0__SI                        0x1F3B
#define mmDIG1_HDMI_ACR_48_1__SI                        0x1F3C
#define mmDIG1_HDMI_ACR_PACKET_CONTROL__SI              0x1F0F
#define mmDIG1_HDMI_ACR_STATUS_0__SI                    0x1F3D
#define mmDIG1_HDMI_ACR_STATUS_1__SI                    0x1F3E
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL__SI            0x1F0E
#define mmDIG1_HDMI_CONTROL__SI                         0x1F0C
#define mmDIG1_HDMI_GC__SI                              0x1F16
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL__SI          0x1F13
#define mmDIG1_HDMI_INFOFRAME_CONTROL0__SI              0x1F11
#define mmDIG1_HDMI_INFOFRAME_CONTROL1__SI              0x1F12
#define mmDIG1_HDMI_STATUS__SI                          0x1F0D
#define mmDIG1_HDMI_VBI_PACKET_CONTROL__SI              0x1F10
#define mmDIG1_LVDS_DATA_CNTL__SI                       0x1F8C
#define mmDIG1_TMDS_CNTL__SI                            0x1F7C
#define mmDIG1_TMDS_CONTROL0_FEEDBACK__SI               0x1F7E
#define mmDIG1_TMDS_CONTROL_CHAR__SI                    0x1F7D
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL__SI                 0x1F86
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL__SI                 0x1F87
#define mmDIG1_TMDS_CTL_BITS__SI                        0x1F83
#define mmDIG1_TMDS_DCBALANCER_CONTROL__SI              0x1F84
#define mmDIG1_TMDS_DEBUG__SI                           0x1F82
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL__SI              0x1F7F
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1__SI           0x1F80
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3__SI           0x1F81
#define mmDIG2_AFMT_60958_0__SI                         0x4241
#define mmDIG2_AFMT_60958_1__SI                         0x4242
#define mmDIG2_AFMT_60958_2__SI                         0x4248
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL__SI               0x4243
#define mmDIG2_AFMT_AUDIO_CRC_RESULT__SI                0x4249
#define mmDIG2_AFMT_AUDIO_INFO0__SI                     0x423F
#define mmDIG2_AFMT_AUDIO_INFO1__SI                     0x4240
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2__SI           0x4217
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL__SI            0x424B
#define mmDIG2_AFMT_AVI_INFO0__SI                       0x4221
#define mmDIG2_AFMT_AVI_INFO1__SI                       0x4222
#define mmDIG2_AFMT_AVI_INFO2__SI                       0x4223
#define mmDIG2_AFMT_AVI_INFO3__SI                       0x4224
#define mmDIG2_AFMT_INFOFRAME_CONTROL0__SI              0x424D
#define mmDIG2_AFMT_ISRC1_0__SI                         0x4218
#define mmDIG2_AFMT_ISRC1_1__SI                         0x4219
#define mmDIG2_AFMT_ISRC1_2__SI                         0x421A
#define mmDIG2_AFMT_ISRC1_3__SI                         0x421B
#define mmDIG2_AFMT_ISRC1_4__SI                         0x421C
#define mmDIG2_AFMT_ISRC2_0__SI                         0x421D
#define mmDIG2_AFMT_ISRC2_1__SI                         0x421E
#define mmDIG2_AFMT_ISRC2_2__SI                         0x421F
#define mmDIG2_AFMT_ISRC2_3__SI                         0x4220
#define mmDIG2_AFMT_MPEG_INFO0__SI                      0x4225
#define mmDIG2_AFMT_MPEG_INFO1__SI                      0x4226
#define mmDIG2_AFMT_RAMP_CONTROL0__SI                   0x4244
#define mmDIG2_AFMT_RAMP_CONTROL1__SI                   0x4245
#define mmDIG2_AFMT_RAMP_CONTROL2__SI                   0x4246
#define mmDIG2_AFMT_RAMP_CONTROL3__SI                   0x4247
#define mmDIG2_AFMT_STATUS__SI                          0x424A
#define mmDIG2_AFMT_VBI_PACKET_CONTROL__SI              0x424C
#define mmDIG2_DIG_CLOCK_PATTERN__SI                    0x4203
#define mmDIG2_DIG_OUTPUT_CRC_CNTL__SI                  0x4201
#define mmDIG2_DIG_OUTPUT_CRC_RESULT__SI                0x4202
#define mmDIG2_DIG_RANDOM_PATTERN_SEED__SI              0x4205
#define mmDIG2_DIG_TEST_PATTERN__SI                     0x4204
#define mmDIG2_HDMI_ACR_32_0__SI                        0x4237
#define mmDIG2_HDMI_ACR_32_1__SI                        0x4238
#define mmDIG2_HDMI_ACR_44_0__SI                        0x4239
#define mmDIG2_HDMI_ACR_44_1__SI                        0x423A
#define mmDIG2_HDMI_ACR_48_0__SI                        0x423B
#define mmDIG2_HDMI_ACR_48_1__SI                        0x423C
#define mmDIG2_HDMI_ACR_PACKET_CONTROL__SI              0x420F
#define mmDIG2_HDMI_ACR_STATUS_0__SI                    0x423D
#define mmDIG2_HDMI_ACR_STATUS_1__SI                    0x423E
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL__SI            0x420E
#define mmDIG2_HDMI_CONTROL__SI                         0x420C
#define mmDIG2_HDMI_GC__SI                              0x4216
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL__SI          0x4213
#define mmDIG2_HDMI_INFOFRAME_CONTROL0__SI              0x4211
#define mmDIG2_HDMI_INFOFRAME_CONTROL1__SI              0x4212
#define mmDIG2_HDMI_STATUS__SI                          0x420D
#define mmDIG2_HDMI_VBI_PACKET_CONTROL__SI              0x4210
#define mmDIG2_LVDS_DATA_CNTL__SI                       0x428C
#define mmDIG2_TMDS_CNTL__SI                            0x427C
#define mmDIG2_TMDS_CONTROL0_FEEDBACK__SI               0x427E
#define mmDIG2_TMDS_CONTROL_CHAR__SI                    0x427D
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL__SI                 0x4286
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL__SI                 0x4287
#define mmDIG2_TMDS_CTL_BITS__SI                        0x4283
#define mmDIG2_TMDS_DCBALANCER_CONTROL__SI              0x4284
#define mmDIG2_TMDS_DEBUG__SI                           0x4282
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL__SI              0x427F
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1__SI           0x4280
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3__SI           0x4281
#define mmDIG3_AFMT_60958_0__SI                         0x4541
#define mmDIG3_AFMT_60958_1__SI                         0x4542
#define mmDIG3_AFMT_60958_2__SI                         0x4548
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL__SI               0x4543
#define mmDIG3_AFMT_AUDIO_CRC_RESULT__SI                0x4549
#define mmDIG3_AFMT_AUDIO_INFO0__SI                     0x453F
#define mmDIG3_AFMT_AUDIO_INFO1__SI                     0x4540
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2__SI           0x4517
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL__SI            0x454B
#define mmDIG3_AFMT_AVI_INFO0__SI                       0x4521
#define mmDIG3_AFMT_AVI_INFO1__SI                       0x4522
#define mmDIG3_AFMT_AVI_INFO2__SI                       0x4523
#define mmDIG3_AFMT_AVI_INFO3__SI                       0x4524
#define mmDIG3_AFMT_INFOFRAME_CONTROL0__SI              0x454D
#define mmDIG3_AFMT_ISRC1_0__SI                         0x4518
#define mmDIG3_AFMT_ISRC1_1__SI                         0x4519
#define mmDIG3_AFMT_ISRC1_2__SI                         0x451A
#define mmDIG3_AFMT_ISRC1_3__SI                         0x451B
#define mmDIG3_AFMT_ISRC1_4__SI                         0x451C
#define mmDIG3_AFMT_ISRC2_0__SI                         0x451D
#define mmDIG3_AFMT_ISRC2_1__SI                         0x451E
#define mmDIG3_AFMT_ISRC2_2__SI                         0x451F
#define mmDIG3_AFMT_ISRC2_3__SI                         0x4520
#define mmDIG3_AFMT_MPEG_INFO0__SI                      0x4525
#define mmDIG3_AFMT_MPEG_INFO1__SI                      0x4526
#define mmDIG3_AFMT_RAMP_CONTROL0__SI                   0x4544
#define mmDIG3_AFMT_RAMP_CONTROL1__SI                   0x4545
#define mmDIG3_AFMT_RAMP_CONTROL2__SI                   0x4546
#define mmDIG3_AFMT_RAMP_CONTROL3__SI                   0x4547
#define mmDIG3_AFMT_STATUS__SI                          0x454A
#define mmDIG3_AFMT_VBI_PACKET_CONTROL__SI              0x454C
#define mmDIG3_DIG_CLOCK_PATTERN__SI                    0x4503
#define mmDIG3_DIG_OUTPUT_CRC_CNTL__SI                  0x4501
#define mmDIG3_DIG_OUTPUT_CRC_RESULT__SI                0x4502
#define mmDIG3_DIG_RANDOM_PATTERN_SEED__SI              0x4505
#define mmDIG3_DIG_TEST_PATTERN__SI                     0x4504
#define mmDIG3_HDMI_ACR_32_0__SI                        0x4537
#define mmDIG3_HDMI_ACR_32_1__SI                        0x4538
#define mmDIG3_HDMI_ACR_44_0__SI                        0x4539
#define mmDIG3_HDMI_ACR_44_1__SI                        0x453A
#define mmDIG3_HDMI_ACR_48_0__SI                        0x453B
#define mmDIG3_HDMI_ACR_48_1__SI                        0x453C
#define mmDIG3_HDMI_ACR_PACKET_CONTROL__SI              0x450F
#define mmDIG3_HDMI_ACR_STATUS_0__SI                    0x453D
#define mmDIG3_HDMI_ACR_STATUS_1__SI                    0x453E
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL__SI            0x450E
#define mmDIG3_HDMI_CONTROL__SI                         0x450C
#define mmDIG3_HDMI_GC__SI                              0x4516
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL__SI          0x4513
#define mmDIG3_HDMI_INFOFRAME_CONTROL0__SI              0x4511
#define mmDIG3_HDMI_INFOFRAME_CONTROL1__SI              0x4512
#define mmDIG3_HDMI_STATUS__SI                          0x450D
#define mmDIG3_HDMI_VBI_PACKET_CONTROL__SI              0x4510
#define mmDIG3_LVDS_DATA_CNTL__SI                       0x458C
#define mmDIG3_TMDS_CNTL__SI                            0x457C
#define mmDIG3_TMDS_CONTROL0_FEEDBACK__SI               0x457E
#define mmDIG3_TMDS_CONTROL_CHAR__SI                    0x457D
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL__SI                 0x4586
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL__SI                 0x4587
#define mmDIG3_TMDS_CTL_BITS__SI                        0x4583
#define mmDIG3_TMDS_DCBALANCER_CONTROL__SI              0x4584
#define mmDIG3_TMDS_DEBUG__SI                           0x4582
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL__SI              0x457F
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1__SI           0x4580
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3__SI           0x4581
#define mmDIG4_AFMT_60958_0__SI                         0x4841
#define mmDIG4_AFMT_60958_1__SI                         0x4842
#define mmDIG4_AFMT_60958_2__SI                         0x4848
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL__SI               0x4843
#define mmDIG4_AFMT_AUDIO_CRC_RESULT__SI                0x4849
#define mmDIG4_AFMT_AUDIO_INFO0__SI                     0x483F
#define mmDIG4_AFMT_AUDIO_INFO1__SI                     0x4840
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2__SI           0x4817
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL__SI            0x484B
#define mmDIG4_AFMT_AVI_INFO0__SI                       0x4821
#define mmDIG4_AFMT_AVI_INFO1__SI                       0x4822
#define mmDIG4_AFMT_AVI_INFO2__SI                       0x4823
#define mmDIG4_AFMT_AVI_INFO3__SI                       0x4824
#define mmDIG4_AFMT_INFOFRAME_CONTROL0__SI              0x484D
#define mmDIG4_AFMT_ISRC1_0__SI                         0x4818
#define mmDIG4_AFMT_ISRC1_1__SI                         0x4819
#define mmDIG4_AFMT_ISRC1_2__SI                         0x481A
#define mmDIG4_AFMT_ISRC1_3__SI                         0x481B
#define mmDIG4_AFMT_ISRC1_4__SI                         0x481C
#define mmDIG4_AFMT_ISRC2_0__SI                         0x481D
#define mmDIG4_AFMT_ISRC2_1__SI                         0x481E
#define mmDIG4_AFMT_ISRC2_2__SI                         0x481F
#define mmDIG4_AFMT_ISRC2_3__SI                         0x4820
#define mmDIG4_AFMT_MPEG_INFO0__SI                      0x4825
#define mmDIG4_AFMT_MPEG_INFO1__SI                      0x4826
#define mmDIG4_AFMT_RAMP_CONTROL0__SI                   0x4844
#define mmDIG4_AFMT_RAMP_CONTROL1__SI                   0x4845
#define mmDIG4_AFMT_RAMP_CONTROL2__SI                   0x4846
#define mmDIG4_AFMT_RAMP_CONTROL3__SI                   0x4847
#define mmDIG4_AFMT_STATUS__SI                          0x484A
#define mmDIG4_AFMT_VBI_PACKET_CONTROL__SI              0x484C
#define mmDIG4_DIG_CLOCK_PATTERN__SI                    0x4803
#define mmDIG4_DIG_OUTPUT_CRC_CNTL__SI                  0x4801
#define mmDIG4_DIG_OUTPUT_CRC_RESULT__SI                0x4802
#define mmDIG4_DIG_RANDOM_PATTERN_SEED__SI              0x4805
#define mmDIG4_DIG_TEST_PATTERN__SI                     0x4804
#define mmDIG4_HDMI_ACR_32_0__SI                        0x4837
#define mmDIG4_HDMI_ACR_32_1__SI                        0x4838
#define mmDIG4_HDMI_ACR_44_0__SI                        0x4839
#define mmDIG4_HDMI_ACR_44_1__SI                        0x483A
#define mmDIG4_HDMI_ACR_48_0__SI                        0x483B
#define mmDIG4_HDMI_ACR_48_1__SI                        0x483C
#define mmDIG4_HDMI_ACR_PACKET_CONTROL__SI              0x480F
#define mmDIG4_HDMI_ACR_STATUS_0__SI                    0x483D
#define mmDIG4_HDMI_ACR_STATUS_1__SI                    0x483E
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL__SI            0x480E
#define mmDIG4_HDMI_CONTROL__SI                         0x480C
#define mmDIG4_HDMI_GC__SI                              0x4816
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL__SI          0x4813
#define mmDIG4_HDMI_INFOFRAME_CONTROL0__SI              0x4811
#define mmDIG4_HDMI_INFOFRAME_CONTROL1__SI              0x4812
#define mmDIG4_HDMI_STATUS__SI                          0x480D
#define mmDIG4_HDMI_VBI_PACKET_CONTROL__SI              0x4810
#define mmDIG4_LVDS_DATA_CNTL__SI                       0x488C
#define mmDIG4_TMDS_CNTL__SI                            0x487C
#define mmDIG4_TMDS_CONTROL0_FEEDBACK__SI               0x487E
#define mmDIG4_TMDS_CONTROL_CHAR__SI                    0x487D
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL__SI                 0x4886
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL__SI                 0x4887
#define mmDIG4_TMDS_CTL_BITS__SI                        0x4883
#define mmDIG4_TMDS_DCBALANCER_CONTROL__SI              0x4884
#define mmDIG4_TMDS_DEBUG__SI                           0x4882
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL__SI              0x487F
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1__SI           0x4880
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3__SI           0x4881
#define mmDIG5_AFMT_60958_0__SI                         0x4B41
#define mmDIG5_AFMT_60958_1__SI                         0x4B42
#define mmDIG5_AFMT_60958_2__SI                         0x4B48
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL__SI               0x4B43
#define mmDIG5_AFMT_AUDIO_CRC_RESULT__SI                0x4B49
#define mmDIG5_AFMT_AUDIO_INFO0__SI                     0x4B3F
#define mmDIG5_AFMT_AUDIO_INFO1__SI                     0x4B40
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2__SI           0x4B17
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL__SI            0x4B4B
#define mmDIG5_AFMT_AVI_INFO0__SI                       0x4B21
#define mmDIG5_AFMT_AVI_INFO1__SI                       0x4B22
#define mmDIG5_AFMT_AVI_INFO2__SI                       0x4B23
#define mmDIG5_AFMT_AVI_INFO3__SI                       0x4B24
#define mmDIG5_AFMT_INFOFRAME_CONTROL0__SI              0x4B4D
#define mmDIG5_AFMT_ISRC1_0__SI                         0x4B18
#define mmDIG5_AFMT_ISRC1_1__SI                         0x4B19
#define mmDIG5_AFMT_ISRC1_2__SI                         0x4B1A
#define mmDIG5_AFMT_ISRC1_3__SI                         0x4B1B
#define mmDIG5_AFMT_ISRC1_4__SI                         0x4B1C
#define mmDIG5_AFMT_ISRC2_0__SI                         0x4B1D
#define mmDIG5_AFMT_ISRC2_1__SI                         0x4B1E
#define mmDIG5_AFMT_ISRC2_2__SI                         0x4B1F
#define mmDIG5_AFMT_ISRC2_3__SI                         0x4B20
#define mmDIG5_AFMT_MPEG_INFO0__SI                      0x4B25
#define mmDIG5_AFMT_MPEG_INFO1__SI                      0x4B26
#define mmDIG5_AFMT_RAMP_CONTROL0__SI                   0x4B44
#define mmDIG5_AFMT_RAMP_CONTROL1__SI                   0x4B45
#define mmDIG5_AFMT_RAMP_CONTROL2__SI                   0x4B46
#define mmDIG5_AFMT_RAMP_CONTROL3__SI                   0x4B47
#define mmDIG5_AFMT_STATUS__SI                          0x4B4A
#define mmDIG5_AFMT_VBI_PACKET_CONTROL__SI              0x4B4C
#define mmDIG5_DIG_CLOCK_PATTERN__SI                    0x4B03
#define mmDIG5_DIG_OUTPUT_CRC_CNTL__SI                  0x4B01
#define mmDIG5_DIG_OUTPUT_CRC_RESULT__SI                0x4B02
#define mmDIG5_DIG_RANDOM_PATTERN_SEED__SI              0x4B05
#define mmDIG5_DIG_TEST_PATTERN__SI                     0x4B04
#define mmDIG5_HDMI_ACR_32_0__SI                        0x4B37
#define mmDIG5_HDMI_ACR_32_1__SI                        0x4B38
#define mmDIG5_HDMI_ACR_44_0__SI                        0x4B39
#define mmDIG5_HDMI_ACR_44_1__SI                        0x4B3A
#define mmDIG5_HDMI_ACR_48_0__SI                        0x4B3B
#define mmDIG5_HDMI_ACR_48_1__SI                        0x4B3C
#define mmDIG5_HDMI_ACR_PACKET_CONTROL__SI              0x4B0F
#define mmDIG5_HDMI_ACR_STATUS_0__SI                    0x4B3D
#define mmDIG5_HDMI_ACR_STATUS_1__SI                    0x4B3E
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL__SI            0x4B0E
#define mmDIG5_HDMI_CONTROL__SI                         0x4B0C
#define mmDIG5_HDMI_GC__SI                              0x4B16
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL__SI          0x4B13
#define mmDIG5_HDMI_INFOFRAME_CONTROL0__SI              0x4B11
#define mmDIG5_HDMI_INFOFRAME_CONTROL1__SI              0x4B12
#define mmDIG5_HDMI_STATUS__SI                          0x4B0D
#define mmDIG5_HDMI_VBI_PACKET_CONTROL__SI              0x4B10
#define mmDIG5_LVDS_DATA_CNTL__SI                       0x4B8C
#define mmDIG5_TMDS_CNTL__SI                            0x4B7C
#define mmDIG5_TMDS_CONTROL0_FEEDBACK__SI               0x4B7E
#define mmDIG5_TMDS_CONTROL_CHAR__SI                    0x4B7D
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL__SI                 0x4B86
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL__SI                 0x4B87
#define mmDIG5_TMDS_CTL_BITS__SI                        0x4B83
#define mmDIG5_TMDS_DCBALANCER_CONTROL__SI              0x4B84
#define mmDIG5_TMDS_DEBUG__SI                           0x4B82
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL__SI              0x4B7F
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1__SI           0x4B80
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3__SI           0x4B81
#define mmDIG_CLOCK_PATTERN__SI                         0x1C03
#define mmDIG_OUTPUT_CRC_CNTL__SI                       0x1C01
#define mmDIG_OUTPUT_CRC_RESULT__SI                     0x1C02
#define mmDIG_RANDOM_PATTERN_SEED__SI                   0x1C05
#define mmDIG_TEST_PATTERN__SI                          0x1C04
#define mmDISPCLK_CGTT_BLK_CTRL_REG__SI                 0x0128
#define mmDISP_INTERRUPT_STATUS_CONTINUE2__SI           0x183F
#define mmDISP_INTERRUPT_STATUS_CONTINUE__SI            0x183E
#define mmDISP_INTERRUPT_STATUS__SI                     0x183D
#define mmDISP_TIMER_CONTROL__SI                        0x1842
#define mmDLL_CNTL__SI__CI                              0x0AE9
#define mmDMCU_CTRL__SI__VI                             0x1600
#define mmDMCU_ERAM_RD_CTRL__SI__VI                     0x160B
#define mmDMCU_ERAM_RD_DATA__SI__VI                     0x160C
#define mmDMCU_ERAM_WR_CTRL__SI__VI                     0x1609
#define mmDMCU_ERAM_WR_DATA__SI__VI                     0x160A
#define mmDMCU_EVENT_TRIGGER__SI__VI                    0x1611
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI__VI        0x161A
#define mmDMCU_FW_CS_HI__SI__VI                         0x1606
#define mmDMCU_FW_CS_LO__SI__VI                         0x1607
#define mmDMCU_FW_END_ADDR__SI__VI                      0x1604
#define mmDMCU_FW_ISR_START_ADDR__SI__VI                0x1605
#define mmDMCU_FW_START_ADDR__SI__VI                    0x1603
#define mmDMCU_INTERRUPT_STATUS__SI__VI                 0x1614
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK__SI__VI        0x1615
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK__SI__VI          0x1616
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI__VI     0x1617
#define mmDMCU_INT_CNT__SI__VI                          0x1619
#define mmDMCU_IRAM_RD_CTRL__SI__VI                     0x160F
#define mmDMCU_IRAM_RD_DATA__SI__VI                     0x1610
#define mmDMCU_IRAM_WR_CTRL__SI__VI                     0x160D
#define mmDMCU_IRAM_WR_DATA__SI__VI                     0x160E
#define mmDMCU_PC_START_ADDR__SI__VI                    0x1602
#define mmDMCU_RAM_ACCESS_CTRL__SI__VI                  0x1608
#define mmDMCU_STATUS__SI__VI                           0x1601
#define mmDMCU_TEST_DEBUG_DATA__SI__VI                  0x1627
#define mmDMCU_TEST_DEBUG_INDEX__SI__VI                 0x1626
#define mmDMCU_UC_INTERNAL_INT_STATUS__SI__VI           0x1612
#define mmDMIF_ARBITRATION_CONTROL__SI__VI              0x02F9
#define mmDMIF_CONTROL__SI__VI                          0x02F6
#define mmDMIF_HW_DEBUG__SI__VI                         0x02F8
#define mmDMIF_STATUS__SI__VI                           0x02F7
#define mmDMIF_TEST_DEBUG_DATA__SI                      0x0313
#define mmDMIF_TEST_DEBUG_INDEX__SI                     0x0312
#define mmDOUT_POWER_MANAGEMENT_CNTL__SI                0x1841
#define mmDOUT_SCRATCH0__SI                             0x1844
#define mmDOUT_SCRATCH1__SI                             0x1845
#define mmDOUT_SCRATCH2__SI                             0x1846
#define mmDOUT_SCRATCH3__SI                             0x1847
#define mmDOUT_SCRATCH4__SI                             0x1848
#define mmDOUT_SCRATCH5__SI                             0x1849
#define mmDOUT_SCRATCH6__SI                             0x184A
#define mmDOUT_SCRATCH7__SI                             0x184B
#define mmDOUT_TEST_DEBUG_DATA__SI                      0x184E
#define mmDOUT_TEST_DEBUG_INDEX__SI                     0x184D
#define mmDP0_DP_CONFIG__SI                             0x1CC2
#define mmDP0_DP_DPHY_8B10B_CNTL__SI                    0x1CD3
#define mmDP0_DP_DPHY_CNTL__SI                          0x1CD0
#define mmDP0_DP_DPHY_CRC_CNTL__SI                      0x1CD7
#define mmDP0_DP_DPHY_CRC_EN__SI                        0x1CD6
#define mmDP0_DP_DPHY_CRC_RESULT__SI                    0x1CD8
#define mmDP0_DP_DPHY_FAST_TRAINING__SI                 0x1CCE
#define mmDP0_DP_DPHY_PRBS_CNTL__SI                     0x1CD4
#define mmDP0_DP_DPHY_SYM__SI                           0x1CD2
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL__SI          0x1CD1
#define mmDP0_DP_LINK_CNTL__SI                          0x1CC0
#define mmDP0_DP_PIXEL_FORMAT__SI                       0x1CC1
#define mmDP0_DP_SEC_AUD_M_READBACK__SI                 0x1CA8
#define mmDP0_DP_SEC_AUD_M__SI                          0x1CA7
#define mmDP0_DP_SEC_AUD_N_READBACK__SI                 0x1CA6
#define mmDP0_DP_SEC_AUD_N__SI                          0x1CA5
#define mmDP0_DP_SEC_CNTL__SI                           0x1CA0
#define mmDP0_DP_SEC_FRAMING1__SI                       0x1CA1
#define mmDP0_DP_SEC_FRAMING2__SI                       0x1CA2
#define mmDP0_DP_SEC_FRAMING3__SI                       0x1CA3
#define mmDP0_DP_SEC_FRAMING4__SI                       0x1CA4
#define mmDP0_DP_SEC_PACKET_CNTL__SI                    0x1CAA
#define mmDP0_DP_SEC_TIMESTAMP__SI                      0x1CA9
#define mmDP0_DP_STEER_FIFO__SI                         0x1CC4
#define mmDP0_DP_TEST_DEBUG_DATA__SI                    0x1CFD
#define mmDP0_DP_TEST_DEBUG_INDEX__SI                   0x1CFC
#define mmDP0_DP_VID_INTERRUPT_CNTL__SI                 0x1CCF
#define mmDP0_DP_VID_MSA_VBID__SI                       0x1CCD
#define mmDP0_DP_VID_M__SI                              0x1CCB
#define mmDP0_DP_VID_N__SI                              0x1CCA
#define mmDP0_DP_VID_STREAM_CNTL__SI                    0x1CC3
#define mmDP0_DP_VID_TIMING__SI                         0x1CC9
#define mmDP1_DP_CONFIG__SI                             0x1FC2
#define mmDP1_DP_DPHY_8B10B_CNTL__SI                    0x1FD3
#define mmDP1_DP_DPHY_CNTL__SI                          0x1FD0
#define mmDP1_DP_DPHY_CRC_CNTL__SI                      0x1FD7
#define mmDP1_DP_DPHY_CRC_EN__SI                        0x1FD6
#define mmDP1_DP_DPHY_CRC_RESULT__SI                    0x1FD8
#define mmDP1_DP_DPHY_FAST_TRAINING__SI                 0x1FCE
#define mmDP1_DP_DPHY_PRBS_CNTL__SI                     0x1FD4
#define mmDP1_DP_DPHY_SYM__SI                           0x1FD2
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL__SI          0x1FD1
#define mmDP1_DP_LINK_CNTL__SI                          0x1FC0
#define mmDP1_DP_PIXEL_FORMAT__SI                       0x1FC1
#define mmDP1_DP_SEC_AUD_M_READBACK__SI                 0x1FA8
#define mmDP1_DP_SEC_AUD_M__SI                          0x1FA7
#define mmDP1_DP_SEC_AUD_N_READBACK__SI                 0x1FA6
#define mmDP1_DP_SEC_AUD_N__SI                          0x1FA5
#define mmDP1_DP_SEC_CNTL__SI                           0x1FA0
#define mmDP1_DP_SEC_FRAMING1__SI                       0x1FA1
#define mmDP1_DP_SEC_FRAMING2__SI                       0x1FA2
#define mmDP1_DP_SEC_FRAMING3__SI                       0x1FA3
#define mmDP1_DP_SEC_FRAMING4__SI                       0x1FA4
#define mmDP1_DP_SEC_PACKET_CNTL__SI                    0x1FAA
#define mmDP1_DP_SEC_TIMESTAMP__SI                      0x1FA9
#define mmDP1_DP_STEER_FIFO__SI                         0x1FC4
#define mmDP1_DP_TEST_DEBUG_DATA__SI                    0x1FFD
#define mmDP1_DP_TEST_DEBUG_INDEX__SI                   0x1FFC
#define mmDP1_DP_VID_INTERRUPT_CNTL__SI                 0x1FCF
#define mmDP1_DP_VID_MSA_VBID__SI                       0x1FCD
#define mmDP1_DP_VID_M__SI                              0x1FCB
#define mmDP1_DP_VID_N__SI                              0x1FCA
#define mmDP1_DP_VID_STREAM_CNTL__SI                    0x1FC3
#define mmDP1_DP_VID_TIMING__SI                         0x1FC9
#define mmDP2_DP_CONFIG__SI                             0x42C2
#define mmDP2_DP_DPHY_8B10B_CNTL__SI                    0x42D3
#define mmDP2_DP_DPHY_CNTL__SI                          0x42D0
#define mmDP2_DP_DPHY_CRC_CNTL__SI                      0x42D7
#define mmDP2_DP_DPHY_CRC_EN__SI                        0x42D6
#define mmDP2_DP_DPHY_CRC_RESULT__SI                    0x42D8
#define mmDP2_DP_DPHY_FAST_TRAINING__SI                 0x42CE
#define mmDP2_DP_DPHY_PRBS_CNTL__SI                     0x42D4
#define mmDP2_DP_DPHY_SYM__SI                           0x42D2
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL__SI          0x42D1
#define mmDP2_DP_LINK_CNTL__SI                          0x42C0
#define mmDP2_DP_PIXEL_FORMAT__SI                       0x42C1
#define mmDP2_DP_SEC_AUD_M_READBACK__SI                 0x42A8
#define mmDP2_DP_SEC_AUD_M__SI                          0x42A7
#define mmDP2_DP_SEC_AUD_N_READBACK__SI                 0x42A6
#define mmDP2_DP_SEC_AUD_N__SI                          0x42A5
#define mmDP2_DP_SEC_CNTL__SI                           0x42A0
#define mmDP2_DP_SEC_FRAMING1__SI                       0x42A1
#define mmDP2_DP_SEC_FRAMING2__SI                       0x42A2
#define mmDP2_DP_SEC_FRAMING3__SI                       0x42A3
#define mmDP2_DP_SEC_FRAMING4__SI                       0x42A4
#define mmDP2_DP_SEC_PACKET_CNTL__SI                    0x42AA
#define mmDP2_DP_SEC_TIMESTAMP__SI                      0x42A9
#define mmDP2_DP_STEER_FIFO__SI                         0x42C4
#define mmDP2_DP_TEST_DEBUG_DATA__SI                    0x42FD
#define mmDP2_DP_TEST_DEBUG_INDEX__SI                   0x42FC
#define mmDP2_DP_VID_INTERRUPT_CNTL__SI                 0x42CF
#define mmDP2_DP_VID_MSA_VBID__SI                       0x42CD
#define mmDP2_DP_VID_M__SI                              0x42CB
#define mmDP2_DP_VID_N__SI                              0x42CA
#define mmDP2_DP_VID_STREAM_CNTL__SI                    0x42C3
#define mmDP2_DP_VID_TIMING__SI                         0x42C9
#define mmDP3_DP_CONFIG__SI                             0x45C2
#define mmDP3_DP_DPHY_8B10B_CNTL__SI                    0x45D3
#define mmDP3_DP_DPHY_CNTL__SI                          0x45D0
#define mmDP3_DP_DPHY_CRC_CNTL__SI                      0x45D7
#define mmDP3_DP_DPHY_CRC_EN__SI                        0x45D6
#define mmDP3_DP_DPHY_CRC_RESULT__SI                    0x45D8
#define mmDP3_DP_DPHY_FAST_TRAINING__SI                 0x45CE
#define mmDP3_DP_DPHY_PRBS_CNTL__SI                     0x45D4
#define mmDP3_DP_DPHY_SYM__SI                           0x45D2
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL__SI          0x45D1
#define mmDP3_DP_LINK_CNTL__SI                          0x45C0
#define mmDP3_DP_PIXEL_FORMAT__SI                       0x45C1
#define mmDP3_DP_SEC_AUD_M_READBACK__SI                 0x45A8
#define mmDP3_DP_SEC_AUD_M__SI                          0x45A7
#define mmDP3_DP_SEC_AUD_N_READBACK__SI                 0x45A6
#define mmDP3_DP_SEC_AUD_N__SI                          0x45A5
#define mmDP3_DP_SEC_CNTL__SI                           0x45A0
#define mmDP3_DP_SEC_FRAMING1__SI                       0x45A1
#define mmDP3_DP_SEC_FRAMING2__SI                       0x45A2
#define mmDP3_DP_SEC_FRAMING3__SI                       0x45A3
#define mmDP3_DP_SEC_FRAMING4__SI                       0x45A4
#define mmDP3_DP_SEC_PACKET_CNTL__SI                    0x45AA
#define mmDP3_DP_SEC_TIMESTAMP__SI                      0x45A9
#define mmDP3_DP_STEER_FIFO__SI                         0x45C4
#define mmDP3_DP_TEST_DEBUG_DATA__SI                    0x45FD
#define mmDP3_DP_TEST_DEBUG_INDEX__SI                   0x45FC
#define mmDP3_DP_VID_INTERRUPT_CNTL__SI                 0x45CF
#define mmDP3_DP_VID_MSA_VBID__SI                       0x45CD
#define mmDP3_DP_VID_M__SI                              0x45CB
#define mmDP3_DP_VID_N__SI                              0x45CA
#define mmDP3_DP_VID_STREAM_CNTL__SI                    0x45C3
#define mmDP3_DP_VID_TIMING__SI                         0x45C9
#define mmDP4_DP_CONFIG__SI                             0x48C2
#define mmDP4_DP_DPHY_8B10B_CNTL__SI                    0x48D3
#define mmDP4_DP_DPHY_CNTL__SI                          0x48D0
#define mmDP4_DP_DPHY_CRC_CNTL__SI                      0x48D7
#define mmDP4_DP_DPHY_CRC_EN__SI                        0x48D6
#define mmDP4_DP_DPHY_CRC_RESULT__SI                    0x48D8
#define mmDP4_DP_DPHY_FAST_TRAINING__SI                 0x48CE
#define mmDP4_DP_DPHY_PRBS_CNTL__SI                     0x48D4
#define mmDP4_DP_DPHY_SYM__SI                           0x48D2
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL__SI          0x48D1
#define mmDP4_DP_LINK_CNTL__SI                          0x48C0
#define mmDP4_DP_PIXEL_FORMAT__SI                       0x48C1
#define mmDP4_DP_SEC_AUD_M_READBACK__SI                 0x48A8
#define mmDP4_DP_SEC_AUD_M__SI                          0x48A7
#define mmDP4_DP_SEC_AUD_N_READBACK__SI                 0x48A6
#define mmDP4_DP_SEC_AUD_N__SI                          0x48A5
#define mmDP4_DP_SEC_CNTL__SI                           0x48A0
#define mmDP4_DP_SEC_FRAMING1__SI                       0x48A1
#define mmDP4_DP_SEC_FRAMING2__SI                       0x48A2
#define mmDP4_DP_SEC_FRAMING3__SI                       0x48A3
#define mmDP4_DP_SEC_FRAMING4__SI                       0x48A4
#define mmDP4_DP_SEC_PACKET_CNTL__SI                    0x48AA
#define mmDP4_DP_SEC_TIMESTAMP__SI                      0x48A9
#define mmDP4_DP_STEER_FIFO__SI                         0x48C4
#define mmDP4_DP_TEST_DEBUG_DATA__SI                    0x48FD
#define mmDP4_DP_TEST_DEBUG_INDEX__SI                   0x48FC
#define mmDP4_DP_VID_INTERRUPT_CNTL__SI                 0x48CF
#define mmDP4_DP_VID_MSA_VBID__SI                       0x48CD
#define mmDP4_DP_VID_M__SI                              0x48CB
#define mmDP4_DP_VID_N__SI                              0x48CA
#define mmDP4_DP_VID_STREAM_CNTL__SI                    0x48C3
#define mmDP4_DP_VID_TIMING__SI                         0x48C9
#define mmDP5_DP_CONFIG__SI                             0x4BC2
#define mmDP5_DP_DPHY_8B10B_CNTL__SI                    0x4BD3
#define mmDP5_DP_DPHY_CNTL__SI                          0x4BD0
#define mmDP5_DP_DPHY_CRC_CNTL__SI                      0x4BD7
#define mmDP5_DP_DPHY_CRC_EN__SI                        0x4BD6
#define mmDP5_DP_DPHY_CRC_RESULT__SI                    0x4BD8
#define mmDP5_DP_DPHY_FAST_TRAINING__SI                 0x4BCE
#define mmDP5_DP_DPHY_PRBS_CNTL__SI                     0x4BD4
#define mmDP5_DP_DPHY_SYM__SI                           0x4BD2
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL__SI          0x4BD1
#define mmDP5_DP_LINK_CNTL__SI                          0x4BC0
#define mmDP5_DP_PIXEL_FORMAT__SI                       0x4BC1
#define mmDP5_DP_SEC_AUD_M_READBACK__SI                 0x4BA8
#define mmDP5_DP_SEC_AUD_M__SI                          0x4BA7
#define mmDP5_DP_SEC_AUD_N_READBACK__SI                 0x4BA6
#define mmDP5_DP_SEC_AUD_N__SI                          0x4BA5
#define mmDP5_DP_SEC_CNTL__SI                           0x4BA0
#define mmDP5_DP_SEC_FRAMING1__SI                       0x4BA1
#define mmDP5_DP_SEC_FRAMING2__SI                       0x4BA2
#define mmDP5_DP_SEC_FRAMING3__SI                       0x4BA3
#define mmDP5_DP_SEC_FRAMING4__SI                       0x4BA4
#define mmDP5_DP_SEC_PACKET_CNTL__SI                    0x4BAA
#define mmDP5_DP_SEC_TIMESTAMP__SI                      0x4BA9
#define mmDP5_DP_STEER_FIFO__SI                         0x4BC4
#define mmDP5_DP_TEST_DEBUG_DATA__SI                    0x4BFD
#define mmDP5_DP_TEST_DEBUG_INDEX__SI                   0x4BFC
#define mmDP5_DP_VID_INTERRUPT_CNTL__SI                 0x4BCF
#define mmDP5_DP_VID_MSA_VBID__SI                       0x4BCD
#define mmDP5_DP_VID_M__SI                              0x4BCB
#define mmDP5_DP_VID_N__SI                              0x4BCA
#define mmDP5_DP_VID_STREAM_CNTL__SI                    0x4BC3
#define mmDP5_DP_VID_TIMING__SI                         0x4BC9
#define mmDP_AUX0_AUX_ARB_CONTROL__SI                   0x1882
#define mmDP_AUX0_AUX_CONTROL__SI                       0x1880
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0__SI              0x188A
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1__SI              0x188B
#define mmDP_AUX0_AUX_DPHY_RX_STATUS__SI                0x188D
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL__SI               0x1889
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL__SI           0x1888
#define mmDP_AUX0_AUX_DPHY_TX_STATUS__SI                0x188C
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL__SI             0x1883
#define mmDP_AUX0_AUX_LS_DATA__SI                       0x1887
#define mmDP_AUX0_AUX_LS_STATUS__SI                     0x1885
#define mmDP_AUX0_AUX_SW_CONTROL__SI                    0x1881
#define mmDP_AUX0_AUX_SW_DATA__SI                       0x1886
#define mmDP_AUX0_AUX_SW_STATUS__SI                     0x1884
#define mmDP_AUX1_AUX_ARB_CONTROL__SI                   0x1896
#define mmDP_AUX1_AUX_CONTROL__SI                       0x1894
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0__SI              0x189E
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1__SI              0x189F
#define mmDP_AUX1_AUX_DPHY_RX_STATUS__SI                0x18A1
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL__SI               0x189D
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL__SI           0x189C
#define mmDP_AUX1_AUX_DPHY_TX_STATUS__SI                0x18A0
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL__SI             0x1897
#define mmDP_AUX1_AUX_LS_DATA__SI                       0x189B
#define mmDP_AUX1_AUX_LS_STATUS__SI                     0x1899
#define mmDP_AUX1_AUX_SW_CONTROL__SI                    0x1895
#define mmDP_AUX1_AUX_SW_DATA__SI                       0x189A
#define mmDP_AUX1_AUX_SW_STATUS__SI                     0x1898
#define mmDP_AUX2_AUX_ARB_CONTROL__SI                   0x18AA
#define mmDP_AUX2_AUX_CONTROL__SI                       0x18A8
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0__SI              0x18B2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1__SI              0x18B3
#define mmDP_AUX2_AUX_DPHY_RX_STATUS__SI                0x18B5
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL__SI               0x18B1
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL__SI           0x18B0
#define mmDP_AUX2_AUX_DPHY_TX_STATUS__SI                0x18B4
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL__SI             0x18AB
#define mmDP_AUX2_AUX_LS_DATA__SI                       0x18AF
#define mmDP_AUX2_AUX_LS_STATUS__SI                     0x18AD
#define mmDP_AUX2_AUX_SW_CONTROL__SI                    0x18A9
#define mmDP_AUX2_AUX_SW_DATA__SI                       0x18AE
#define mmDP_AUX2_AUX_SW_STATUS__SI                     0x18AC
#define mmDP_AUX3_AUX_ARB_CONTROL__SI                   0x18C2
#define mmDP_AUX3_AUX_CONTROL__SI                       0x18C0
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0__SI              0x18CA
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1__SI              0x18CB
#define mmDP_AUX3_AUX_DPHY_RX_STATUS__SI                0x18CD
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL__SI               0x18C9
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL__SI           0x18C8
#define mmDP_AUX3_AUX_DPHY_TX_STATUS__SI                0x18CC
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL__SI             0x18C3
#define mmDP_AUX3_AUX_LS_DATA__SI                       0x18C7
#define mmDP_AUX3_AUX_LS_STATUS__SI                     0x18C5
#define mmDP_AUX3_AUX_SW_CONTROL__SI                    0x18C1
#define mmDP_AUX3_AUX_SW_DATA__SI                       0x18C6
#define mmDP_AUX3_AUX_SW_STATUS__SI                     0x18C4
#define mmDP_AUX4_AUX_ARB_CONTROL__SI                   0x18D6
#define mmDP_AUX4_AUX_CONTROL__SI                       0x18D4
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0__SI              0x18DE
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1__SI              0x18DF
#define mmDP_AUX4_AUX_DPHY_RX_STATUS__SI                0x18E1
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL__SI               0x18DD
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL__SI           0x18DC
#define mmDP_AUX4_AUX_DPHY_TX_STATUS__SI                0x18E0
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL__SI             0x18D7
#define mmDP_AUX4_AUX_LS_DATA__SI                       0x18DB
#define mmDP_AUX4_AUX_LS_STATUS__SI                     0x18D9
#define mmDP_AUX4_AUX_SW_CONTROL__SI                    0x18D5
#define mmDP_AUX4_AUX_SW_DATA__SI                       0x18DA
#define mmDP_AUX4_AUX_SW_STATUS__SI                     0x18D8
#define mmDP_AUX5_AUX_ARB_CONTROL__SI                   0x18EA
#define mmDP_AUX5_AUX_CONTROL__SI                       0x18E8
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0__SI              0x18F2
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1__SI              0x18F3
#define mmDP_AUX5_AUX_DPHY_RX_STATUS__SI                0x18F5
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL__SI               0x18F1
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL__SI           0x18F0
#define mmDP_AUX5_AUX_DPHY_TX_STATUS__SI                0x18F4
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL__SI             0x18EB
#define mmDP_AUX5_AUX_LS_DATA__SI                       0x18EF
#define mmDP_AUX5_AUX_LS_STATUS__SI                     0x18ED
#define mmDP_AUX5_AUX_SW_CONTROL__SI                    0x18E9
#define mmDP_AUX5_AUX_SW_DATA__SI                       0x18EE
#define mmDP_AUX5_AUX_SW_STATUS__SI                     0x18EC
#define mmDP_CONFIG__SI                                 0x1CC2
#define mmDP_DPHY_8B10B_CNTL__SI                        0x1CD3
#define mmDP_DPHY_CNTL__SI                              0x1CD0
#define mmDP_DPHY_CRC_CNTL__SI                          0x1CD7
#define mmDP_DPHY_CRC_EN__SI                            0x1CD6
#define mmDP_DPHY_CRC_RESULT__SI                        0x1CD8
#define mmDP_DPHY_FAST_TRAINING__SI                     0x1CCE
#define mmDP_DPHY_PRBS_CNTL__SI                         0x1CD4
#define mmDP_DPHY_SYM__SI                               0x1CD2
#define mmDP_DPHY_TRAINING_PATTERN_SEL__SI              0x1CD1
#define mmDP_DTO0_MODULO__SI                            0x0171
#define mmDP_DTO0_PHASE__SI                             0x0170
#define mmDP_DTO1_MODULO__SI                            0x0173
#define mmDP_DTO1_PHASE__SI                             0x0172
#define mmDP_DTO2_MODULO__SI                            0x0175
#define mmDP_DTO2_PHASE__SI                             0x0174
#define mmDP_DTO3_MODULO__SI                            0x0177
#define mmDP_DTO3_PHASE__SI                             0x0176
#define mmDP_DTO4_MODULO__SI                            0x0179
#define mmDP_DTO4_PHASE__SI                             0x0178
#define mmDP_DTO5_MODULO__SI                            0x017B
#define mmDP_DTO5_PHASE__SI                             0x017A
#define mmDP_LINK_CNTL__SI                              0x1CC0
#define mmDP_PIXEL_FORMAT__SI                           0x1CC1
#define mmDP_SEC_AUD_M_READBACK__SI                     0x1CA8
#define mmDP_SEC_AUD_M__SI                              0x1CA7
#define mmDP_SEC_AUD_N_READBACK__SI                     0x1CA6
#define mmDP_SEC_AUD_N__SI                              0x1CA5
#define mmDP_SEC_CNTL__SI                               0x1CA0
#define mmDP_SEC_FRAMING1__SI                           0x1CA1
#define mmDP_SEC_FRAMING2__SI                           0x1CA2
#define mmDP_SEC_FRAMING3__SI                           0x1CA3
#define mmDP_SEC_FRAMING4__SI                           0x1CA4
#define mmDP_SEC_PACKET_CNTL__SI                        0x1CAA
#define mmDP_SEC_TIMESTAMP__SI                          0x1CA9
#define mmDP_STEER_FIFO__SI                             0x1CC4
#define mmDP_TEST_DEBUG_DATA__SI                        0x1CFD
#define mmDP_TEST_DEBUG_INDEX__SI                       0x1CFC
#define mmDP_VID_INTERRUPT_CNTL__SI                     0x1CCF
#define mmDP_VID_MSA_VBID__SI                           0x1CCD
#define mmDP_VID_M__SI                                  0x1CCB
#define mmDP_VID_N__SI                                  0x1CCA
#define mmDP_VID_STREAM_CNTL__SI                        0x1CC3
#define mmDP_VID_TIMING__SI                             0x1CC9
#define mmDVOACLKC_CNTL__SI                             0x014E
#define mmDVOACLKC_MVP_CNTL__SI                         0x014D
#define mmDVOACLKD_CNTL__SI                             0x014C
#define mmDVO_CONTROL__SI                               0x185B
#define mmDVO_CRC2_SIG_MASK__SI                         0x185D
#define mmDVO_CRC2_SIG_RESULT__SI                       0x185E
#define mmDVO_CRC_EN__SI                                0x185C
#define mmDVO_ENABLE__SI                                0x1858
#define mmDVO_OUTPUT__SI                                0x185A
#define mmDVO_SOURCE_SELECT__SI                         0x1859
#define mmDVO_STRENGTH_CONTROL__SI                      0x195D
#define mmEXT_OVERSCAN_LEFT_RIGHT__SI__VI               0x1B5E
#define mmEXT_OVERSCAN_TOP_BOTTOM__SI__VI               0x1B5F
#define mmFBC_CLIENT_REGION_MASK__SI                    0x16EB
#define mmFBC_CNTL__SI                                  0x16D0
#define mmFBC_COMP_CNTL__SI                             0x16D4
#define mmFBC_COMP_MODE__SI                             0x16D5
#define mmFBC_CSM_REGION_OFFSET_01__SI                  0x16E9
#define mmFBC_CSM_REGION_OFFSET_23__SI                  0x16EA
#define mmFBC_DEBUG0__SI                                0x16D6
#define mmFBC_DEBUG1__SI                                0x16D7
#define mmFBC_DEBUG2__SI                                0x16D8
#define mmFBC_DEBUG_COMP__SI                            0x16EC
#define mmFBC_DEBUG_CSR_RDATA__SI                       0x16EE
#define mmFBC_DEBUG_CSR_WDATA__SI                       0x16EF
#define mmFBC_DEBUG_CSR__SI                             0x16ED
#define mmFBC_IDLE_FORCE_CLEAR_MASK__SI                 0x16D2
#define mmFBC_IDLE_MASK__SI                             0x16D1
#define mmFBC_IND_LUT0__SI                              0x16D9
#define mmFBC_IND_LUT10__SI                             0x16E3
#define mmFBC_IND_LUT11__SI                             0x16E4
#define mmFBC_IND_LUT12__SI                             0x16E5
#define mmFBC_IND_LUT13__SI                             0x16E6
#define mmFBC_IND_LUT14__SI                             0x16E7
#define mmFBC_IND_LUT15__SI                             0x16E8
#define mmFBC_IND_LUT1__SI                              0x16DA
#define mmFBC_IND_LUT2__SI                              0x16DB
#define mmFBC_IND_LUT3__SI                              0x16DC
#define mmFBC_IND_LUT4__SI                              0x16DD
#define mmFBC_IND_LUT5__SI                              0x16DE
#define mmFBC_IND_LUT6__SI                              0x16DF
#define mmFBC_IND_LUT7__SI                              0x16E0
#define mmFBC_IND_LUT8__SI                              0x16E1
#define mmFBC_IND_LUT9__SI                              0x16E2
#define mmFBC_MISC__SI                                  0x16F0
#define mmFBC_START_STOP_DELAY__SI                      0x16D3
#define mmFBC_TEST_DEBUG_DATA__SI                       0x16F5
#define mmFBC_TEST_DEBUG_INDEX__SI                      0x16F4
#define mmFMT0_FMT_BIT_DEPTH_CONTROL__SI__VI            0x1BF2
#define mmFMT0_FMT_CLAMP_CNTL__SI__VI                   0x1BF9
#define mmFMT0_FMT_CONTROL__SI__VI                      0x1BEE
#define mmFMT0_FMT_CRC_CNTL__SI__VI                     0x1BFA
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI    0x1BFC
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL__SI__VI         0x1BFE
#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK__SI__VI       0x1BFB
#define mmFMT0_FMT_CRC_SIG_RED_GREEN__SI__VI            0x1BFD
#define mmFMT0_FMT_DEBUG_CNTL__SI__VI                   0x1BFF
#define mmFMT0_FMT_DITHER_RAND_B_SEED__SI__VI           0x1BF5
#define mmFMT0_FMT_DITHER_RAND_G_SEED__SI__VI           0x1BF4
#define mmFMT0_FMT_DITHER_RAND_R_SEED__SI__VI           0x1BF3
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL__SI__VI             0x1BED
#define mmFMT0_FMT_FORCE_DATA_0_1__SI__VI               0x1BF0
#define mmFMT0_FMT_FORCE_DATA_2_3__SI__VI               0x1BF1
#define mmFMT0_FMT_FORCE_OUTPUT_CNTL__SI__VI            0x1BEF
#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI 0x1BF6
#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI 0x1BF7
#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI 0x1BF8
#define mmFMT1_FMT_BIT_DEPTH_CONTROL__SI                0x1EF2
#define mmFMT1_FMT_CLAMP_CNTL__SI                       0x1EF9
#define mmFMT1_FMT_CONTROL__SI                          0x1EEE
#define mmFMT1_FMT_CRC_CNTL__SI                         0x1EFA
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI        0x1EFC
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL__SI             0x1EFE
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK__SI           0x1EFB
#define mmFMT1_FMT_CRC_SIG_RED_GREEN__SI                0x1EFD
#define mmFMT1_FMT_DEBUG_CNTL__SI                       0x1EFF
#define mmFMT1_FMT_DITHER_RAND_B_SEED__SI               0x1EF5
#define mmFMT1_FMT_DITHER_RAND_G_SEED__SI               0x1EF4
#define mmFMT1_FMT_DITHER_RAND_R_SEED__SI               0x1EF3
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL__SI                 0x1EED
#define mmFMT1_FMT_FORCE_DATA_0_1__SI                   0x1EF0
#define mmFMT1_FMT_FORCE_DATA_2_3__SI                   0x1EF1
#define mmFMT1_FMT_FORCE_OUTPUT_CNTL__SI                0x1EEF
#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI  0x1EF6
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x1EF7
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x1EF8
#define mmFMT2_FMT_BIT_DEPTH_CONTROL__SI                0x41F2
#define mmFMT2_FMT_CLAMP_CNTL__SI                       0x41F9
#define mmFMT2_FMT_CONTROL__SI                          0x41EE
#define mmFMT2_FMT_CRC_CNTL__SI                         0x41FA
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI        0x41FC
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL__SI             0x41FE
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK__SI           0x41FB
#define mmFMT2_FMT_CRC_SIG_RED_GREEN__SI                0x41FD
#define mmFMT2_FMT_DEBUG_CNTL__SI                       0x41FF
#define mmFMT2_FMT_DITHER_RAND_B_SEED__SI               0x41F5
#define mmFMT2_FMT_DITHER_RAND_G_SEED__SI               0x41F4
#define mmFMT2_FMT_DITHER_RAND_R_SEED__SI               0x41F3
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL__SI                 0x41ED
#define mmFMT2_FMT_FORCE_DATA_0_1__SI                   0x41F0
#define mmFMT2_FMT_FORCE_DATA_2_3__SI                   0x41F1
#define mmFMT2_FMT_FORCE_OUTPUT_CNTL__SI                0x41EF
#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI  0x41F6
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x41F7
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x41F8
#define mmFMT3_FMT_BIT_DEPTH_CONTROL__SI                0x44F2
#define mmFMT3_FMT_CLAMP_CNTL__SI                       0x44F9
#define mmFMT3_FMT_CONTROL__SI                          0x44EE
#define mmFMT3_FMT_CRC_CNTL__SI                         0x44FA
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI        0x44FC
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL__SI             0x44FE
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK__SI           0x44FB
#define mmFMT3_FMT_CRC_SIG_RED_GREEN__SI                0x44FD
#define mmFMT3_FMT_DEBUG_CNTL__SI                       0x44FF
#define mmFMT3_FMT_DITHER_RAND_B_SEED__SI               0x44F5
#define mmFMT3_FMT_DITHER_RAND_G_SEED__SI               0x44F4
#define mmFMT3_FMT_DITHER_RAND_R_SEED__SI               0x44F3
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL__SI                 0x44ED
#define mmFMT3_FMT_FORCE_DATA_0_1__SI                   0x44F0
#define mmFMT3_FMT_FORCE_DATA_2_3__SI                   0x44F1
#define mmFMT3_FMT_FORCE_OUTPUT_CNTL__SI                0x44EF
#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI  0x44F6
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x44F7
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x44F8
#define mmFMT4_FMT_BIT_DEPTH_CONTROL__SI                0x47F2
#define mmFMT4_FMT_CLAMP_CNTL__SI                       0x47F9
#define mmFMT4_FMT_CONTROL__SI                          0x47EE
#define mmFMT4_FMT_CRC_CNTL__SI                         0x47FA
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI        0x47FC
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL__SI             0x47FE
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK__SI           0x47FB
#define mmFMT4_FMT_CRC_SIG_RED_GREEN__SI                0x47FD
#define mmFMT4_FMT_DEBUG_CNTL__SI                       0x47FF
#define mmFMT4_FMT_DITHER_RAND_B_SEED__SI               0x47F5
#define mmFMT4_FMT_DITHER_RAND_G_SEED__SI               0x47F4
#define mmFMT4_FMT_DITHER_RAND_R_SEED__SI               0x47F3
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL__SI                 0x47ED
#define mmFMT4_FMT_FORCE_DATA_0_1__SI                   0x47F0
#define mmFMT4_FMT_FORCE_DATA_2_3__SI                   0x47F1
#define mmFMT4_FMT_FORCE_OUTPUT_CNTL__SI                0x47EF
#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI  0x47F6
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x47F7
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x47F8
#define mmFMT5_FMT_BIT_DEPTH_CONTROL__SI                0x4AF2
#define mmFMT5_FMT_CLAMP_CNTL__SI                       0x4AF9
#define mmFMT5_FMT_CONTROL__SI                          0x4AEE
#define mmFMT5_FMT_CRC_CNTL__SI                         0x4AFA
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI        0x4AFC
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL__SI             0x4AFE
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK__SI           0x4AFB
#define mmFMT5_FMT_CRC_SIG_RED_GREEN__SI                0x4AFD
#define mmFMT5_FMT_DEBUG_CNTL__SI                       0x4AFF
#define mmFMT5_FMT_DITHER_RAND_B_SEED__SI               0x4AF5
#define mmFMT5_FMT_DITHER_RAND_G_SEED__SI               0x4AF4
#define mmFMT5_FMT_DITHER_RAND_R_SEED__SI               0x4AF3
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL__SI                 0x4AED
#define mmFMT5_FMT_FORCE_DATA_0_1__SI                   0x4AF0
#define mmFMT5_FMT_FORCE_DATA_2_3__SI                   0x4AF1
#define mmFMT5_FMT_FORCE_OUTPUT_CNTL__SI                0x4AEF
#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI  0x4AF6
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI 0x4AF7
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI 0x4AF8
#define mmFMT_BIT_DEPTH_CONTROL__SI__VI                 0x1BF2
#define mmFMT_CLAMP_CNTL__SI__VI                        0x1BF9
#define mmFMT_CONTROL__SI__VI                           0x1BEE
#define mmFMT_CRC_CNTL__SI__VI                          0x1BFA
#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI         0x1BFC
#define mmFMT_CRC_SIG_BLUE_CONTROL__SI__VI              0x1BFE
#define mmFMT_CRC_SIG_RED_GREEN_MASK__SI__VI            0x1BFB
#define mmFMT_CRC_SIG_RED_GREEN__SI__VI                 0x1BFD
#define mmFMT_DEBUG_CNTL__SI__VI                        0x1BFF
#define mmFMT_DITHER_RAND_B_SEED__SI__VI                0x1BF5
#define mmFMT_DITHER_RAND_G_SEED__SI__VI                0x1BF4
#define mmFMT_DITHER_RAND_R_SEED__SI__VI                0x1BF3
#define mmFMT_DYNAMIC_EXP_CNTL__SI__VI                  0x1BED
#define mmFMT_FORCE_DATA_0_1__SI__VI                    0x1BF0
#define mmFMT_FORCE_DATA_2_3__SI__VI                    0x1BF1
#define mmFMT_FORCE_OUTPUT_CNTL__SI__VI                 0x1BEF
#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI   0x1BF6
#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI 0x1BF7
#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI 0x1BF8
#define mmGARLIC_FLUSH_ADDR_END_0__CI__VI               0x1403
#define mmGARLIC_FLUSH_ADDR_END_1__CI__VI               0x1405
#define mmGARLIC_FLUSH_ADDR_END_2__CI__VI               0x1407
#define mmGARLIC_FLUSH_ADDR_END_3__CI__VI               0x1409
#define mmGARLIC_FLUSH_ADDR_END_4__CI__VI               0x140B
#define mmGARLIC_FLUSH_ADDR_END_5__CI__VI               0x140D
#define mmGARLIC_FLUSH_ADDR_END_6__CI__VI               0x140F
#define mmGARLIC_FLUSH_ADDR_END_7__CI__VI               0x1411
#define mmGARLIC_FLUSH_ADDR_START_0__CI__VI             0x1402
#define mmGARLIC_FLUSH_ADDR_START_1__CI__VI             0x1404
#define mmGARLIC_FLUSH_ADDR_START_2__CI__VI             0x1406
#define mmGARLIC_FLUSH_ADDR_START_3__CI__VI             0x1408
#define mmGARLIC_FLUSH_ADDR_START_4__CI__VI             0x140A
#define mmGARLIC_FLUSH_ADDR_START_5__CI__VI             0x140C
#define mmGARLIC_FLUSH_ADDR_START_6__CI__VI             0x140E
#define mmGARLIC_FLUSH_ADDR_START_7__CI__VI             0x1410
#define mmGARLIC_FLUSH_CNTL__CI__VI                     0x1401
#define mmGARLIC_FLUSH_REQ__CI__VI                      0x1412
#define mmGB_ADDR_CONFIG                                0x263E
#define mmGB_BACKEND_MAP                                0x263F
#define mmGB_EDC_MODE                                   0x307E
#define mmGB_GPU_ID                                     0x2640
#define mmGB_MACROTILE_MODE0__CI__VI                    0x2664
#define mmGB_MACROTILE_MODE10__CI__VI                   0x266E
#define mmGB_MACROTILE_MODE11__CI__VI                   0x266F
#define mmGB_MACROTILE_MODE12__CI__VI                   0x2670
#define mmGB_MACROTILE_MODE13__CI__VI                   0x2671
#define mmGB_MACROTILE_MODE14__CI__VI                   0x2672
#define mmGB_MACROTILE_MODE15__CI__VI                   0x2673
#define mmGB_MACROTILE_MODE1__CI__VI                    0x2665
#define mmGB_MACROTILE_MODE2__CI__VI                    0x2666
#define mmGB_MACROTILE_MODE3__CI__VI                    0x2667
#define mmGB_MACROTILE_MODE4__CI__VI                    0x2668
#define mmGB_MACROTILE_MODE5__CI__VI                    0x2669
#define mmGB_MACROTILE_MODE6__CI__VI                    0x266A
#define mmGB_MACROTILE_MODE7__CI__VI                    0x266B
#define mmGB_MACROTILE_MODE8__CI__VI                    0x266C
#define mmGB_MACROTILE_MODE9__CI__VI                    0x266D
#define mmGB_TILE_MODE0                                 0x2644
#define mmGB_TILE_MODE1                                 0x2645
#define mmGB_TILE_MODE10                                0x264E
#define mmGB_TILE_MODE11                                0x264F
#define mmGB_TILE_MODE12                                0x2650
#define mmGB_TILE_MODE13                                0x2651
#define mmGB_TILE_MODE14                                0x2652
#define mmGB_TILE_MODE15                                0x2653
#define mmGB_TILE_MODE16                                0x2654
#define mmGB_TILE_MODE17                                0x2655
#define mmGB_TILE_MODE18                                0x2656
#define mmGB_TILE_MODE19                                0x2657
#define mmGB_TILE_MODE2                                 0x2646
#define mmGB_TILE_MODE20                                0x2658
#define mmGB_TILE_MODE21                                0x2659
#define mmGB_TILE_MODE22                                0x265A
#define mmGB_TILE_MODE23                                0x265B
#define mmGB_TILE_MODE24                                0x265C
#define mmGB_TILE_MODE25                                0x265D
#define mmGB_TILE_MODE26                                0x265E
#define mmGB_TILE_MODE27                                0x265F
#define mmGB_TILE_MODE28                                0x2660
#define mmGB_TILE_MODE29                                0x2661
#define mmGB_TILE_MODE3                                 0x2647
#define mmGB_TILE_MODE30                                0x2662
#define mmGB_TILE_MODE31                                0x2663
#define mmGB_TILE_MODE4                                 0x2648
#define mmGB_TILE_MODE5                                 0x2649
#define mmGB_TILE_MODE6                                 0x264A
#define mmGB_TILE_MODE7                                 0x264B
#define mmGB_TILE_MODE8                                 0x264C
#define mmGB_TILE_MODE9                                 0x264D
#define mmGCK_SMC_IND_DATA__CI__VI                      0x0081
#define mmGCK_SMC_IND_INDEX__CI__VI                     0x0080
#define mmGC_USER_PRIM_CONFIG__CI__VI                   0x2241
#define mmGC_USER_RB_BACKEND_DISABLE                    0x26DF
#define mmGC_USER_RB_REDUNDANCY__CI__VI                 0x26DE
#define mmGC_USER_SHADER_ARRAY_CONFIG                   0x2270
#define mmGC_USER_SYS_RB_BACKEND_DISABLE                0x03A1
#define mmGDS_ATOM_BASE__CI__VI                         0xC40C
#define mmGDS_ATOM_BASE__SI                             0x25CE
#define mmGDS_ATOM_CNTL__CI__VI                         0xC40A
#define mmGDS_ATOM_CNTL__SI                             0x25CC
#define mmGDS_ATOM_COMPLETE__CI__VI                     0xC40B
#define mmGDS_ATOM_COMPLETE__SI                         0x25CD
#define mmGDS_ATOM_DST__CI__VI                          0xC410
#define mmGDS_ATOM_DST__SI                              0x25D2
#define mmGDS_ATOM_OFFSET0__CI__VI                      0xC40E
#define mmGDS_ATOM_OFFSET0__SI                          0x25D0
#define mmGDS_ATOM_OFFSET1__CI__VI                      0xC40F
#define mmGDS_ATOM_OFFSET1__SI                          0x25D1
#define mmGDS_ATOM_OP__CI__VI                           0xC411
#define mmGDS_ATOM_OP__SI                               0x25D3
#define mmGDS_ATOM_READ0_U__CI__VI                      0xC417
#define mmGDS_ATOM_READ0_U__SI                          0x25D9
#define mmGDS_ATOM_READ0__CI__VI                        0xC416
#define mmGDS_ATOM_READ0__SI                            0x25D8
#define mmGDS_ATOM_READ1_U__CI__VI                      0xC419
#define mmGDS_ATOM_READ1_U__SI                          0x25DB
#define mmGDS_ATOM_READ1__CI__VI                        0xC418
#define mmGDS_ATOM_READ1__SI                            0x25DA
#define mmGDS_ATOM_SIZE__CI__VI                         0xC40D
#define mmGDS_ATOM_SIZE__SI                             0x25CF
#define mmGDS_ATOM_SRC0_U__CI__VI                       0xC413
#define mmGDS_ATOM_SRC0_U__SI                           0x25D5
#define mmGDS_ATOM_SRC0__CI__VI                         0xC412
#define mmGDS_ATOM_SRC0__SI                             0x25D4
#define mmGDS_ATOM_SRC1_U__CI__VI                       0xC415
#define mmGDS_ATOM_SRC1_U__SI                           0x25D7
#define mmGDS_ATOM_SRC1__CI__VI                         0xC414
#define mmGDS_ATOM_SRC1__SI                             0x25D6
#define mmGDS_CNTL_STATUS                               0x25C1
#define mmGDS_COMPUTE_MAX_WAVE_ID__CI__VI               0x3348
#define mmGDS_CONFIG                                    0x25C0
#define mmGDS_DEBUG_CNTL__CI__VI                        0x25C8
#define mmGDS_DEBUG_CNTL__SI                            0x25DE
#define mmGDS_DEBUG_DATA__CI__VI                        0x25C9
#define mmGDS_DEBUG_DATA__SI                            0x25DF
#define mmGDS_ENHANCE2__CI__VI                          0x25C2
#define mmGDS_ENHANCE__CI__VI                           0x334B
#define mmGDS_ENHANCE__SI                               0x25DC
#define mmGDS_GRBM_SECDED_CNT__CI                       0x25C6
#define mmGDS_GRBM_SECDED_CNT__SI                       0x25E3
#define mmGDS_GWS_RESET0__CI__VI                        0x3344
#define mmGDS_GWS_RESET1__CI__VI                        0x3345
#define mmGDS_GWS_RESOURCE_CNTL__CI__VI                 0xC41A
#define mmGDS_GWS_RESOURCE_CNTL__SI                     0x25E0
#define mmGDS_GWS_RESOURCE_CNT__CI__VI                  0xC41C
#define mmGDS_GWS_RESOURCE_RESET__CI__VI                0x3346
#define mmGDS_GWS_RESOURCE__CI__VI                      0xC41B
#define mmGDS_GWS_RESOURCE__SI                          0x25E1
#define mmGDS_GWS_VMID0__CI__VI                         0x3320
#define mmGDS_GWS_VMID10__CI__VI                        0x332A
#define mmGDS_GWS_VMID11__CI__VI                        0x332B
#define mmGDS_GWS_VMID12__CI__VI                        0x332C
#define mmGDS_GWS_VMID13__CI__VI                        0x332D
#define mmGDS_GWS_VMID14__CI__VI                        0x332E
#define mmGDS_GWS_VMID15__CI__VI                        0x332F
#define mmGDS_GWS_VMID1__CI__VI                         0x3321
#define mmGDS_GWS_VMID2__CI__VI                         0x3322
#define mmGDS_GWS_VMID3__CI__VI                         0x3323
#define mmGDS_GWS_VMID4__CI__VI                         0x3324
#define mmGDS_GWS_VMID5__CI__VI                         0x3325
#define mmGDS_GWS_VMID6__CI__VI                         0x3326
#define mmGDS_GWS_VMID7__CI__VI                         0x3327
#define mmGDS_GWS_VMID8__CI__VI                         0x3328
#define mmGDS_GWS_VMID9__CI__VI                         0x3329
#define mmGDS_OA_ADDRESS__CI__VI                        0xC41F
#define mmGDS_OA_CGPG_RESTORE__CI__VI                   0x334C
#define mmGDS_OA_CNTL__CI__VI                           0xC41D
#define mmGDS_OA_COUNTER__CI__VI                        0xC41E
#define mmGDS_OA_DED__CI                                0x25C7
#define mmGDS_OA_DED__SI                                0x25E4
#define mmGDS_OA_INCDEC__CI__VI                         0xC420
#define mmGDS_OA_RESET_MASK__CI__VI                     0x3349
#define mmGDS_OA_RESET__CI__VI                          0x334A
#define mmGDS_OA_RING_SIZE__CI__VI                      0xC421
#define mmGDS_OA_VMID0__CI__VI                          0x3330
#define mmGDS_OA_VMID10__CI__VI                         0x333A
#define mmGDS_OA_VMID11__CI__VI                         0x333B
#define mmGDS_OA_VMID12__CI__VI                         0x333C
#define mmGDS_OA_VMID13__CI__VI                         0x333D
#define mmGDS_OA_VMID14__CI__VI                         0x333E
#define mmGDS_OA_VMID15__CI__VI                         0x333F
#define mmGDS_OA_VMID1__CI__VI                          0x3331
#define mmGDS_OA_VMID2__CI__VI                          0x3332
#define mmGDS_OA_VMID3__CI__VI                          0x3333
#define mmGDS_OA_VMID4__CI__VI                          0x3334
#define mmGDS_OA_VMID5__CI__VI                          0x3335
#define mmGDS_OA_VMID6__CI__VI                          0x3336
#define mmGDS_OA_VMID7__CI__VI                          0x3337
#define mmGDS_OA_VMID8__CI__VI                          0x3338
#define mmGDS_OA_VMID9__CI__VI                          0x3339
#define mmGDS_PERFCOUNTER0_HI__CI__VI                   0xD281
#define mmGDS_PERFCOUNTER0_HI__SI                       0x25E7
#define mmGDS_PERFCOUNTER0_LO__CI__VI                   0xD280
#define mmGDS_PERFCOUNTER0_LO__SI                       0x25E6
#define mmGDS_PERFCOUNTER0_SELECT1__CI__VI              0xDA84
#define mmGDS_PERFCOUNTER0_SELECT__CI__VI               0xDA80
#define mmGDS_PERFCOUNTER0_SELECT__SI                   0x25E5
#define mmGDS_PERFCOUNTER1_HI__CI__VI                   0xD283
#define mmGDS_PERFCOUNTER1_HI__SI                       0x25EA
#define mmGDS_PERFCOUNTER1_LO__CI__VI                   0xD282
#define mmGDS_PERFCOUNTER1_LO__SI                       0x25E9
#define mmGDS_PERFCOUNTER1_SELECT__CI__VI               0xDA81
#define mmGDS_PERFCOUNTER1_SELECT__SI                   0x25E8
#define mmGDS_PERFCOUNTER2_HI__CI__VI                   0xD285
#define mmGDS_PERFCOUNTER2_HI__SI                       0x25ED
#define mmGDS_PERFCOUNTER2_LO__CI__VI                   0xD284
#define mmGDS_PERFCOUNTER2_LO__SI                       0x25EC
#define mmGDS_PERFCOUNTER2_SELECT__CI__VI               0xDA82
#define mmGDS_PERFCOUNTER2_SELECT__SI                   0x25EB
#define mmGDS_PERFCOUNTER3_HI__CI__VI                   0xD287
#define mmGDS_PERFCOUNTER3_HI__SI                       0x25F0
#define mmGDS_PERFCOUNTER3_LO__CI__VI                   0xD286
#define mmGDS_PERFCOUNTER3_LO__SI                       0x25EF
#define mmGDS_PERFCOUNTER3_SELECT__CI__VI               0xDA83
#define mmGDS_PERFCOUNTER3_SELECT__SI                   0x25EE
#define mmGDS_PROTECTION_FAULT__CI__VI                  0x25C3
#define mmGDS_RD_ADDR__CI__VI                           0xC400
#define mmGDS_RD_ADDR__SI                               0x25C2
#define mmGDS_RD_BURST_ADDR__CI__VI                     0xC402
#define mmGDS_RD_BURST_ADDR__SI                         0x25C4
#define mmGDS_RD_BURST_COUNT__CI__VI                    0xC403
#define mmGDS_RD_BURST_COUNT__SI                        0x25C5
#define mmGDS_RD_BURST_DATA__CI__VI                     0xC404
#define mmGDS_RD_BURST_DATA__SI                         0x25C6
#define mmGDS_RD_DATA__CI__VI                           0xC401
#define mmGDS_RD_DATA__SI                               0x25C3
#define mmGDS_SECDED_CNT__CI                            0x25C5
#define mmGDS_SECDED_CNT__SI                            0x25E2
#define mmGDS_VMID0_BASE__CI__VI                        0x3300
#define mmGDS_VMID0_SIZE__CI__VI                        0x3301
#define mmGDS_VMID10_BASE__CI__VI                       0x3314
#define mmGDS_VMID10_SIZE__CI__VI                       0x3315
#define mmGDS_VMID11_BASE__CI__VI                       0x3316
#define mmGDS_VMID11_SIZE__CI__VI                       0x3317
#define mmGDS_VMID12_BASE__CI__VI                       0x3318
#define mmGDS_VMID12_SIZE__CI__VI                       0x3319
#define mmGDS_VMID13_BASE__CI__VI                       0x331A
#define mmGDS_VMID13_SIZE__CI__VI                       0x331B
#define mmGDS_VMID14_BASE__CI__VI                       0x331C
#define mmGDS_VMID14_SIZE__CI__VI                       0x331D
#define mmGDS_VMID15_BASE__CI__VI                       0x331E
#define mmGDS_VMID15_SIZE__CI__VI                       0x331F
#define mmGDS_VMID1_BASE__CI__VI                        0x3302
#define mmGDS_VMID1_SIZE__CI__VI                        0x3303
#define mmGDS_VMID2_BASE__CI__VI                        0x3304
#define mmGDS_VMID2_SIZE__CI__VI                        0x3305
#define mmGDS_VMID3_BASE__CI__VI                        0x3306
#define mmGDS_VMID3_SIZE__CI__VI                        0x3307
#define mmGDS_VMID4_BASE__CI__VI                        0x3308
#define mmGDS_VMID4_SIZE__CI__VI                        0x3309
#define mmGDS_VMID5_BASE__CI__VI                        0x330A
#define mmGDS_VMID5_SIZE__CI__VI                        0x330B
#define mmGDS_VMID6_BASE__CI__VI                        0x330C
#define mmGDS_VMID6_SIZE__CI__VI                        0x330D
#define mmGDS_VMID7_BASE__CI__VI                        0x330E
#define mmGDS_VMID7_SIZE__CI__VI                        0x330F
#define mmGDS_VMID8_BASE__CI__VI                        0x3310
#define mmGDS_VMID8_SIZE__CI__VI                        0x3311
#define mmGDS_VMID9_BASE__CI__VI                        0x3312
#define mmGDS_VMID9_SIZE__CI__VI                        0x3313
#define mmGDS_VM_PROTECTION_FAULT__CI__VI               0x25C4
#define mmGDS_WRITE_COMPLETE__CI__VI                    0xC409
#define mmGDS_WRITE_COMPLETE__SI                        0x25CB
#define mmGDS_WR_ADDR__CI__VI                           0xC405
#define mmGDS_WR_ADDR__SI                               0x25C7
#define mmGDS_WR_BURST_ADDR__CI__VI                     0xC407
#define mmGDS_WR_BURST_ADDR__SI                         0x25C9
#define mmGDS_WR_BURST_DATA__CI__VI                     0xC408
#define mmGDS_WR_BURST_DATA__SI                         0x25CA
#define mmGDS_WR_DATA__CI__VI                           0xC406
#define mmGDS_WR_DATA__SI                               0x25C8
#define mmGENENB__SI__VI                                0x00F0
#define mmGENERAL_PWRMGT__SI                            0x01E0
#define mmGENERIC_I2C_CONTROL__SI                       0x1834
#define mmGENERIC_I2C_DATA__SI                          0x183A
#define mmGENERIC_I2C_INTERRUPT_CONTROL__SI             0x1835
#define mmGENERIC_I2C_PIN_DEBUG__SI                     0x183C
#define mmGENERIC_I2C_PIN_SELECTION__SI                 0x183B
#define mmGENERIC_I2C_SETUP__SI                         0x1838
#define mmGENERIC_I2C_SPEED__SI                         0x1837
#define mmGENERIC_I2C_STATUS__SI                        0x1836
#define mmGENERIC_I2C_TRANSACTION__SI                   0x1839
#define mmGENFC_RD__SI__VI                              0x00F2
#define mmGENFC_WT__SI__VI                              0x00EE
#define mmGENMO_RD__SI__VI                              0x00F3
#define mmGENMO_WT__SI__VI                              0x00F0
#define mmGENS0__SI__VI                                 0x00F0
#define mmGENS1__SI__VI                                 0x00EE
#define mmGFX_COPY_STATE                                0xA1F4
#define mmGFX_PIPE_CONTROL__CI__VI                      0x226D
#define mmGFX_PIPE_PRIORITY__CI__VI                     0xF87F
#define mmGMCON_DEBUG__CI__VI                           0x0D5F
#define mmGMCON_MASK__CI__VI                            0x0D52
#define mmGMCON_MISC2__CI__VI                           0x0D44
#define mmGMCON_MISC3__CI__VI                           0x0D51
#define mmGMCON_MISC__CI__VI                            0x0D43
#define mmGMCON_PERF_MON_CNTL0__CI__VI                  0x0D4A
#define mmGMCON_PERF_MON_CNTL1__CI__VI                  0x0D4B
#define mmGMCON_PERF_MON_RSLT0__CI__VI                  0x0D4C
#define mmGMCON_PERF_MON_RSLT1__CI__VI                  0x0D4D
#define mmGMCON_PGFSM_CONFIG__CI__VI                    0x0D4E
#define mmGMCON_PGFSM_READ__CI__VI                      0x0D50
#define mmGMCON_PGFSM_WRITE__CI__VI                     0x0D4F
#define mmGMCON_RENG_EXECUTE__CI__VI                    0x0D42
#define mmGMCON_RENG_RAM_DATA__CI__VI                   0x0D41
#define mmGMCON_RENG_RAM_INDEX__CI__VI                  0x0D40
#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI  0x0D48
#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI  0x0D49
#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI     0x0D45
#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI     0x0D46
#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI     0x0D47
#define mmGPIOPAD_A__CI__VI                             0x0183
#define mmGPIOPAD_A__SI                                 0x05E7
#define mmGPIOPAD_EN__CI__VI                            0x0184
#define mmGPIOPAD_EN__SI                                0x05E8
#define mmGPIOPAD_EXTERN_TRIG_CNTL__CI__VI              0x018D
#define mmGPIOPAD_EXTERN_TRIG_CNTL__SI                  0x05F1
#define mmGPIOPAD_INT_EN__CI__VI                        0x018A
#define mmGPIOPAD_INT_EN__SI                            0x05EE
#define mmGPIOPAD_INT_POLARITY__CI__VI                  0x018C
#define mmGPIOPAD_INT_POLARITY__SI                      0x05F0
#define mmGPIOPAD_INT_STAT_AK__CI__VI                   0x0189
#define mmGPIOPAD_INT_STAT_AK__SI                       0x05ED
#define mmGPIOPAD_INT_STAT_EN__CI__VI                   0x0187
#define mmGPIOPAD_INT_STAT_EN__SI                       0x05EB
#define mmGPIOPAD_INT_STAT__CI__VI                      0x0188
#define mmGPIOPAD_INT_STAT__SI                          0x05EC
#define mmGPIOPAD_INT_TYPE__CI__VI                      0x018B
#define mmGPIOPAD_INT_TYPE__SI                          0x05EF
#define mmGPIOPAD_MASK__CI__VI                          0x0182
#define mmGPIOPAD_MASK__SI                              0x05E6
#define mmGPIOPAD_PD_EN__CI__VI                         0x0193
#define mmGPIOPAD_PD_EN__SI                             0x05F4
#define mmGPIOPAD_PINSTRAPS__CI__VI                     0x0186
#define mmGPIOPAD_PINSTRAPS__SI                         0x05EA
#define mmGPIOPAD_PU_EN__CI__VI                         0x0192
#define mmGPIOPAD_PU_EN__SI                             0x05F3
#define mmGPIOPAD_RCVR_SEL__CI__VI                      0x0191
#define mmGPIOPAD_RCVR_SEL__SI                          0x05F2
#define mmGPIOPAD_STRENGTH__CI__VI                      0x0181
#define mmGPIOPAD_STRENGTH__SI                          0x05E5
#define mmGPIOPAD_SW_INT_STAT__CI__VI                   0x0180
#define mmGPIOPAD_SW_INT_STAT__SI                       0x05E4
#define mmGPIOPAD_Y__CI__VI                             0x0185
#define mmGPIOPAD_Y__SI                                 0x05E9
#define mmGPU_GARLIC_FLUSH_DONE__CI__VI                 0x1414
#define mmGPU_GARLIC_FLUSH_REQ__CI__VI                  0x1413
#define mmGPU_HDP_FLUSH_DONE__CI__VI                    0x1538
#define mmGPU_HDP_FLUSH_REQ__CI__VI                     0x1537
#define mmGRBM_CNTL                                     0x2000
#define mmGRBM_DEBUG                                    0x2014
#define mmGRBM_DEBUG_CNTL                               0x2009
#define mmGRBM_DEBUG_DATA                               0x200A
#define mmGRBM_DEBUG_SNAPSHOT                           0x2015
#define mmGRBM_GFX_CLKEN_CNTL                           0x200C
#define mmGRBM_GFX_INDEX__CI__VI                        0xC200
#define mmGRBM_GFX_INDEX__SI                            0x200B
#define mmGRBM_INT_CNTL                                 0x2018
#define mmGRBM_NOWHERE                                  0x203F
#define mmGRBM_PERFCOUNTER0_HI__CI__VI                  0xD041
#define mmGRBM_PERFCOUNTER0_HI__SI                      0x201F
#define mmGRBM_PERFCOUNTER0_LO__CI__VI                  0xD040
#define mmGRBM_PERFCOUNTER0_LO__SI                      0x201E
#define mmGRBM_PERFCOUNTER0_SELECT__CI__VI              0xD840
#define mmGRBM_PERFCOUNTER0_SELECT__SI                  0x201C
#define mmGRBM_PERFCOUNTER1_HI__CI__VI                  0xD044
#define mmGRBM_PERFCOUNTER1_HI__SI                      0x2021
#define mmGRBM_PERFCOUNTER1_LO__CI__VI                  0xD043
#define mmGRBM_PERFCOUNTER1_LO__SI                      0x2020
#define mmGRBM_PERFCOUNTER1_SELECT__CI__VI              0xD841
#define mmGRBM_PERFCOUNTER1_SELECT__SI                  0x201D
#define mmGRBM_PWR_CNTL                                 0x2003
#define mmGRBM_READ_ERROR                               0x2016
#define mmGRBM_READ_ERROR2__CI__VI                      0x2017
#define mmGRBM_SCRATCH_REG0                             0x2040
#define mmGRBM_SCRATCH_REG1                             0x2041
#define mmGRBM_SCRATCH_REG2                             0x2042
#define mmGRBM_SCRATCH_REG3                             0x2043
#define mmGRBM_SCRATCH_REG4                             0x2044
#define mmGRBM_SCRATCH_REG5                             0x2045
#define mmGRBM_SCRATCH_REG6                             0x2046
#define mmGRBM_SCRATCH_REG7                             0x2047
#define mmGRBM_SE0_PERFCOUNTER_HI__CI__VI               0xD046
#define mmGRBM_SE0_PERFCOUNTER_HI__SI                   0x202B
#define mmGRBM_SE0_PERFCOUNTER_LO__CI__VI               0xD045
#define mmGRBM_SE0_PERFCOUNTER_LO__SI                   0x202A
#define mmGRBM_SE0_PERFCOUNTER_SELECT__CI__VI           0xD842
#define mmGRBM_SE0_PERFCOUNTER_SELECT__SI               0x2026
#define mmGRBM_SE1_PERFCOUNTER_HI__CI__VI               0xD048
#define mmGRBM_SE1_PERFCOUNTER_HI__SI                   0x202D
#define mmGRBM_SE1_PERFCOUNTER_LO__CI__VI               0xD047
#define mmGRBM_SE1_PERFCOUNTER_LO__SI                   0x202C
#define mmGRBM_SE1_PERFCOUNTER_SELECT__CI__VI           0xD843
#define mmGRBM_SE1_PERFCOUNTER_SELECT__SI               0x2027
#define mmGRBM_SE2_PERFCOUNTER_HI__CI__VI               0xD04A
#define mmGRBM_SE2_PERFCOUNTER_LO__CI__VI               0xD049
#define mmGRBM_SE2_PERFCOUNTER_SELECT__CI__VI           0xD844
#define mmGRBM_SE3_PERFCOUNTER_HI__CI__VI               0xD04C
#define mmGRBM_SE3_PERFCOUNTER_LO__CI__VI               0xD04B
#define mmGRBM_SE3_PERFCOUNTER_SELECT__CI__VI           0xD845
#define mmGRBM_SKEW_CNTL                                0x2001
#define mmGRBM_SOFT_RESET                               0x2008
#define mmGRBM_STATUS                                   0x2004
#define mmGRBM_STATUS2                                  0x2002
#define mmGRBM_STATUS_SE0                               0x2005
#define mmGRBM_STATUS_SE1                               0x2006
#define mmGRBM_STATUS_SE2__CI__VI                       0x200E
#define mmGRBM_STATUS_SE3__CI__VI                       0x200F
#define mmGRBM_WAIT_IDLE_CLOCKS                         0x200D
#define mmGRPH8_DATA__SI__VI                            0x00F3
#define mmGRPH8_IDX__SI__VI                             0x00F3
#define mmGRPH_COMPRESS_PITCH__SI__VI                   0x1A1A
#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI    0x1A1B
#define mmGRPH_COMPRESS_SURFACE_ADDRESS__SI__VI         0x1A19
#define mmGRPH_CONTROL                                  0x1A01
#define mmGRPH_DFQ_CONTROL__SI__VI                      0x1A14
#define mmGRPH_DFQ_STATUS__SI__VI                       0x1A15
#define mmGRPH_ENABLE__SI__VI                           0x1A00
#define mmGRPH_FLIP_CONTROL__SI__VI                     0x1A12
#define mmGRPH_INTERRUPT_CONTROL__SI__VI                0x1A17
#define mmGRPH_INTERRUPT_STATUS__SI__VI                 0x1A16
#define mmGRPH_LUT_10BIT_BYPASS__SI__VI                 0x1A02
#define mmGRPH_PITCH__SI__VI                            0x1A06
#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI__VI     0x1A07
#define mmGRPH_PRIMARY_SURFACE_ADDRESS__SI__VI          0x1A04
#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI   0x1A08
#define mmGRPH_SECONDARY_SURFACE_ADDRESS__SI__VI        0x1A05
#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI       0x1A18
#define mmGRPH_SURFACE_ADDRESS_INUSE__SI__VI            0x1A13
#define mmGRPH_SURFACE_OFFSET_X__SI__VI                 0x1A09
#define mmGRPH_SURFACE_OFFSET_Y__SI__VI                 0x1A0A
#define mmGRPH_SWAP_CNTL__SI__VI                        0x1A03
#define mmGRPH_UPDATE__SI__VI                           0x1A11
#define mmGRPH_X_END__SI__VI                            0x1A0D
#define mmGRPH_X_START__SI__VI                          0x1A0B
#define mmGRPH_Y_END__SI__VI                            0x1A0E
#define mmGRPH_Y_START__SI__VI                          0x1A0C
#define mmHDMI_ACR_32_0__SI                             0x1C37
#define mmHDMI_ACR_32_1__SI                             0x1C38
#define mmHDMI_ACR_44_0__SI                             0x1C39
#define mmHDMI_ACR_44_1__SI                             0x1C3A
#define mmHDMI_ACR_48_0__SI                             0x1C3B
#define mmHDMI_ACR_48_1__SI                             0x1C3C
#define mmHDMI_ACR_PACKET_CONTROL__SI                   0x1C0F
#define mmHDMI_ACR_STATUS_0__SI                         0x1C3D
#define mmHDMI_ACR_STATUS_1__SI                         0x1C3E
#define mmHDMI_AUDIO_PACKET_CONTROL__SI                 0x1C0E
#define mmHDMI_CONTROL__SI                              0x1C0C
#define mmHDMI_GC__SI                                   0x1C16
#define mmHDMI_GENERIC_PACKET_CONTROL__SI               0x1C13
#define mmHDMI_INFOFRAME_CONTROL0__SI                   0x1C11
#define mmHDMI_INFOFRAME_CONTROL1__SI                   0x1C12
#define mmHDMI_STATUS__SI                               0x1C0D
#define mmHDMI_VBI_PACKET_CONTROL__SI                   0x1C10
#define mmHDP_DEBUG0                                    0x0BCC
#define mmHDP_DEBUG1                                    0x0BCD
#define mmHDP_HOST_PATH_CNTL                            0x0B00
#define mmHDP_LAST_SURFACE_HIT                          0x0BCE
#define mmHDP_MEM_COHERENCY_FLUSH_CNTL                  0x1520
#define mmHDP_NONSURFACE_BASE                           0x0B01
#define mmHDP_NONSURFACE_INFO                           0x0B02
#define mmHDP_NONSURFACE_SIZE                           0x0B03
#define mmHDP_NONSURF_FLAGS                             0x0BC9
#define mmHDP_NONSURF_FLAGS_CLR                         0x0BCA
#define mmHDP_OUTSTANDING_REQ                           0x0BD1
#define mmHDP_REG_COHERENCY_FLUSH_CNTL                  0x1528
#define mmHDP_SC_MULTI_CHIP_CNTL                        0x0BD0
#define mmHDP_SW_SEMAPHORE                              0x0BCB
#define mmHDP_TILING_CONFIG                             0x0BCF
#define mmHDP_XDP_BUSY_STS                              0x0C3E
#define mmHDP_XDP_CGTT_BLK_CTRL                         0x0C33
#define mmHDP_XDP_CHKN                                  0x0C40
#define mmHDP_XDP_D2H_BAR_UPDATE                        0x0C02
#define mmHDP_XDP_D2H_FLUSH                             0x0C01
#define mmHDP_XDP_D2H_RSVD_10                           0x0C0A
#define mmHDP_XDP_D2H_RSVD_11                           0x0C0B
#define mmHDP_XDP_D2H_RSVD_12                           0x0C0C
#define mmHDP_XDP_D2H_RSVD_13                           0x0C0D
#define mmHDP_XDP_D2H_RSVD_14                           0x0C0E
#define mmHDP_XDP_D2H_RSVD_15                           0x0C0F
#define mmHDP_XDP_D2H_RSVD_16                           0x0C10
#define mmHDP_XDP_D2H_RSVD_17                           0x0C11
#define mmHDP_XDP_D2H_RSVD_18                           0x0C12
#define mmHDP_XDP_D2H_RSVD_19                           0x0C13
#define mmHDP_XDP_D2H_RSVD_20                           0x0C14
#define mmHDP_XDP_D2H_RSVD_21                           0x0C15
#define mmHDP_XDP_D2H_RSVD_22                           0x0C16
#define mmHDP_XDP_D2H_RSVD_23                           0x0C17
#define mmHDP_XDP_D2H_RSVD_24                           0x0C18
#define mmHDP_XDP_D2H_RSVD_25                           0x0C19
#define mmHDP_XDP_D2H_RSVD_26                           0x0C1A
#define mmHDP_XDP_D2H_RSVD_27                           0x0C1B
#define mmHDP_XDP_D2H_RSVD_28                           0x0C1C
#define mmHDP_XDP_D2H_RSVD_29                           0x0C1D
#define mmHDP_XDP_D2H_RSVD_3                            0x0C03
#define mmHDP_XDP_D2H_RSVD_30                           0x0C1E
#define mmHDP_XDP_D2H_RSVD_31                           0x0C1F
#define mmHDP_XDP_D2H_RSVD_32                           0x0C20
#define mmHDP_XDP_D2H_RSVD_33                           0x0C21
#define mmHDP_XDP_D2H_RSVD_34                           0x0C22
#define mmHDP_XDP_D2H_RSVD_4                            0x0C04
#define mmHDP_XDP_D2H_RSVD_5                            0x0C05
#define mmHDP_XDP_D2H_RSVD_6                            0x0C06
#define mmHDP_XDP_D2H_RSVD_7                            0x0C07
#define mmHDP_XDP_D2H_RSVD_8                            0x0C08
#define mmHDP_XDP_D2H_RSVD_9                            0x0C09
#define mmHDP_XDP_DBG_ADDR                              0x0C41
#define mmHDP_XDP_DBG_DATA                              0x0C42
#define mmHDP_XDP_DBG_MASK                              0x0C43
#define mmHDP_XDP_DIRECT2HDP_FIRST                      0x0C00
#define mmHDP_XDP_DIRECT2HDP_LAST                       0x0C23
#define mmHDP_XDP_FLUSH_ARMED_STS                       0x0C3C
#define mmHDP_XDP_FLUSH_CNTR0_STS                       0x0C3D
#define mmHDP_XDP_HDP_IPH_CFG                           0x0C31
#define mmHDP_XDP_HDP_MBX_MC_CFG                        0x0C2D
#define mmHDP_XDP_HDP_MC_CFG                            0x0C2E
#define mmHDP_XDP_HST_CFG                               0x0C2F
#define mmHDP_XDP_P2P_BAR0                              0x0C34
#define mmHDP_XDP_P2P_BAR1                              0x0C35
#define mmHDP_XDP_P2P_BAR2                              0x0C36
#define mmHDP_XDP_P2P_BAR3                              0x0C37
#define mmHDP_XDP_P2P_BAR4                              0x0C38
#define mmHDP_XDP_P2P_BAR5                              0x0C39
#define mmHDP_XDP_P2P_BAR6                              0x0C3A
#define mmHDP_XDP_P2P_BAR7                              0x0C3B
#define mmHDP_XDP_P2P_BAR_CFG                           0x0C24
#define mmHDP_XDP_P2P_MBX_ADDR0                         0x0C26
#define mmHDP_XDP_P2P_MBX_ADDR1                         0x0C27
#define mmHDP_XDP_P2P_MBX_ADDR2                         0x0C28
#define mmHDP_XDP_P2P_MBX_ADDR3                         0x0C29
#define mmHDP_XDP_P2P_MBX_ADDR4                         0x0C2A
#define mmHDP_XDP_P2P_MBX_ADDR5                         0x0C2B
#define mmHDP_XDP_P2P_MBX_ADDR6                         0x0C2C
#define mmHDP_XDP_P2P_MBX_OFFSET                        0x0C25
#define mmHDP_XDP_SID_CFG                               0x0C30
#define mmHDP_XDP_SRBM_CFG                              0x0C32
#define mmHDP_XDP_STICKY                                0x0C3F
#define mmHOST_BUSNUM                                   0x153D
#define mmHW_DEBUG                                      0x1515
#define mmIA_CNTL_STATUS                                0x2237
#define mmIA_DEBUG_CNTL                                 0x223A
#define mmIA_DEBUG_DATA                                 0x223B
#define mmIA_ENHANCE                                    0xA29C
#define mmIA_MULTI_VGT_PARAM                            0xA2AA
#define mmIA_PERFCOUNTER0_HI__CI__VI                    0xD089
#define mmIA_PERFCOUNTER0_HI__SI                        0x2225
#define mmIA_PERFCOUNTER0_LO__CI__VI                    0xD088
#define mmIA_PERFCOUNTER0_LO__SI                        0x2224
#define mmIA_PERFCOUNTER0_SELECT1__CI__VI               0xD888
#define mmIA_PERFCOUNTER0_SELECT__CI__VI                0xD884
#define mmIA_PERFCOUNTER0_SELECT__SI                    0x2220
#define mmIA_PERFCOUNTER1_HI__CI__VI                    0xD08B
#define mmIA_PERFCOUNTER1_HI__SI                        0x2227
#define mmIA_PERFCOUNTER1_LO__CI__VI                    0xD08A
#define mmIA_PERFCOUNTER1_LO__SI                        0x2226
#define mmIA_PERFCOUNTER1_SELECT__CI__VI                0xD885
#define mmIA_PERFCOUNTER1_SELECT__SI                    0x2221
#define mmIA_PERFCOUNTER2_HI__CI__VI                    0xD08D
#define mmIA_PERFCOUNTER2_HI__SI                        0x2229
#define mmIA_PERFCOUNTER2_LO__CI__VI                    0xD08C
#define mmIA_PERFCOUNTER2_LO__SI                        0x2228
#define mmIA_PERFCOUNTER2_SELECT__CI__VI                0xD886
#define mmIA_PERFCOUNTER2_SELECT__SI                    0x2222
#define mmIA_PERFCOUNTER3_HI__CI__VI                    0xD08F
#define mmIA_PERFCOUNTER3_HI__SI                        0x222B
#define mmIA_PERFCOUNTER3_LO__CI__VI                    0xD08E
#define mmIA_PERFCOUNTER3_LO__SI                        0x222A
#define mmIA_PERFCOUNTER3_SELECT__CI__VI                0xD887
#define mmIA_PERFCOUNTER3_SELECT__SI                    0x2223
#define mmIA_VMID_OVERRIDE__SI__CI                      0x2260
#define mmIH_ADVFAULT_CNTL__SI__CI                      0x0F8C
#define mmIH_PERFCOUNTER0_RESULT__CI                    0x0F8A
#define mmIH_PERFCOUNTER1_RESULT__CI                    0x0F8B
#define mmIH_PERFMON_CNTL__CI                           0x0F89
#define mmIH_VMID_0_LUT__CI                             0x0F50
#define mmIH_VMID_10_LUT__CI                            0x0F5A
#define mmIH_VMID_11_LUT__CI                            0x0F5B
#define mmIH_VMID_12_LUT__CI                            0x0F5C
#define mmIH_VMID_13_LUT__CI                            0x0F5D
#define mmIH_VMID_14_LUT__CI                            0x0F5E
#define mmIH_VMID_15_LUT__CI                            0x0F5F
#define mmIH_VMID_1_LUT__CI                             0x0F51
#define mmIH_VMID_2_LUT__CI                             0x0F52
#define mmIH_VMID_3_LUT__CI                             0x0F53
#define mmIH_VMID_4_LUT__CI                             0x0F54
#define mmIH_VMID_5_LUT__CI                             0x0F55
#define mmIH_VMID_6_LUT__CI                             0x0F56
#define mmIH_VMID_7_LUT__CI                             0x0F57
#define mmIH_VMID_8_LUT__CI                             0x0F58
#define mmIH_VMID_9_LUT__CI                             0x0F59
#define mmIMPCTL_RESET__CI__VI                          0x14F5
#define mmINTERRUPT_CNTL                                0x151A
#define mmINTERRUPT_CNTL2                               0x151B
#define mmINT_MASK__SI                                  0x1AD0
#define mmLB0_DC_MVP_LB_CONTROL__SI                     0x1ADB
#define mmLB0_LB_DEBUG__SI                              0x1AFC
#define mmLB0_LB_SYNC_RESET_SEL__SI                     0x1ACA
#define mmLB0_LB_TEST_DEBUG_DATA__SI__VI                0x1AFF
#define mmLB0_LB_TEST_DEBUG_INDEX__SI__VI               0x1AFE
#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL__SI                0x1AD9
#define mmLB0_MVP_AFR_FLIP_MODE__SI                     0x1AD8
#define mmLB0_MVP_FLIP_LINE_NUM_INSERT__SI              0x1ADA
#define mmLB1_DC_MVP_LB_CONTROL__SI                     0x1DDB
#define mmLB1_LB_DEBUG__SI                              0x1DFC
#define mmLB1_LB_SYNC_RESET_SEL__SI                     0x1DCA
#define mmLB1_LB_TEST_DEBUG_DATA__SI                    0x1DFF
#define mmLB1_LB_TEST_DEBUG_INDEX__SI                   0x1DFE
#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL__SI                0x1DD9
#define mmLB1_MVP_AFR_FLIP_MODE__SI                     0x1DD8
#define mmLB1_MVP_FLIP_LINE_NUM_INSERT__SI              0x1DDA
#define mmLB2_DC_MVP_LB_CONTROL__SI                     0x40DB
#define mmLB2_LB_DEBUG__SI                              0x40FC
#define mmLB2_LB_SYNC_RESET_SEL__SI                     0x40CA
#define mmLB2_LB_TEST_DEBUG_DATA__SI                    0x40FF
#define mmLB2_LB_TEST_DEBUG_INDEX__SI                   0x40FE
#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL__SI                0x40D9
#define mmLB2_MVP_AFR_FLIP_MODE__SI                     0x40D8
#define mmLB2_MVP_FLIP_LINE_NUM_INSERT__SI              0x40DA
#define mmLB3_DC_MVP_LB_CONTROL__SI                     0x43DB
#define mmLB3_LB_DEBUG__SI                              0x43FC
#define mmLB3_LB_SYNC_RESET_SEL__SI                     0x43CA
#define mmLB3_LB_TEST_DEBUG_DATA__SI                    0x43FF
#define mmLB3_LB_TEST_DEBUG_INDEX__SI                   0x43FE
#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL__SI                0x43D9
#define mmLB3_MVP_AFR_FLIP_MODE__SI                     0x43D8
#define mmLB3_MVP_FLIP_LINE_NUM_INSERT__SI              0x43DA
#define mmLB4_DC_MVP_LB_CONTROL__SI                     0x46DB
#define mmLB4_LB_DEBUG__SI                              0x46FC
#define mmLB4_LB_SYNC_RESET_SEL__SI                     0x46CA
#define mmLB4_LB_TEST_DEBUG_DATA__SI                    0x46FF
#define mmLB4_LB_TEST_DEBUG_INDEX__SI                   0x46FE
#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL__SI                0x46D9
#define mmLB4_MVP_AFR_FLIP_MODE__SI                     0x46D8
#define mmLB4_MVP_FLIP_LINE_NUM_INSERT__SI              0x46DA
#define mmLB5_DC_MVP_LB_CONTROL__SI                     0x49DB
#define mmLB5_LB_DEBUG__SI                              0x49FC
#define mmLB5_LB_SYNC_RESET_SEL__SI                     0x49CA
#define mmLB5_LB_TEST_DEBUG_DATA__SI                    0x49FF
#define mmLB5_LB_TEST_DEBUG_INDEX__SI                   0x49FE
#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL__SI                0x49D9
#define mmLB5_MVP_AFR_FLIP_MODE__SI                     0x49D8
#define mmLB5_MVP_FLIP_LINE_NUM_INSERT__SI              0x49DA
#define mmLB_DEBUG__SI                                  0x1AFC
#define mmLB_SYNC_RESET_SEL__SI                         0x1ACA
#define mmLB_TEST_DEBUG_DATA__SI__VI                    0x1AFF
#define mmLB_TEST_DEBUG_INDEX__SI__VI                   0x1AFE
#define mmLNCNT_CONTROL__CI                             0x1487
#define mmLVDS_DATA_CNTL__SI                            0x1C8C
#define mmLVTMA_PWRSEQ_CNTL__SI                         0x1962
#define mmLVTMA_PWRSEQ_DELAY1__SI                       0x1965
#define mmLVTMA_PWRSEQ_DELAY2__SI                       0x1966
#define mmLVTMA_PWRSEQ_REF_DIV__SI                      0x1964
#define mmLVTMA_PWRSEQ_STATE__SI                        0x1963
#define mmMASTER_COMM_CMD_REG__SI__VI                   0x161F
#define mmMASTER_COMM_CNTL_REG__SI__VI                  0x1620
#define mmMASTER_COMM_DATA_REG1__SI__VI                 0x161C
#define mmMASTER_COMM_DATA_REG2__SI__VI                 0x161D
#define mmMASTER_COMM_DATA_REG3__SI__VI                 0x161E
#define mmMASTER_CREDIT_CNTL                            0x1516
#define mmMASTER_UPDATE_LOCK__SI__VI                    0x1BBD
#define mmMASTER_UPDATE_MODE__SI__VI                    0x1BBE
#define mmMCIF_CONTROL__SI                              0x0314
#define mmMCIF_TEST_DEBUG_DATA__SI                      0x0317
#define mmMCIF_TEST_DEBUG_INDEX__SI                     0x0316
#define mmMCIF_WRITE_COMBINE_CONTROL__SI                0x0315
#define mmMCLK_PWRMGT_CNTL__SI__CI                      0x0AE8
#define mmMC_ARB_ADDR_HASH                              0x09DC
#define mmMC_ARB_ADDR_SWIZ0__CI__VI                     0x09CB
#define mmMC_ARB_ADDR_SWIZ1__CI__VI                     0x09CC
#define mmMC_ARB_AGE_CNTL__CI__VI                       0x09BF
#define mmMC_ARB_AGE_RD                                 0x09E9
#define mmMC_ARB_AGE_WR                                 0x09EA
#define mmMC_ARB_BANKMAP                                0x09D7
#define mmMC_ARB_BURST_TIME                             0x0A02
#define mmMC_ARB_BUSY_STATUS__CI__VI                    0x09FD
#define mmMC_ARB_CAC_CNTL                               0x09D4
#define mmMC_ARB_CG                                     0x09FA
#define mmMC_ARB_DRAM_TIMING                            0x09DD
#define mmMC_ARB_DRAM_TIMING2                           0x09DE
#define mmMC_ARB_DRAM_TIMING2_1                         0x09FF
#define mmMC_ARB_DRAM_TIMING_1                          0x09FC
#define mmMC_ARB_FED_CNTL                               0x09C1
#define mmMC_ARB_GDEC_RD_CNTL                           0x09EE
#define mmMC_ARB_GDEC_WR_CNTL                           0x09EF
#define mmMC_ARB_GECC2                                  0x09C9
#define mmMC_ARB_GECC2_CLI                              0x09CA
#define mmMC_ARB_GECC2_DEBUG                            0x09C4
#define mmMC_ARB_GECC2_DEBUG2                           0x09C5
#define mmMC_ARB_GECC2_MISC                             0x09C3
#define mmMC_ARB_GECC2_STATUS                           0x09C2
#define mmMC_ARB_HARSH_BWCNT0_RD__CI__VI                0x0DCE
#define mmMC_ARB_HARSH_BWCNT0_WR__CI__VI                0x0DCF
#define mmMC_ARB_HARSH_BWCNT1_RD__CI__VI                0x0DD0
#define mmMC_ARB_HARSH_BWCNT1_WR__CI__VI                0x0DD1
#define mmMC_ARB_HARSH_BWPERIOD0_RD__CI__VI             0x0DCA
#define mmMC_ARB_HARSH_BWPERIOD0_WR__CI__VI             0x0DCB
#define mmMC_ARB_HARSH_BWPERIOD1_RD__CI__VI             0x0DCC
#define mmMC_ARB_HARSH_BWPERIOD1_WR__CI__VI             0x0DCD
#define mmMC_ARB_HARSH_CTL_RD__CI__VI                   0x0DD6
#define mmMC_ARB_HARSH_CTL_WR__CI__VI                   0x0DD7
#define mmMC_ARB_HARSH_EN_RD__CI__VI                    0x0DC0
#define mmMC_ARB_HARSH_EN_WR__CI__VI                    0x0DC1
#define mmMC_ARB_HARSH_SAT0_RD__CI__VI                  0x0DD2
#define mmMC_ARB_HARSH_SAT0_WR__CI__VI                  0x0DD3
#define mmMC_ARB_HARSH_SAT1_RD__CI__VI                  0x0DD4
#define mmMC_ARB_HARSH_SAT1_WR__CI__VI                  0x0DD5
#define mmMC_ARB_HARSH_TX_HI0_RD__CI__VI                0x0DC2
#define mmMC_ARB_HARSH_TX_HI0_WR__CI__VI                0x0DC3
#define mmMC_ARB_HARSH_TX_HI1_RD__CI__VI                0x0DC4
#define mmMC_ARB_HARSH_TX_HI1_WR__CI__VI                0x0DC5
#define mmMC_ARB_HARSH_TX_LO0_RD__CI__VI                0x0DC6
#define mmMC_ARB_HARSH_TX_LO0_WR__CI__VI                0x0DC7
#define mmMC_ARB_HARSH_TX_LO1_RD__CI__VI                0x0DC8
#define mmMC_ARB_HARSH_TX_LO1_WR__CI__VI                0x0DC9
#define mmMC_ARB_LAZY0_RD                               0x09E5
#define mmMC_ARB_LAZY0_WR                               0x09E6
#define mmMC_ARB_LAZY1_RD                               0x09E7
#define mmMC_ARB_LAZY1_WR                               0x09E8
#define mmMC_ARB_LM_RD                                  0x09F0
#define mmMC_ARB_LM_WR                                  0x09F1
#define mmMC_ARB_MAX_LAT_CID__CI__VI                    0x09F6
#define mmMC_ARB_MAX_LAT_RSLT0__CI__VI                  0x09F7
#define mmMC_ARB_MAX_LAT_RSLT1__CI__VI                  0x09F8
#define mmMC_ARB_MINCLKS                                0x09DA
#define mmMC_ARB_MISC                                   0x09D6
#define mmMC_ARB_MISC2                                  0x09D5
#define mmMC_ARB_MISC3__CI__VI                          0x09CD
#define mmMC_ARB_PERFCOUNTER0_CFG__CI__VI               0x07BC
#define mmMC_ARB_PERFCOUNTER1_CFG__CI__VI               0x07BD
#define mmMC_ARB_PERFCOUNTER2_CFG__CI__VI               0x07BE
#define mmMC_ARB_PERFCOUNTER3_CFG__CI__VI               0x07BF
#define mmMC_ARB_PERFCOUNTER_HI__CI__VI                 0x07AE
#define mmMC_ARB_PERFCOUNTER_LO__CI__VI                 0x07A6
#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI          0x07D4
#define mmMC_ARB_PERF_MON_CNTL0_ECC__CI                 0x07DB
#define mmMC_ARB_PERF_MON_CNTL0__SI                     0x09F6
#define mmMC_ARB_PM_CNTL                                0x09ED
#define mmMC_ARB_POP                                    0x09D9
#define mmMC_ARB_RAMCFG                                 0x09D8
#define mmMC_ARB_REMREQ                                 0x09F2
#define mmMC_ARB_REPLAY                                 0x09F3
#define mmMC_ARB_RET_CREDITS2__CI__VI                   0x09C0
#define mmMC_ARB_RET_CREDITS_RD                         0x09F4
#define mmMC_ARB_RET_CREDITS_WR                         0x09F5
#define mmMC_ARB_RFSH_CNTL                              0x09EB
#define mmMC_ARB_RFSH_RATE                              0x09EC
#define mmMC_ARB_RTT_CNTL0                              0x09D0
#define mmMC_ARB_RTT_CNTL1                              0x09D1
#define mmMC_ARB_RTT_CNTL2                              0x09D2
#define mmMC_ARB_RTT_DATA                               0x09CF
#define mmMC_ARB_RTT_DEBUG                              0x09D3
#define mmMC_ARB_SQM_CNTL                               0x09DB
#define mmMC_ARB_SSM__CI                                0x09F9
#define mmMC_ARB_TM_CNTL_RD                             0x09E3
#define mmMC_ARB_TM_CNTL_WR                             0x09E4
#define mmMC_ARB_WCDR__SI__CI                           0x09FB
#define mmMC_ARB_WCDR_2__SI__CI                         0x09CE
#define mmMC_ARB_WTM_CNTL_RD                            0x09DF
#define mmMC_ARB_WTM_CNTL_WR                            0x09E0
#define mmMC_ARB_WTM_GRPWT_RD                           0x09E1
#define mmMC_ARB_WTM_GRPWT_WR                           0x09E2
#define mmMC_BIST_AUTO_CNTL__SI__CI                     0x0A06
#define mmMC_BIST_CMD_CNTL__SI__CI                      0x0A8E
#define mmMC_BIST_CMP_CNTL__SI__CI                      0x0A8D
#define mmMC_BIST_CMP_CNTL_2__SI__CI                    0x0AB6
#define mmMC_BIST_DATA_MASK__SI__CI                     0x0A12
#define mmMC_BIST_DIR_CNTL__SI__CI                      0x0A07
#define mmMC_BIST_EADDR__SI__CI                         0x0A09
#define mmMC_BIST_RDATA_EDC__SI__CI                     0x0A1D
#define mmMC_BIST_RDATA_MASK__SI__CI                    0x0A1C
#define mmMC_BIST_SADDR__SI__CI                         0x0A08
#define mmMC_CG_CONFIG                                  0x096F
#define mmMC_CG_CONFIG_MCD                              0x0829
#define mmMC_CITF_CNTL                                  0x0970
#define mmMC_CITF_CREDITS_ARB_RD                        0x0972
#define mmMC_CITF_CREDITS_ARB_WR                        0x0973
#define mmMC_CITF_CREDITS_VM                            0x0971
#define mmMC_CITF_CREDITS_XBAR                          0x0989
#define mmMC_CITF_DAGB_CNTL                             0x0974
#define mmMC_CITF_DAGB_DLY                              0x0977
#define mmMC_CITF_INT_CREDITS                           0x0975
#define mmMC_CITF_INT_CREDITS_WR__CI__VI                0x097D
#define mmMC_CITF_MISC_RD_CG                            0x0992
#define mmMC_CITF_MISC_VM_CG                            0x0994
#define mmMC_CITF_MISC_WR_CG                            0x0993
#define mmMC_CITF_PERFCOUNTER0_CFG__CI__VI              0x07B0
#define mmMC_CITF_PERFCOUNTER1_CFG__CI__VI              0x07B1
#define mmMC_CITF_PERFCOUNTER2_CFG__CI__VI              0x07B2
#define mmMC_CITF_PERFCOUNTER3_CFG__CI__VI              0x07B3
#define mmMC_CITF_PERFCOUNTER_HI__CI__VI                0x07A8
#define mmMC_CITF_PERFCOUNTER_LO__CI__VI                0x07A0
#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI         0x07CE
#define mmMC_CITF_PERF_MON_CNTL2                        0x098E
#define mmMC_CITF_PERF_MON_RSLT2                        0x0991
#define mmMC_CITF_REMREQ                                0x097A
#define mmMC_CITF_RET_MODE                              0x0976
#define mmMC_CITF_WTM_RD_CNTL                           0x097F
#define mmMC_CITF_WTM_WR_CNTL                           0x0980
#define mmMC_CITF_XTRA_ENABLE                           0x096D
#define mmMC_CONFIG                                     0x0800
#define mmMC_CONFIG_MCD                                 0x0828
#define mmMC_DC_INTERFACE_NACK_STATUS__SI               0x031C
#define mmMC_DLB_CONFIG0__CI                            0x0D93
#define mmMC_DLB_CONFIG1__CI                            0x0D94
#define mmMC_DLB_MISCCTRL0__CI                          0x0D90
#define mmMC_DLB_MISCCTRL1__CI                          0x0D91
#define mmMC_DLB_MISCCTRL2__CI                          0x0D92
#define mmMC_DLB_SETUPFIFO__CI                          0x0D97
#define mmMC_DLB_SETUPSWEEP__CI                         0x0D96
#define mmMC_DLB_SETUP__CI                              0x0D95
#define mmMC_DLB_STATUS_MISC0__CI                       0x0D9A
#define mmMC_DLB_STATUS_MISC1__CI                       0x0D9B
#define mmMC_DLB_STATUS_MISC2__CI                       0x0D9C
#define mmMC_DLB_STATUS_MISC3__CI                       0x0D9D
#define mmMC_DLB_STATUS_MISC4__CI                       0x0D9E
#define mmMC_DLB_STATUS_MISC5__CI                       0x0D9F
#define mmMC_DLB_STATUS_MISC6__CI                       0x0DA0
#define mmMC_DLB_STATUS_MISC7__CI                       0x0DA1
#define mmMC_DLB_STATUS__CI                             0x0D99
#define mmMC_DLB_WRITE_MASK__CI                         0x0D98
#define mmMC_HUB_MISC_DBG__SI__CI                       0x0831
#define mmMC_HUB_MISC_FRAMING                           0x0834
#define mmMC_HUB_MISC_HUB_CG                            0x082E
#define mmMC_HUB_MISC_IDLE_STATUS                       0x0847
#define mmMC_HUB_MISC_OVERRIDE                          0x0833
#define mmMC_HUB_MISC_POWER                             0x082D
#define mmMC_HUB_MISC_SIP_CG                            0x0830
#define mmMC_HUB_MISC_STATUS                            0x0832
#define mmMC_HUB_MISC_VM_CG                             0x082F
#define mmMC_HUB_PERFCOUNTER0_CFG__CI__VI               0x07B4
#define mmMC_HUB_PERFCOUNTER1_CFG__CI__VI               0x07B5
#define mmMC_HUB_PERFCOUNTER2_CFG__CI__VI               0x07B6
#define mmMC_HUB_PERFCOUNTER3_CFG__CI__VI               0x07B7
#define mmMC_HUB_PERFCOUNTER_HI__CI__VI                 0x07A9
#define mmMC_HUB_PERFCOUNTER_LO__CI__VI                 0x07A1
#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI          0x07CF
#define mmMC_HUB_RDREQ_ACPG_LIMIT__CI__VI               0x0849
#define mmMC_HUB_RDREQ_ACPG__CI                         0x0887
#define mmMC_HUB_RDREQ_ACPO__CI                         0x0888
#define mmMC_HUB_RDREQ_CNTL                             0x083B
#define mmMC_HUB_RDREQ_CPC__CI                          0x085A
#define mmMC_HUB_RDREQ_CPF__CI                          0x085B
#define mmMC_HUB_RDREQ_CPG__CI                          0x0859
#define mmMC_HUB_RDREQ_CP__SI                           0x0859
#define mmMC_HUB_RDREQ_CREDITS                          0x0844
#define mmMC_HUB_RDREQ_CREDITS2                         0x0845
#define mmMC_HUB_RDREQ_DMIF_LIMIT                       0x0848
#define mmMC_HUB_RDREQ_DMIF__CI                         0x0865
#define mmMC_HUB_RDREQ_DMIF__SI                         0x0863
#define mmMC_HUB_RDREQ_GBL0                             0x0856
#define mmMC_HUB_RDREQ_GBL1                             0x0857
#define mmMC_HUB_RDREQ_HDP__CI                          0x085E
#define mmMC_HUB_RDREQ_HDP__SI                          0x085B
#define mmMC_HUB_RDREQ_IA0__CI                          0x084F
#define mmMC_HUB_RDREQ_IA1__CI                          0x0850
#define mmMC_HUB_RDREQ_IA__CI                           0x0864
#define mmMC_HUB_RDREQ_MCDW                             0x0851
#define mmMC_HUB_RDREQ_MCDX                             0x0852
#define mmMC_HUB_RDREQ_MCDY                             0x0853
#define mmMC_HUB_RDREQ_MCDZ                             0x0854
#define mmMC_HUB_RDREQ_MCIF__CI                         0x0866
#define mmMC_HUB_RDREQ_MCIF__SI                         0x0864
#define mmMC_HUB_RDREQ_RLC__CI                          0x085F
#define mmMC_HUB_RDREQ_RLC__SI                          0x085D
#define mmMC_HUB_RDREQ_SAM__CI                          0x0889
#define mmMC_HUB_RDREQ_SDMA0__CI                        0x085C
#define mmMC_HUB_RDREQ_SDMA1__CI                        0x085D
#define mmMC_HUB_RDREQ_SEM__CI                          0x0860
#define mmMC_HUB_RDREQ_SEM__SI                          0x085E
#define mmMC_HUB_RDREQ_SIP                              0x0855
#define mmMC_HUB_RDREQ_SMU                              0x0858
#define mmMC_HUB_RDREQ_STATUS                           0x0839
#define mmMC_HUB_RDREQ_UMC__CI                          0x0862
#define mmMC_HUB_RDREQ_UMC__SI                          0x0860
#define mmMC_HUB_RDREQ_UVD__CI                          0x0863
#define mmMC_HUB_RDREQ_UVD__SI                          0x0861
#define mmMC_HUB_RDREQ_VCEU__CI                         0x0868
#define mmMC_HUB_RDREQ_VCEU__SI                         0x0866
#define mmMC_HUB_RDREQ_VCE__CI                          0x0861
#define mmMC_HUB_RDREQ_VCE__SI                          0x085F
#define mmMC_HUB_RDREQ_VMC__CI                          0x0867
#define mmMC_HUB_RDREQ_VMC__SI                          0x0865
#define mmMC_HUB_RDREQ_WTM_CNTL                         0x083D
#define mmMC_HUB_RDREQ_XDMAM__CI                        0x0886
#define mmMC_HUB_RDREQ_XDMAM__SI                        0x0882
#define mmMC_HUB_SHARED_DAGB_DLY                        0x0846
#define mmMC_HUB_WDP_ACPG__CI                           0x088A
#define mmMC_HUB_WDP_ACPO__CI                           0x088B
#define mmMC_HUB_WDP_BP                                 0x0837
#define mmMC_HUB_WDP_CNTL                               0x0835
#define mmMC_HUB_WDP_CPC__CI                            0x086F
#define mmMC_HUB_WDP_CPF__CI                            0x0870
#define mmMC_HUB_WDP_CPG__CI                            0x086E
#define mmMC_HUB_WDP_CP__SI                             0x086C
#define mmMC_HUB_WDP_CREDITS                            0x083F
#define mmMC_HUB_WDP_ERR                                0x0836
#define mmMC_HUB_WDP_GBL0                               0x0841
#define mmMC_HUB_WDP_GBL1                               0x0842
#define mmMC_HUB_WDP_HDP__CI                            0x087C
#define mmMC_HUB_WDP_HDP__SI                            0x0879
#define mmMC_HUB_WDP_IH__CI                             0x0875
#define mmMC_HUB_WDP_IH__SI                             0x0872
#define mmMC_HUB_WDP_MCDW__CI                           0x0869
#define mmMC_HUB_WDP_MCDW__SI                           0x0867
#define mmMC_HUB_WDP_MCDX__CI                           0x086A
#define mmMC_HUB_WDP_MCDX__SI                           0x0868
#define mmMC_HUB_WDP_MCDY__CI                           0x086B
#define mmMC_HUB_WDP_MCDY__SI                           0x0869
#define mmMC_HUB_WDP_MCDZ__CI                           0x086C
#define mmMC_HUB_WDP_MCDZ__SI                           0x086A
#define mmMC_HUB_WDP_MCIF__CI                           0x0872
#define mmMC_HUB_WDP_MCIF__SI                           0x086F
#define mmMC_HUB_WDP_MGPU__SI__CI                       0x0843
#define mmMC_HUB_WDP_MGPU2__SI__CI                      0x0840
#define mmMC_HUB_WDP_RLC__CI                            0x0876
#define mmMC_HUB_WDP_RLC__SI                            0x0873
#define mmMC_HUB_WDP_SAM__CI                            0x088C
#define mmMC_HUB_WDP_SDMA0__CI                          0x087D
#define mmMC_HUB_WDP_SDMA1__CI                          0x087E
#define mmMC_HUB_WDP_SEM__CI                            0x0877
#define mmMC_HUB_WDP_SEM__SI                            0x0874
#define mmMC_HUB_WDP_SH0__CI                            0x0871
#define mmMC_HUB_WDP_SH0__SI                            0x086E
#define mmMC_HUB_WDP_SH1__CI                            0x0879
#define mmMC_HUB_WDP_SH1__SI                            0x0876
#define mmMC_HUB_WDP_SH2__CI__VI                        0x084D
#define mmMC_HUB_WDP_SH3__CI__VI                        0x084E
#define mmMC_HUB_WDP_SIP__CI                            0x086D
#define mmMC_HUB_WDP_SIP__SI                            0x086B
#define mmMC_HUB_WDP_SMU__CI                            0x0878
#define mmMC_HUB_WDP_SMU__SI                            0x0875
#define mmMC_HUB_WDP_STATUS                             0x0838
#define mmMC_HUB_WDP_UMC__CI                            0x087A
#define mmMC_HUB_WDP_UMC__SI                            0x0877
#define mmMC_HUB_WDP_UVD__CI                            0x087B
#define mmMC_HUB_WDP_UVD__SI                            0x0878
#define mmMC_HUB_WDP_VCEU__CI                           0x0883
#define mmMC_HUB_WDP_VCEU__SI                           0x087F
#define mmMC_HUB_WDP_VCE__CI                            0x0873
#define mmMC_HUB_WDP_VCE__SI                            0x0870
#define mmMC_HUB_WDP_WTM_CNTL                           0x083E
#define mmMC_HUB_WDP_XDMAM__CI                          0x0884
#define mmMC_HUB_WDP_XDMAM__SI                          0x0880
#define mmMC_HUB_WDP_XDMA__CI                           0x0885
#define mmMC_HUB_WDP_XDMA__SI                           0x0881
#define mmMC_HUB_WDP_XDP__CI                            0x0874
#define mmMC_HUB_WDP_XDP__SI                            0x0871
#define mmMC_HUB_WRRET_CNTL                             0x083C
#define mmMC_HUB_WRRET_MCDW__CI                         0x087F
#define mmMC_HUB_WRRET_MCDW__SI                         0x087B
#define mmMC_HUB_WRRET_MCDX__CI                         0x0880
#define mmMC_HUB_WRRET_MCDX__SI                         0x087C
#define mmMC_HUB_WRRET_MCDY__CI                         0x0881
#define mmMC_HUB_WRRET_MCDY__SI                         0x087D
#define mmMC_HUB_WRRET_MCDZ__CI                         0x0882
#define mmMC_HUB_WRRET_MCDZ__SI                         0x087E
#define mmMC_HUB_WRRET_STATUS                           0x083A
#define mmMC_IMP_CNTL__SI__CI                           0x0A36
#define mmMC_IMP_DEBUG__SI__CI                          0x0A37
#define mmMC_IMP_DQ_STATUS__SI__CI                      0x0ABC
#define mmMC_IMP_STATUS__SI__CI                         0x0A38
#define mmMC_IO_APHY_STR_CNTL_D0__SI__CI                0x0A97
#define mmMC_IO_APHY_STR_CNTL_D1__SI__CI                0x0A98
#define mmMC_IO_CDRCNTL1_D0__SI__CI                     0x0ADD
#define mmMC_IO_CDRCNTL1_D1__SI__CI                     0x0ADE
#define mmMC_IO_CDRCNTL2_D0__SI__CI                     0x0AE4
#define mmMC_IO_CDRCNTL2_D1__SI__CI                     0x0AE5
#define mmMC_IO_CDRCNTL_D0__SI__CI                      0x0A55
#define mmMC_IO_CDRCNTL_D1__SI__CI                      0x0A56
#define mmMC_IO_DPHY_STR_CNTL_D0__SI__CI                0x0A4E
#define mmMC_IO_DPHY_STR_CNTL_D1__SI__CI                0x0A54
#define mmMC_IO_PAD_CNTL__SI__CI                        0x0A73
#define mmMC_IO_PAD_CNTL_D0__SI__CI                     0x0A74
#define mmMC_IO_PAD_CNTL_D1__SI__CI                     0x0A75
#define mmMC_IO_RXCNTL1_DPHY0_D0__SI__CI                0x0ADF
#define mmMC_IO_RXCNTL1_DPHY0_D1__SI__CI                0x0AE1
#define mmMC_IO_RXCNTL1_DPHY1_D0__SI__CI                0x0AE0
#define mmMC_IO_RXCNTL1_DPHY1_D1__SI__CI                0x0AE2
#define mmMC_IO_RXCNTL_DPHY0_D0__SI__CI                 0x0A4C
#define mmMC_IO_RXCNTL_DPHY0_D1__SI__CI                 0x0A52
#define mmMC_IO_RXCNTL_DPHY1_D0__SI__CI                 0x0A4D
#define mmMC_IO_RXCNTL_DPHY1_D1__SI__CI                 0x0A53
#define mmMC_IO_TXCNTL_APHY_D0__SI__CI                  0x0A4B
#define mmMC_IO_TXCNTL_APHY_D1__SI__CI                  0x0A51
#define mmMC_IO_TXCNTL_DPHY0_D0__SI__CI                 0x0A49
#define mmMC_IO_TXCNTL_DPHY0_D1__SI__CI                 0x0A4F
#define mmMC_IO_TXCNTL_DPHY1_D0__SI__CI                 0x0A4A
#define mmMC_IO_TXCNTL_DPHY1_D1__SI__CI                 0x0A50
#define mmMC_MCBVM_PERFCOUNTER0_CFG__CI__VI             0x07C0
#define mmMC_MCBVM_PERFCOUNTER1_CFG__CI__VI             0x07C1
#define mmMC_MCBVM_PERFCOUNTER2_CFG__CI__VI             0x07C2
#define mmMC_MCBVM_PERFCOUNTER3_CFG__CI__VI             0x07C3
#define mmMC_MCBVM_PERFCOUNTER_HI__CI__VI               0x07AA
#define mmMC_MCBVM_PERFCOUNTER_LO__CI__VI               0x07A3
#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI        0x07D1
#define mmMC_MCDVM_PERFCOUNTER0_CFG__CI__VI             0x07C4
#define mmMC_MCDVM_PERFCOUNTER1_CFG__CI__VI             0x07C5
#define mmMC_MCDVM_PERFCOUNTER2_CFG__CI__VI             0x07C6
#define mmMC_MCDVM_PERFCOUNTER3_CFG__CI__VI             0x07C7
#define mmMC_MCDVM_PERFCOUNTER_HI__CI__VI               0x07AB
#define mmMC_MCDVM_PERFCOUNTER_LO__CI__VI               0x07A4
#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI        0x07D2
#define mmMC_MEM_POWER_LS                               0x082A
#define mmMC_NPL_STATUS__SI__CI                         0x0A76
#define mmMC_PHY_TIMING_2__SI__CI                       0x0ACE
#define mmMC_PHY_TIMING_D0__SI__CI                      0x0ACC
#define mmMC_PHY_TIMING_D1__SI__CI                      0x0ACD
#define mmMC_PMG_AUTO_CFG__SI__CI                       0x0A35
#define mmMC_PMG_AUTO_CMD__SI__CI                       0x0A34
#define mmMC_RD_CB                                      0x0981
#define mmMC_RD_DB                                      0x0982
#define mmMC_RD_GRP_EXT                                 0x0978
#define mmMC_RD_GRP_GFX                                 0x0803
#define mmMC_RD_GRP_LCL                                 0x098A
#define mmMC_RD_GRP_OTH                                 0x0807
#define mmMC_RD_GRP_SYS                                 0x0805
#define mmMC_RD_HUB                                     0x0985
#define mmMC_RD_TC0                                     0x0983
#define mmMC_RD_TC1                                     0x0984
#define mmMC_RPB_ARB_CNTL                               0x0951
#define mmMC_RPB_BIF_CNTL                               0x0952
#define mmMC_RPB_CID_QUEUE_EX                           0x095A
#define mmMC_RPB_CID_QUEUE_EX_DATA                      0x095B
#define mmMC_RPB_CID_QUEUE_RD                           0x0957
#define mmMC_RPB_CID_QUEUE_WR                           0x0956
#define mmMC_RPB_CONF                                   0x094D
#define mmMC_RPB_DBG1                                   0x094F
#define mmMC_RPB_EFF_CNTL                               0x0950
#define mmMC_RPB_IF_CONF                                0x094E
#define mmMC_RPB_PERFCOUNTER0_CFG__CI__VI               0x07B8
#define mmMC_RPB_PERFCOUNTER1_CFG__CI__VI               0x07B9
#define mmMC_RPB_PERFCOUNTER2_CFG__CI__VI               0x07BA
#define mmMC_RPB_PERFCOUNTER3_CFG__CI__VI               0x07BB
#define mmMC_RPB_PERFCOUNTER_HI__CI__VI                 0x07AC
#define mmMC_RPB_PERFCOUNTER_LO__CI__VI                 0x07A2
#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI          0x07D0
#define mmMC_RPB_PERF_COUNTER_CNTL                      0x0958
#define mmMC_RPB_PERF_COUNTER_STATUS                    0x0959
#define mmMC_RPB_RD_SWITCH_CNTL                         0x0955
#define mmMC_RPB_WR_COMBINE_CNTL                        0x0954
#define mmMC_RPB_WR_SWITCH_CNTL                         0x0953
#define mmMC_SEQ_BIT_REMAP_B0_D0__SI__CI                0x0AA3
#define mmMC_SEQ_BIT_REMAP_B0_D1__SI__CI                0x0AA7
#define mmMC_SEQ_BIT_REMAP_B1_D0__SI__CI                0x0AA4
#define mmMC_SEQ_BIT_REMAP_B1_D1__SI__CI                0x0AA8
#define mmMC_SEQ_BIT_REMAP_B2_D0__SI__CI                0x0AA5
#define mmMC_SEQ_BIT_REMAP_B2_D1__SI__CI                0x0AA9
#define mmMC_SEQ_BIT_REMAP_B3_D0__SI__CI                0x0AA6
#define mmMC_SEQ_BIT_REMAP_B3_D1__SI__CI                0x0AAA
#define mmMC_SEQ_BYTE_REMAP_D0__SI__CI                  0x0A93
#define mmMC_SEQ_BYTE_REMAP_D1__SI__CI                  0x0A94
#define mmMC_SEQ_CNTL_3__CI                             0x0D80
#define mmMC_SEQ_DLL_STBY_LP__CI                        0x0D8F
#define mmMC_SEQ_DLL_STBY__CI                           0x0D8E
#define mmMC_SEQ_DRAM_ERROR_INSERTION__SI__CI           0x0ACB
#define mmMC_SEQ_G5PDX_CMD0_LP__CI                      0x0D84
#define mmMC_SEQ_G5PDX_CMD0__CI                         0x0D83
#define mmMC_SEQ_G5PDX_CMD1_LP__CI                      0x0D86
#define mmMC_SEQ_G5PDX_CMD1__CI                         0x0D85
#define mmMC_SEQ_G5PDX_CTRL_LP__CI                      0x0D82
#define mmMC_SEQ_G5PDX_CTRL__CI                         0x0D81
#define mmMC_SEQ_IO_RDBI__SI__CI                        0x0AB4
#define mmMC_SEQ_IO_REDC__SI__CI                        0x0AB5
#define mmMC_SEQ_IO_RESERVE_D0__SI__CI                  0x0AB7
#define mmMC_SEQ_IO_RESERVE_D1__SI__CI                  0x0AB8
#define mmMC_SEQ_IO_RWORD0__SI__CI                      0x0AAC
#define mmMC_SEQ_IO_RWORD1__SI__CI                      0x0AAD
#define mmMC_SEQ_IO_RWORD2__SI__CI                      0x0AAE
#define mmMC_SEQ_IO_RWORD3__SI__CI                      0x0AAF
#define mmMC_SEQ_IO_RWORD4__SI__CI                      0x0AB0
#define mmMC_SEQ_IO_RWORD5__SI__CI                      0x0AB1
#define mmMC_SEQ_IO_RWORD6__SI__CI                      0x0AB2
#define mmMC_SEQ_IO_RWORD7__SI__CI                      0x0AB3
#define mmMC_SEQ_MPLL_OVERRIDE__SI__CI                  0x0A22
#define mmMC_SEQ_PERF_CNTL__SI__CI                      0x0A77
#define mmMC_SEQ_PERF_CNTL_1__SI__CI                    0x0AFD
#define mmMC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI              0x0A79
#define mmMC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI              0x0A7A
#define mmMC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI              0x0A7B
#define mmMC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI              0x0A7C
#define mmMC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI              0x0AD9
#define mmMC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI              0x0ADA
#define mmMC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI              0x0ADB
#define mmMC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI              0x0ADC
#define mmMC_SEQ_PERF_SEQ_CTL__SI__CI                   0x0A78
#define mmMC_SEQ_PHYREG_BCAST__CI                       0x0D89
#define mmMC_SEQ_PMG_CMD_EMRS_LP__SI__CI                0x0AA1
#define mmMC_SEQ_PMG_CMD_MRS1_LP__SI__CI                0x0AD2
#define mmMC_SEQ_PMG_CMD_MRS2_LP__SI__CI                0x0AD8
#define mmMC_SEQ_PMG_CMD_MRS_LP__SI__CI                 0x0AA2
#define mmMC_SEQ_PMG_DVS_CMD_LP__CI                     0x0D8D
#define mmMC_SEQ_PMG_DVS_CMD__CI                        0x0D8C
#define mmMC_SEQ_PMG_DVS_CTL_LP__CI                     0x0D8B
#define mmMC_SEQ_PMG_DVS_CTL__CI                        0x0D8A
#define mmMC_SEQ_PMG_PG_HWCNTL__SI__CI                  0x0AB9
#define mmMC_SEQ_PMG_PG_SWCNTL_0__SI__CI                0x0ABA
#define mmMC_SEQ_PMG_PG_SWCNTL_1__SI__CI                0x0ABB
#define mmMC_SEQ_RXFRAMING_BYTE0_D0__SI__CI             0x0A67
#define mmMC_SEQ_RXFRAMING_BYTE0_D1__SI__CI             0x0A6D
#define mmMC_SEQ_RXFRAMING_BYTE1_D0__SI__CI             0x0A68
#define mmMC_SEQ_RXFRAMING_BYTE1_D1__SI__CI             0x0A6E
#define mmMC_SEQ_RXFRAMING_BYTE2_D0__SI__CI             0x0A69
#define mmMC_SEQ_RXFRAMING_BYTE2_D1__SI__CI             0x0A6F
#define mmMC_SEQ_RXFRAMING_BYTE3_D0__SI__CI             0x0A6A
#define mmMC_SEQ_RXFRAMING_BYTE3_D1__SI__CI             0x0A70
#define mmMC_SEQ_RXFRAMING_DBI_D0__SI__CI               0x0A6B
#define mmMC_SEQ_RXFRAMING_DBI_D1__SI__CI               0x0A71
#define mmMC_SEQ_RXFRAMING_EDC_D0__SI__CI               0x0A6C
#define mmMC_SEQ_RXFRAMING_EDC_D1__SI__CI               0x0A72
#define mmMC_SEQ_SREG_READ__CI                          0x0D87
#define mmMC_SEQ_SREG_STATUS__CI                        0x0D88
#define mmMC_SEQ_TCG_CNTL__SI__CI                       0x0ABD
#define mmMC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI            0x0A3B
#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI           0x0AFE
#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI           0x0AFF
#define mmMC_SEQ_TRAIN_TIMING__SI__CI                   0x0A40
#define mmMC_SEQ_TSM_BCNT__SI__CI                       0x0AC2
#define mmMC_SEQ_TSM_CTRL__SI__CI                       0x0ABE
#define mmMC_SEQ_TSM_DBI__SI__CI                        0x0AC6
#define mmMC_SEQ_TSM_DEBUG_DATA__SI__CI                 0x0AD0
#define mmMC_SEQ_TSM_DEBUG_INDEX__SI__CI                0x0ACF
#define mmMC_SEQ_TSM_EDC__SI__CI                        0x0AC5
#define mmMC_SEQ_TSM_FLAG__SI__CI                       0x0AC3
#define mmMC_SEQ_TSM_GCNT__SI__CI                       0x0ABF
#define mmMC_SEQ_TSM_MISC__SI__CI                       0x0AE6
#define mmMC_SEQ_TSM_NCNT__SI__CI                       0x0AC1
#define mmMC_SEQ_TSM_OCNT__SI__CI                       0x0AC0
#define mmMC_SEQ_TSM_UPDATE__SI__CI                     0x0AC4
#define mmMC_SEQ_TSM_WCDR__SI__CI                       0x0AE3
#define mmMC_SEQ_TXFRAMING_BYTE0_D0__SI__CI             0x0A58
#define mmMC_SEQ_TXFRAMING_BYTE0_D1__SI__CI             0x0A60
#define mmMC_SEQ_TXFRAMING_BYTE1_D0__SI__CI             0x0A59
#define mmMC_SEQ_TXFRAMING_BYTE1_D1__SI__CI             0x0A61
#define mmMC_SEQ_TXFRAMING_BYTE2_D0__SI__CI             0x0A5A
#define mmMC_SEQ_TXFRAMING_BYTE2_D1__SI__CI             0x0A62
#define mmMC_SEQ_TXFRAMING_BYTE3_D0__SI__CI             0x0A5B
#define mmMC_SEQ_TXFRAMING_BYTE3_D1__SI__CI             0x0A63
#define mmMC_SEQ_TXFRAMING_DBI_D0__SI__CI               0x0A5C
#define mmMC_SEQ_TXFRAMING_DBI_D1__SI__CI               0x0A64
#define mmMC_SEQ_TXFRAMING_EDC_D0__SI__CI               0x0A5D
#define mmMC_SEQ_TXFRAMING_EDC_D1__SI__CI               0x0A65
#define mmMC_SEQ_TXFRAMING_FCK_D0__SI__CI               0x0A5E
#define mmMC_SEQ_TXFRAMING_FCK_D1__SI__CI               0x0A66
#define mmMC_SEQ_VENDOR_ID_I0__SI__CI                   0x0A7E
#define mmMC_SEQ_VENDOR_ID_I1__SI__CI                   0x0A7F
#define mmMC_SEQ_WCDR_CTRL__SI__CI                      0x0A39
#define mmMC_SEQ_WR_CTL_2__SI__CI                       0x0AD5
#define mmMC_SEQ_WR_CTL_2_LP__SI__CI                    0x0AD6
#define mmMC_SHARED_BLACKOUT_CNTL                       0x082B
#define mmMC_SHARED_CHMAP                               0x0801
#define mmMC_SHARED_CHREMAP                             0x0802
#define mmMC_TRAIN_EDCCDR_R_D0__SI__CI                  0x0A41
#define mmMC_TRAIN_EDCCDR_R_D1__SI__CI                  0x0A42
#define mmMC_TRAIN_EDC_STATUS_D0__SI__CI                0x0A45
#define mmMC_TRAIN_EDC_STATUS_D1__SI__CI                0x0A48
#define mmMC_TRAIN_PRBSERR_0_D0__SI__CI                 0x0A43
#define mmMC_TRAIN_PRBSERR_0_D1__SI__CI                 0x0A46
#define mmMC_TRAIN_PRBSERR_1_D0__SI__CI                 0x0A44
#define mmMC_TRAIN_PRBSERR_1_D1__SI__CI                 0x0A47
#define mmMC_TRAIN_PRBSERR_2_D0__SI__CI                 0x0AFB
#define mmMC_TRAIN_PRBSERR_2_D1__SI__CI                 0x0AFC
#define mmMC_VM_AGP_BASE                                0x080C
#define mmMC_VM_AGP_BOT                                 0x080B
#define mmMC_VM_AGP_TOP                                 0x080A
#define mmMC_VM_DC_WRITE_CNTL                           0x0810
#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR         0x0815
#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR          0x0811
#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR         0x0816
#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR          0x0812
#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR         0x0817
#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR          0x0813
#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR         0x0818
#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR          0x0814
#define mmMC_VM_FB_LOCATION                             0x0809
#define mmMC_VM_FB_OFFSET                               0x081A
#define mmMC_VM_L2_PERFCOUNTER0_CFG__CI__VI             0x07CC
#define mmMC_VM_L2_PERFCOUNTER1_CFG__CI__VI             0x07CD
#define mmMC_VM_L2_PERFCOUNTER_HI__CI__VI               0x07AD
#define mmMC_VM_L2_PERFCOUNTER_LO__CI__VI               0x07A5
#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI        0x07D3
#define mmMC_VM_MB_L1_TLB0_DEBUG                        0x0891
#define mmMC_VM_MB_L1_TLB0_STATUS                       0x0895
#define mmMC_VM_MB_L1_TLB1_STATUS                       0x0896
#define mmMC_VM_MB_L1_TLB2_DEBUG                        0x0893
#define mmMC_VM_MB_L1_TLB2_STATUS                       0x0897
#define mmMC_VM_MB_L1_TLB3_DEBUG                        0x08A5
#define mmMC_VM_MB_L1_TLB3_STATUS                       0x08A6
#define mmMC_VM_MB_L2ARBITER_L2_CREDITS                 0x08A1
#define mmMC_VM_MD_L1_TLB0_DEBUG                        0x0998
#define mmMC_VM_MD_L1_TLB0_STATUS                       0x099B
#define mmMC_VM_MD_L1_TLB1_DEBUG                        0x0999
#define mmMC_VM_MD_L1_TLB1_STATUS                       0x099C
#define mmMC_VM_MD_L1_TLB2_DEBUG                        0x099A
#define mmMC_VM_MD_L1_TLB2_STATUS                       0x099D
#define mmMC_VM_MD_L1_TLB3_DEBUG                        0x09A7
#define mmMC_VM_MD_L1_TLB3_STATUS                       0x09A8
#define mmMC_VM_MD_L2ARBITER_L2_CREDITS                 0x09A4
#define mmMC_VM_MX_L1_TLB_CNTL                          0x0819
#define mmMC_VM_STEERING__CI__VI                        0x081B
#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR            0x080F
#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR               0x080E
#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR                0x080D
#define mmMC_WR_CB                                      0x0986
#define mmMC_WR_DB                                      0x0987
#define mmMC_WR_GRP_EXT                                 0x0979
#define mmMC_WR_GRP_GFX                                 0x0804
#define mmMC_WR_GRP_LCL                                 0x098B
#define mmMC_WR_GRP_OTH                                 0x0808
#define mmMC_WR_GRP_SYS                                 0x0806
#define mmMC_WR_HUB                                     0x0988
#define mmMC_WR_TC0                                     0x097B
#define mmMC_WR_TC1                                     0x097C
#define mmMC_XBAR_ADDR_DEC                              0x0C80
#define mmMC_XBAR_ARB                                   0x0C8D
#define mmMC_XBAR_ARB_MAX_BURST                         0x0C8E
#define mmMC_XBAR_CHTRIREMAP                            0x0C8B
#define mmMC_XBAR_PERF_MON_CNTL0__SI__CI                0x0C8F
#define mmMC_XBAR_PERF_MON_CNTL1__SI__CI                0x0C90
#define mmMC_XBAR_PERF_MON_CNTL2__SI__CI                0x0C91
#define mmMC_XBAR_PERF_MON_MAX_THSH__SI__CI             0x0C96
#define mmMC_XBAR_PERF_MON_RSLT0__SI__CI                0x0C92
#define mmMC_XBAR_PERF_MON_RSLT1__SI__CI                0x0C93
#define mmMC_XBAR_PERF_MON_RSLT2__SI__CI                0x0C94
#define mmMC_XBAR_PERF_MON_RSLT3__SI__CI                0x0C95
#define mmMC_XBAR_RDREQ_CREDIT                          0x0C83
#define mmMC_XBAR_RDREQ_PRI_CREDIT                      0x0C84
#define mmMC_XBAR_RDRET_CREDIT1                         0x0C87
#define mmMC_XBAR_RDRET_CREDIT2                         0x0C88
#define mmMC_XBAR_RDRET_PRI_CREDIT1                     0x0C89
#define mmMC_XBAR_RDRET_PRI_CREDIT2                     0x0C8A
#define mmMC_XBAR_REMOTE                                0x0C81
#define mmMC_XBAR_SPARE0                                0x0C97
#define mmMC_XBAR_SPARE1                                0x0C98
#define mmMC_XBAR_TWOCHAN                               0x0C8C
#define mmMC_XBAR_WRREQ_CREDIT                          0x0C82
#define mmMC_XBAR_WRRET_CREDIT1                         0x0C85
#define mmMC_XBAR_WRRET_CREDIT2                         0x0C86
#define mmMC_XPB_CLG_CFG0                               0x08E9
#define mmMC_XPB_CLG_CFG1                               0x08EA
#define mmMC_XPB_CLG_CFG10                              0x08F3
#define mmMC_XPB_CLG_CFG11                              0x08F4
#define mmMC_XPB_CLG_CFG12                              0x08F5
#define mmMC_XPB_CLG_CFG13                              0x08F6
#define mmMC_XPB_CLG_CFG14                              0x08F7
#define mmMC_XPB_CLG_CFG15                              0x08F8
#define mmMC_XPB_CLG_CFG16                              0x08F9
#define mmMC_XPB_CLG_CFG17                              0x08FA
#define mmMC_XPB_CLG_CFG18                              0x08FB
#define mmMC_XPB_CLG_CFG19                              0x08FC
#define mmMC_XPB_CLG_CFG2                               0x08EB
#define mmMC_XPB_CLG_CFG20                              0x0928
#define mmMC_XPB_CLG_CFG21                              0x0929
#define mmMC_XPB_CLG_CFG22                              0x092A
#define mmMC_XPB_CLG_CFG23                              0x092B
#define mmMC_XPB_CLG_CFG24                              0x092C
#define mmMC_XPB_CLG_CFG25                              0x092D
#define mmMC_XPB_CLG_CFG26                              0x092E
#define mmMC_XPB_CLG_CFG27                              0x092F
#define mmMC_XPB_CLG_CFG28                              0x0930
#define mmMC_XPB_CLG_CFG29                              0x0931
#define mmMC_XPB_CLG_CFG3                               0x08EC
#define mmMC_XPB_CLG_CFG30                              0x0932
#define mmMC_XPB_CLG_CFG31                              0x0933
#define mmMC_XPB_CLG_CFG32                              0x0936
#define mmMC_XPB_CLG_CFG33                              0x0937
#define mmMC_XPB_CLG_CFG34                              0x0938
#define mmMC_XPB_CLG_CFG35                              0x0939
#define mmMC_XPB_CLG_CFG36                              0x093A
#define mmMC_XPB_CLG_CFG4                               0x08ED
#define mmMC_XPB_CLG_CFG5                               0x08EE
#define mmMC_XPB_CLG_CFG6                               0x08EF
#define mmMC_XPB_CLG_CFG7                               0x08F0
#define mmMC_XPB_CLG_CFG8                               0x08F1
#define mmMC_XPB_CLG_CFG9                               0x08F2
#define mmMC_XPB_CLG_EXTRA                              0x08FD
#define mmMC_XPB_CLG_EXTRA_RD                           0x0935
#define mmMC_XPB_CLK_GAT                                0x091E
#define mmMC_XPB_INTF_CFG                               0x091F
#define mmMC_XPB_INTF_CFG2                              0x0934
#define mmMC_XPB_INTF_STS                               0x0920
#define mmMC_XPB_LB_ADDR                                0x08FE
#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB               0x0923
#define mmMC_XPB_MISC_CFG                               0x0927
#define mmMC_XPB_P2P_BAR0                               0x0904
#define mmMC_XPB_P2P_BAR1                               0x0905
#define mmMC_XPB_P2P_BAR2                               0x0906
#define mmMC_XPB_P2P_BAR3                               0x0907
#define mmMC_XPB_P2P_BAR4                               0x0908
#define mmMC_XPB_P2P_BAR5                               0x0909
#define mmMC_XPB_P2P_BAR6                               0x090A
#define mmMC_XPB_P2P_BAR7                               0x090B
#define mmMC_XPB_P2P_BAR_CFG                            0x0903
#define mmMC_XPB_P2P_BAR_DEBUG                          0x090D
#define mmMC_XPB_P2P_BAR_DELTA_ABOVE                    0x090E
#define mmMC_XPB_P2P_BAR_DELTA_BELOW                    0x090F
#define mmMC_XPB_P2P_BAR_SETUP                          0x090C
#define mmMC_XPB_PEER_SYS_BAR0                          0x0910
#define mmMC_XPB_PEER_SYS_BAR1                          0x0911
#define mmMC_XPB_PEER_SYS_BAR2                          0x0912
#define mmMC_XPB_PEER_SYS_BAR3                          0x0913
#define mmMC_XPB_PEER_SYS_BAR4                          0x0914
#define mmMC_XPB_PEER_SYS_BAR5                          0x0915
#define mmMC_XPB_PEER_SYS_BAR6                          0x0916
#define mmMC_XPB_PEER_SYS_BAR7                          0x0917
#define mmMC_XPB_PEER_SYS_BAR8                          0x0918
#define mmMC_XPB_PEER_SYS_BAR9                          0x0919
#define mmMC_XPB_PERF_KNOBS                             0x0924
#define mmMC_XPB_PIPE_STS                               0x0921
#define mmMC_XPB_RTR_DEST_MAP0                          0x08DB
#define mmMC_XPB_RTR_DEST_MAP1                          0x08DC
#define mmMC_XPB_RTR_DEST_MAP2                          0x08DD
#define mmMC_XPB_RTR_DEST_MAP3                          0x08DE
#define mmMC_XPB_RTR_DEST_MAP4                          0x08DF
#define mmMC_XPB_RTR_DEST_MAP5                          0x08E0
#define mmMC_XPB_RTR_DEST_MAP6                          0x08E1
#define mmMC_XPB_RTR_DEST_MAP7                          0x08E2
#define mmMC_XPB_RTR_DEST_MAP8                          0x08E3
#define mmMC_XPB_RTR_DEST_MAP9                          0x08E4
#define mmMC_XPB_RTR_SRC_APRTR0                         0x08CD
#define mmMC_XPB_RTR_SRC_APRTR1                         0x08CE
#define mmMC_XPB_RTR_SRC_APRTR2                         0x08CF
#define mmMC_XPB_RTR_SRC_APRTR3                         0x08D0
#define mmMC_XPB_RTR_SRC_APRTR4                         0x08D1
#define mmMC_XPB_RTR_SRC_APRTR5                         0x08D2
#define mmMC_XPB_RTR_SRC_APRTR6                         0x08D3
#define mmMC_XPB_RTR_SRC_APRTR7                         0x08D4
#define mmMC_XPB_RTR_SRC_APRTR8                         0x08D5
#define mmMC_XPB_RTR_SRC_APRTR9                         0x08D6
#define mmMC_XPB_STICKY                                 0x0925
#define mmMC_XPB_STICKY_W1C                             0x0926
#define mmMC_XPB_SUB_CTRL                               0x0922
#define mmMC_XPB_UNC_THRESH_HST                         0x08FF
#define mmMC_XPB_UNC_THRESH_SID                         0x0900
#define mmMC_XPB_WCB_CFG                                0x0902
#define mmMC_XPB_WCB_STS                                0x0901
#define mmMC_XPB_XDMA_PEER_SYS_BAR0                     0x091A
#define mmMC_XPB_XDMA_PEER_SYS_BAR1                     0x091B
#define mmMC_XPB_XDMA_PEER_SYS_BAR2                     0x091C
#define mmMC_XPB_XDMA_PEER_SYS_BAR3                     0x091D
#define mmMC_XPB_XDMA_RTR_DEST_MAP0                     0x08E5
#define mmMC_XPB_XDMA_RTR_DEST_MAP1                     0x08E6
#define mmMC_XPB_XDMA_RTR_DEST_MAP2                     0x08E7
#define mmMC_XPB_XDMA_RTR_DEST_MAP3                     0x08E8
#define mmMC_XPB_XDMA_RTR_SRC_APRTR0                    0x08D7
#define mmMC_XPB_XDMA_RTR_SRC_APRTR1                    0x08D8
#define mmMC_XPB_XDMA_RTR_SRC_APRTR2                    0x08D9
#define mmMC_XPB_XDMA_RTR_SRC_APRTR3                    0x08DA
#define mmMEM_TYPE_CNTL__CI__VI                         0x14E4
#define mmMICROSECOND_TIME_BASE_DIV__SI                 0x0148
#define mmMM_CFGREGS_CNTL                               0x1513
#define mmMM_DATA                                       0x0001
#define mmMM_INDEX                                      0x0000
#define mmMM_INDEX_HI__CI__VI                           0x0006
#define mmMPLL_AD_FUNC_CNTL__SI__CI                     0x0AF0
#define mmMPLL_AD_STATUS__SI__CI                        0x0AF6
#define mmMPLL_BYPASSCLK_SEL__SI                        0x0197
#define mmMPLL_CNTL_MODE__SI__CI                        0x0AEC
#define mmMPLL_CONTROL__SI__CI                          0x0AF5
#define mmMPLL_DQ_0_0_STATUS__SI__CI                    0x0AF7
#define mmMPLL_DQ_0_1_STATUS__SI__CI                    0x0AF8
#define mmMPLL_DQ_1_0_STATUS__SI__CI                    0x0AF9
#define mmMPLL_DQ_1_1_STATUS__SI__CI                    0x0AFA
#define mmMPLL_DQ_FUNC_CNTL__SI__CI                     0x0AF1
#define mmMPLL_FUNC_CNTL__SI__CI                        0x0AED
#define mmMPLL_FUNC_CNTL_1__SI__CI                      0x0AEE
#define mmMPLL_FUNC_CNTL_2__SI__CI                      0x0AEF
#define mmMPLL_SEQ_UCODE_1__SI__CI                      0x0AEA
#define mmMPLL_SEQ_UCODE_2__SI__CI                      0x0AEB
#define mmMPLL_SS1__SI__CI                              0x0AF3
#define mmMPLL_SS2__SI__CI                              0x0AF4
#define mmMPLL_TIME__SI__CI                             0x0AF2
#define mmMVP_AFR_FLIP_FIFO_CNTL__SI                    0x1AD9
#define mmMVP_AFR_FLIP_MODE__SI                         0x1AD8
#define mmMVP_BLACK_KEYER__SI                           0x1686
#define mmMVP_CONTROL1__SI                              0x1680
#define mmMVP_CONTROL2__SI                              0x1681
#define mmMVP_CONTROL3__SI                              0x168A
#define mmMVP_CRC_CNTL__SI                              0x1687
#define mmMVP_CRC_RESULT_BLUE_GREEN__SI                 0x1688
#define mmMVP_CRC_RESULT_RED__SI                        0x1689
#define mmMVP_FIFO_CONTROL__SI                          0x1682
#define mmMVP_FIFO_STATUS__SI                           0x1683
#define mmMVP_FLIP_LINE_NUM_INSERT__SI                  0x1ADA
#define mmMVP_INBAND_CNTL_CAP__SI                       0x1685
#define mmMVP_RECEIVE_CNT_CNTL1__SI                     0x168B
#define mmMVP_RECEIVE_CNT_CNTL2__SI                     0x168C
#define mmMVP_SLAVE_STATUS__SI                          0x1684
#define mmMVP_TEST_DEBUG_DATA__SI                       0x168E
#define mmMVP_TEST_DEBUG_INDEX__SI                      0x168D
#define mmNEW_REFCLKB_TIMER_1__CI                       0x1484
#define mmNEW_REFCLKB_TIMER__CI                         0x1485
#define mmOVLSCL_EDGE_PIXEL_CNTL__SI__VI                0x1A2C
#define mmOVL_CONTROL1__SI__VI                          0x1A1D
#define mmOVL_CONTROL2__SI__VI                          0x1A1E
#define mmOVL_DFQ_CONTROL__SI__VI                       0x1A29
#define mmOVL_DFQ_STATUS__SI__VI                        0x1A2A
#define mmOVL_ENABLE__SI__VI                            0x1A1C
#define mmOVL_END__SI__VI                               0x1A26
#define mmOVL_PITCH__SI__VI                             0x1A21
#define mmOVL_START__SI__VI                             0x1A25
#define mmOVL_SURFACE_ADDRESS                           0x1A20
#define mmOVL_SURFACE_ADDRESS_HIGH                      0x1A22
#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI        0x1A2B
#define mmOVL_SURFACE_ADDRESS_INUSE__SI__VI             0x1A28
#define mmOVL_SURFACE_OFFSET_X__SI__VI                  0x1A23
#define mmOVL_SURFACE_OFFSET_Y__SI__VI                  0x1A24
#define mmOVL_SWAP_CNTL__SI__VI                         0x1A1F
#define mmOVL_UPDATE__SI__VI                            0x1A27
#define mmPAGE_MIRROR_CNTL__SI                          0x0581
#define mmPA_CL_CLIP_CNTL                               0xA204
#define mmPA_CL_CNTL_STATUS                             0x2284
#define mmPA_CL_ENHANCE                                 0x2285
#define mmPA_CL_GB_HORZ_CLIP_ADJ                        0xA2FC
#define mmPA_CL_GB_HORZ_DISC_ADJ                        0xA2FD
#define mmPA_CL_GB_VERT_CLIP_ADJ                        0xA2FA
#define mmPA_CL_GB_VERT_DISC_ADJ                        0xA2FB
#define mmPA_CL_NANINF_CNTL                             0xA208
#define mmPA_CL_POINT_CULL_RAD                          0xA1F8
#define mmPA_CL_POINT_SIZE                              0xA1F7
#define mmPA_CL_POINT_X_RAD                             0xA1F5
#define mmPA_CL_POINT_Y_RAD                             0xA1F6
#define mmPA_CL_RESET_DEBUG__CI__VI                     0x2286
#define mmPA_CL_UCP_0_W                                 0xA172
#define mmPA_CL_UCP_0_X                                 0xA16F
#define mmPA_CL_UCP_0_Y                                 0xA170
#define mmPA_CL_UCP_0_Z                                 0xA171
#define mmPA_CL_UCP_1_W                                 0xA176
#define mmPA_CL_UCP_1_X                                 0xA173
#define mmPA_CL_UCP_1_Y                                 0xA174
#define mmPA_CL_UCP_1_Z                                 0xA175
#define mmPA_CL_UCP_2_W                                 0xA17A
#define mmPA_CL_UCP_2_X                                 0xA177
#define mmPA_CL_UCP_2_Y                                 0xA178
#define mmPA_CL_UCP_2_Z                                 0xA179
#define mmPA_CL_UCP_3_W                                 0xA17E
#define mmPA_CL_UCP_3_X                                 0xA17B
#define mmPA_CL_UCP_3_Y                                 0xA17C
#define mmPA_CL_UCP_3_Z                                 0xA17D
#define mmPA_CL_UCP_4_W                                 0xA182
#define mmPA_CL_UCP_4_X                                 0xA17F
#define mmPA_CL_UCP_4_Y                                 0xA180
#define mmPA_CL_UCP_4_Z                                 0xA181
#define mmPA_CL_UCP_5_W                                 0xA186
#define mmPA_CL_UCP_5_X                                 0xA183
#define mmPA_CL_UCP_5_Y                                 0xA184
#define mmPA_CL_UCP_5_Z                                 0xA185
#define mmPA_CL_VPORT_XOFFSET                           0xA110
#define mmPA_CL_VPORT_XOFFSET_1                         0xA116
#define mmPA_CL_VPORT_XOFFSET_10                        0xA14C
#define mmPA_CL_VPORT_XOFFSET_11                        0xA152
#define mmPA_CL_VPORT_XOFFSET_12                        0xA158
#define mmPA_CL_VPORT_XOFFSET_13                        0xA15E
#define mmPA_CL_VPORT_XOFFSET_14                        0xA164
#define mmPA_CL_VPORT_XOFFSET_15                        0xA16A
#define mmPA_CL_VPORT_XOFFSET_2                         0xA11C
#define mmPA_CL_VPORT_XOFFSET_3                         0xA122
#define mmPA_CL_VPORT_XOFFSET_4                         0xA128
#define mmPA_CL_VPORT_XOFFSET_5                         0xA12E
#define mmPA_CL_VPORT_XOFFSET_6                         0xA134
#define mmPA_CL_VPORT_XOFFSET_7                         0xA13A
#define mmPA_CL_VPORT_XOFFSET_8                         0xA140
#define mmPA_CL_VPORT_XOFFSET_9                         0xA146
#define mmPA_CL_VPORT_XSCALE                            0xA10F
#define mmPA_CL_VPORT_XSCALE_1                          0xA115
#define mmPA_CL_VPORT_XSCALE_10                         0xA14B
#define mmPA_CL_VPORT_XSCALE_11                         0xA151
#define mmPA_CL_VPORT_XSCALE_12                         0xA157
#define mmPA_CL_VPORT_XSCALE_13                         0xA15D
#define mmPA_CL_VPORT_XSCALE_14                         0xA163
#define mmPA_CL_VPORT_XSCALE_15                         0xA169
#define mmPA_CL_VPORT_XSCALE_2                          0xA11B
#define mmPA_CL_VPORT_XSCALE_3                          0xA121
#define mmPA_CL_VPORT_XSCALE_4                          0xA127
#define mmPA_CL_VPORT_XSCALE_5                          0xA12D
#define mmPA_CL_VPORT_XSCALE_6                          0xA133
#define mmPA_CL_VPORT_XSCALE_7                          0xA139
#define mmPA_CL_VPORT_XSCALE_8                          0xA13F
#define mmPA_CL_VPORT_XSCALE_9                          0xA145
#define mmPA_CL_VPORT_YOFFSET                           0xA112
#define mmPA_CL_VPORT_YOFFSET_1                         0xA118
#define mmPA_CL_VPORT_YOFFSET_10                        0xA14E
#define mmPA_CL_VPORT_YOFFSET_11                        0xA154
#define mmPA_CL_VPORT_YOFFSET_12                        0xA15A
#define mmPA_CL_VPORT_YOFFSET_13                        0xA160
#define mmPA_CL_VPORT_YOFFSET_14                        0xA166
#define mmPA_CL_VPORT_YOFFSET_15                        0xA16C
#define mmPA_CL_VPORT_YOFFSET_2                         0xA11E
#define mmPA_CL_VPORT_YOFFSET_3                         0xA124
#define mmPA_CL_VPORT_YOFFSET_4                         0xA12A
#define mmPA_CL_VPORT_YOFFSET_5                         0xA130
#define mmPA_CL_VPORT_YOFFSET_6                         0xA136
#define mmPA_CL_VPORT_YOFFSET_7                         0xA13C
#define mmPA_CL_VPORT_YOFFSET_8                         0xA142
#define mmPA_CL_VPORT_YOFFSET_9                         0xA148
#define mmPA_CL_VPORT_YSCALE                            0xA111
#define mmPA_CL_VPORT_YSCALE_1                          0xA117
#define mmPA_CL_VPORT_YSCALE_10                         0xA14D
#define mmPA_CL_VPORT_YSCALE_11                         0xA153
#define mmPA_CL_VPORT_YSCALE_12                         0xA159
#define mmPA_CL_VPORT_YSCALE_13                         0xA15F
#define mmPA_CL_VPORT_YSCALE_14                         0xA165
#define mmPA_CL_VPORT_YSCALE_15                         0xA16B
#define mmPA_CL_VPORT_YSCALE_2                          0xA11D
#define mmPA_CL_VPORT_YSCALE_3                          0xA123
#define mmPA_CL_VPORT_YSCALE_4                          0xA129
#define mmPA_CL_VPORT_YSCALE_5                          0xA12F
#define mmPA_CL_VPORT_YSCALE_6                          0xA135
#define mmPA_CL_VPORT_YSCALE_7                          0xA13B
#define mmPA_CL_VPORT_YSCALE_8                          0xA141
#define mmPA_CL_VPORT_YSCALE_9                          0xA147
#define mmPA_CL_VPORT_ZOFFSET                           0xA114
#define mmPA_CL_VPORT_ZOFFSET_1                         0xA11A
#define mmPA_CL_VPORT_ZOFFSET_10                        0xA150
#define mmPA_CL_VPORT_ZOFFSET_11                        0xA156
#define mmPA_CL_VPORT_ZOFFSET_12                        0xA15C
#define mmPA_CL_VPORT_ZOFFSET_13                        0xA162
#define mmPA_CL_VPORT_ZOFFSET_14                        0xA168
#define mmPA_CL_VPORT_ZOFFSET_15                        0xA16E
#define mmPA_CL_VPORT_ZOFFSET_2                         0xA120
#define mmPA_CL_VPORT_ZOFFSET_3                         0xA126
#define mmPA_CL_VPORT_ZOFFSET_4                         0xA12C
#define mmPA_CL_VPORT_ZOFFSET_5                         0xA132
#define mmPA_CL_VPORT_ZOFFSET_6                         0xA138
#define mmPA_CL_VPORT_ZOFFSET_7                         0xA13E
#define mmPA_CL_VPORT_ZOFFSET_8                         0xA144
#define mmPA_CL_VPORT_ZOFFSET_9                         0xA14A
#define mmPA_CL_VPORT_ZSCALE                            0xA113
#define mmPA_CL_VPORT_ZSCALE_1                          0xA119
#define mmPA_CL_VPORT_ZSCALE_10                         0xA14F
#define mmPA_CL_VPORT_ZSCALE_11                         0xA155
#define mmPA_CL_VPORT_ZSCALE_12                         0xA15B
#define mmPA_CL_VPORT_ZSCALE_13                         0xA161
#define mmPA_CL_VPORT_ZSCALE_14                         0xA167
#define mmPA_CL_VPORT_ZSCALE_15                         0xA16D
#define mmPA_CL_VPORT_ZSCALE_2                          0xA11F
#define mmPA_CL_VPORT_ZSCALE_3                          0xA125
#define mmPA_CL_VPORT_ZSCALE_4                          0xA12B
#define mmPA_CL_VPORT_ZSCALE_5                          0xA131
#define mmPA_CL_VPORT_ZSCALE_6                          0xA137
#define mmPA_CL_VPORT_ZSCALE_7                          0xA13D
#define mmPA_CL_VPORT_ZSCALE_8                          0xA143
#define mmPA_CL_VPORT_ZSCALE_9                          0xA149
#define mmPA_CL_VS_OUT_CNTL                             0xA207
#define mmPA_CL_VTE_CNTL                                0xA206
#define mmPA_SC_AA_CONFIG                               0xA2F8
#define mmPA_SC_AA_MASK_X0Y0_X1Y0                       0xA30E
#define mmPA_SC_AA_MASK_X0Y1_X1Y1                       0xA30F
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0             0xA2FE
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1             0xA2FF
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2             0xA300
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3             0xA301
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0             0xA306
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1             0xA307
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2             0xA308
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3             0xA309
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0             0xA302
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1             0xA303
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2             0xA304
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3             0xA305
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0             0xA30A
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1             0xA30B
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2             0xA30C
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3             0xA30D
#define mmPA_SC_CENTROID_PRIORITY_0                     0xA2F5
#define mmPA_SC_CENTROID_PRIORITY_1                     0xA2F6
#define mmPA_SC_CLIPRECT_0_BR                           0xA085
#define mmPA_SC_CLIPRECT_0_TL                           0xA084
#define mmPA_SC_CLIPRECT_1_BR                           0xA087
#define mmPA_SC_CLIPRECT_1_TL                           0xA086
#define mmPA_SC_CLIPRECT_2_BR                           0xA089
#define mmPA_SC_CLIPRECT_2_TL                           0xA088
#define mmPA_SC_CLIPRECT_3_BR                           0xA08B
#define mmPA_SC_CLIPRECT_3_TL                           0xA08A
#define mmPA_SC_CLIPRECT_RULE                           0xA083
#define mmPA_SC_DEBUG_CNTL                              0x22F6
#define mmPA_SC_DEBUG_DATA                              0x22F7
#define mmPA_SC_EDGERULE                                0xA08C
#define mmPA_SC_ENHANCE                                 0x22FC
#define mmPA_SC_FIFO_DEPTH_CNTL                         0x2295
#define mmPA_SC_FIFO_SIZE                               0x22F3
#define mmPA_SC_FORCE_EOV_MAX_CNTS                      0x22C9
#define mmPA_SC_GENERIC_SCISSOR_BR                      0xA091
#define mmPA_SC_GENERIC_SCISSOR_TL                      0xA090
#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI          0xC2AC
#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI          0xC2A8
#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI        0x22C1
#define mmPA_SC_HP3D_TRAP_SCREEN_H__CI__VI              0xC2A9
#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI     0xC2AB
#define mmPA_SC_HP3D_TRAP_SCREEN_V__CI__VI              0xC2AA
#define mmPA_SC_IF_FIFO_SIZE                            0x22F5
#define mmPA_SC_LINE_CNTL                               0xA2F7
#define mmPA_SC_LINE_STIPPLE                            0xA283
#define mmPA_SC_LINE_STIPPLE_STATE__CI__VI              0xC281
#define mmPA_SC_LINE_STIPPLE_STATE__SI                  0x22C4
#define mmPA_SC_MODE_CNTL_0                             0xA292
#define mmPA_SC_MODE_CNTL_1                             0xA293
#define mmPA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI           0xC2A4
#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI           0xC2A0
#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI         0x22C0
#define mmPA_SC_P3D_TRAP_SCREEN_H__CI__VI               0xC2A1
#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI      0xC2A3
#define mmPA_SC_P3D_TRAP_SCREEN_V__CI__VI               0xC2A2
#define mmPA_SC_PERFCOUNTER0_HI__CI__VI                 0xD141
#define mmPA_SC_PERFCOUNTER0_HI__SI                     0x22A9
#define mmPA_SC_PERFCOUNTER0_LO__CI__VI                 0xD140
#define mmPA_SC_PERFCOUNTER0_LO__SI                     0x22A8
#define mmPA_SC_PERFCOUNTER0_SELECT1__CI__VI            0xD941
#define mmPA_SC_PERFCOUNTER0_SELECT__CI__VI             0xD940
#define mmPA_SC_PERFCOUNTER0_SELECT__SI                 0x22A0
#define mmPA_SC_PERFCOUNTER1_HI__CI__VI                 0xD143
#define mmPA_SC_PERFCOUNTER1_HI__SI                     0x22AB
#define mmPA_SC_PERFCOUNTER1_LO__CI__VI                 0xD142
#define mmPA_SC_PERFCOUNTER1_LO__SI                     0x22AA
#define mmPA_SC_PERFCOUNTER1_SELECT__CI__VI             0xD942
#define mmPA_SC_PERFCOUNTER1_SELECT__SI                 0x22A1
#define mmPA_SC_PERFCOUNTER2_HI__CI__VI                 0xD145
#define mmPA_SC_PERFCOUNTER2_HI__SI                     0x22AD
#define mmPA_SC_PERFCOUNTER2_LO__CI__VI                 0xD144
#define mmPA_SC_PERFCOUNTER2_LO__SI                     0x22AC
#define mmPA_SC_PERFCOUNTER2_SELECT__CI__VI             0xD943
#define mmPA_SC_PERFCOUNTER2_SELECT__SI                 0x22A2
#define mmPA_SC_PERFCOUNTER3_HI__CI__VI                 0xD147
#define mmPA_SC_PERFCOUNTER3_HI__SI                     0x22AF
#define mmPA_SC_PERFCOUNTER3_LO__CI__VI                 0xD146
#define mmPA_SC_PERFCOUNTER3_LO__SI                     0x22AE
#define mmPA_SC_PERFCOUNTER3_SELECT__CI__VI             0xD944
#define mmPA_SC_PERFCOUNTER3_SELECT__SI                 0x22A3
#define mmPA_SC_PERFCOUNTER4_HI__CI__VI                 0xD149
#define mmPA_SC_PERFCOUNTER4_HI__SI                     0x22B1
#define mmPA_SC_PERFCOUNTER4_LO__CI__VI                 0xD148
#define mmPA_SC_PERFCOUNTER4_LO__SI                     0x22B0
#define mmPA_SC_PERFCOUNTER4_SELECT__CI__VI             0xD945
#define mmPA_SC_PERFCOUNTER4_SELECT__SI                 0x22A4
#define mmPA_SC_PERFCOUNTER5_HI__CI__VI                 0xD14B
#define mmPA_SC_PERFCOUNTER5_HI__SI                     0x22B3
#define mmPA_SC_PERFCOUNTER5_LO__CI__VI                 0xD14A
#define mmPA_SC_PERFCOUNTER5_LO__SI                     0x22B2
#define mmPA_SC_PERFCOUNTER5_SELECT__CI__VI             0xD946
#define mmPA_SC_PERFCOUNTER5_SELECT__SI                 0x22A5
#define mmPA_SC_PERFCOUNTER6_HI__CI__VI                 0xD14D
#define mmPA_SC_PERFCOUNTER6_HI__SI                     0x22B5
#define mmPA_SC_PERFCOUNTER6_LO__CI__VI                 0xD14C
#define mmPA_SC_PERFCOUNTER6_LO__SI                     0x22B4
#define mmPA_SC_PERFCOUNTER6_SELECT__CI__VI             0xD947
#define mmPA_SC_PERFCOUNTER6_SELECT__SI                 0x22A6
#define mmPA_SC_PERFCOUNTER7_HI__CI__VI                 0xD14F
#define mmPA_SC_PERFCOUNTER7_HI__SI                     0x22B7
#define mmPA_SC_PERFCOUNTER7_LO__CI__VI                 0xD14E
#define mmPA_SC_PERFCOUNTER7_LO__SI                     0x22B6
#define mmPA_SC_PERFCOUNTER7_SELECT__CI__VI             0xD948
#define mmPA_SC_PERFCOUNTER7_SELECT__SI                 0x22A7
#define mmPA_SC_RASTER_CONFIG                           0xA0D4
#define mmPA_SC_RASTER_CONFIG_1__CI__VI                 0xA0D5
#define mmPA_SC_SCREEN_EXTENT_CONTROL__CI__VI           0xA0D6
#define mmPA_SC_SCREEN_EXTENT_MAX_0__CI__VI             0xC285
#define mmPA_SC_SCREEN_EXTENT_MAX_1__CI__VI             0xC28B
#define mmPA_SC_SCREEN_EXTENT_MIN_0__CI__VI             0xC284
#define mmPA_SC_SCREEN_EXTENT_MIN_1__CI__VI             0xC286
#define mmPA_SC_SCREEN_SCISSOR_BR                       0xA00D
#define mmPA_SC_SCREEN_SCISSOR_TL                       0xA00C
#define mmPA_SC_TRAP_SCREEN_COUNT__CI__VI               0xC2B4
#define mmPA_SC_TRAP_SCREEN_HV_EN__CI__VI               0xC2B0
#define mmPA_SC_TRAP_SCREEN_HV_LOCK__CI__VI             0x22C2
#define mmPA_SC_TRAP_SCREEN_H__CI__VI                   0xC2B1
#define mmPA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI          0xC2B3
#define mmPA_SC_TRAP_SCREEN_V__CI__VI                   0xC2B2
#define mmPA_SC_VPORT_SCISSOR_0_BR                      0xA095
#define mmPA_SC_VPORT_SCISSOR_0_TL                      0xA094
#define mmPA_SC_VPORT_SCISSOR_10_BR                     0xA0A9
#define mmPA_SC_VPORT_SCISSOR_10_TL                     0xA0A8
#define mmPA_SC_VPORT_SCISSOR_11_BR                     0xA0AB
#define mmPA_SC_VPORT_SCISSOR_11_TL                     0xA0AA
#define mmPA_SC_VPORT_SCISSOR_12_BR                     0xA0AD
#define mmPA_SC_VPORT_SCISSOR_12_TL                     0xA0AC
#define mmPA_SC_VPORT_SCISSOR_13_BR                     0xA0AF
#define mmPA_SC_VPORT_SCISSOR_13_TL                     0xA0AE
#define mmPA_SC_VPORT_SCISSOR_14_BR                     0xA0B1
#define mmPA_SC_VPORT_SCISSOR_14_TL                     0xA0B0
#define mmPA_SC_VPORT_SCISSOR_15_BR                     0xA0B3
#define mmPA_SC_VPORT_SCISSOR_15_TL                     0xA0B2
#define mmPA_SC_VPORT_SCISSOR_1_BR                      0xA097
#define mmPA_SC_VPORT_SCISSOR_1_TL                      0xA096
#define mmPA_SC_VPORT_SCISSOR_2_BR                      0xA099
#define mmPA_SC_VPORT_SCISSOR_2_TL                      0xA098
#define mmPA_SC_VPORT_SCISSOR_3_BR                      0xA09B
#define mmPA_SC_VPORT_SCISSOR_3_TL                      0xA09A
#define mmPA_SC_VPORT_SCISSOR_4_BR                      0xA09D
#define mmPA_SC_VPORT_SCISSOR_4_TL                      0xA09C
#define mmPA_SC_VPORT_SCISSOR_5_BR                      0xA09F
#define mmPA_SC_VPORT_SCISSOR_5_TL                      0xA09E
#define mmPA_SC_VPORT_SCISSOR_6_BR                      0xA0A1
#define mmPA_SC_VPORT_SCISSOR_6_TL                      0xA0A0
#define mmPA_SC_VPORT_SCISSOR_7_BR                      0xA0A3
#define mmPA_SC_VPORT_SCISSOR_7_TL                      0xA0A2
#define mmPA_SC_VPORT_SCISSOR_8_BR                      0xA0A5
#define mmPA_SC_VPORT_SCISSOR_8_TL                      0xA0A4
#define mmPA_SC_VPORT_SCISSOR_9_BR                      0xA0A7
#define mmPA_SC_VPORT_SCISSOR_9_TL                      0xA0A6
#define mmPA_SC_VPORT_ZMAX_0                            0xA0B5
#define mmPA_SC_VPORT_ZMAX_1                            0xA0B7
#define mmPA_SC_VPORT_ZMAX_10                           0xA0C9
#define mmPA_SC_VPORT_ZMAX_11                           0xA0CB
#define mmPA_SC_VPORT_ZMAX_12                           0xA0CD
#define mmPA_SC_VPORT_ZMAX_13                           0xA0CF
#define mmPA_SC_VPORT_ZMAX_14                           0xA0D1
#define mmPA_SC_VPORT_ZMAX_15                           0xA0D3
#define mmPA_SC_VPORT_ZMAX_2                            0xA0B9
#define mmPA_SC_VPORT_ZMAX_3                            0xA0BB
#define mmPA_SC_VPORT_ZMAX_4                            0xA0BD
#define mmPA_SC_VPORT_ZMAX_5                            0xA0BF
#define mmPA_SC_VPORT_ZMAX_6                            0xA0C1
#define mmPA_SC_VPORT_ZMAX_7                            0xA0C3
#define mmPA_SC_VPORT_ZMAX_8                            0xA0C5
#define mmPA_SC_VPORT_ZMAX_9                            0xA0C7
#define mmPA_SC_VPORT_ZMIN_0                            0xA0B4
#define mmPA_SC_VPORT_ZMIN_1                            0xA0B6
#define mmPA_SC_VPORT_ZMIN_10                           0xA0C8
#define mmPA_SC_VPORT_ZMIN_11                           0xA0CA
#define mmPA_SC_VPORT_ZMIN_12                           0xA0CC
#define mmPA_SC_VPORT_ZMIN_13                           0xA0CE
#define mmPA_SC_VPORT_ZMIN_14                           0xA0D0
#define mmPA_SC_VPORT_ZMIN_15                           0xA0D2
#define mmPA_SC_VPORT_ZMIN_2                            0xA0B8
#define mmPA_SC_VPORT_ZMIN_3                            0xA0BA
#define mmPA_SC_VPORT_ZMIN_4                            0xA0BC
#define mmPA_SC_VPORT_ZMIN_5                            0xA0BE
#define mmPA_SC_VPORT_ZMIN_6                            0xA0C0
#define mmPA_SC_VPORT_ZMIN_7                            0xA0C2
#define mmPA_SC_VPORT_ZMIN_8                            0xA0C4
#define mmPA_SC_VPORT_ZMIN_9                            0xA0C6
#define mmPA_SC_WINDOW_OFFSET                           0xA080
#define mmPA_SC_WINDOW_SCISSOR_BR                       0xA082
#define mmPA_SC_WINDOW_SCISSOR_TL                       0xA081
#define mmPA_SU_CNTL_STATUS                             0x2294
#define mmPA_SU_DEBUG_CNTL                              0x2280
#define mmPA_SU_DEBUG_DATA                              0x2281
#define mmPA_SU_HARDWARE_SCREEN_OFFSET                  0xA08D
#define mmPA_SU_LINE_CNTL                               0xA282
#define mmPA_SU_LINE_STIPPLE_CNTL                       0xA209
#define mmPA_SU_LINE_STIPPLE_SCALE                      0xA20A
#define mmPA_SU_LINE_STIPPLE_VALUE__CI__VI              0xC280
#define mmPA_SU_LINE_STIPPLE_VALUE__SI                  0x2298
#define mmPA_SU_PERFCOUNTER0_HI__CI__VI                 0xD101
#define mmPA_SU_PERFCOUNTER0_HI__SI                     0x228D
#define mmPA_SU_PERFCOUNTER0_LO__CI__VI                 0xD100
#define mmPA_SU_PERFCOUNTER0_LO__SI                     0x228C
#define mmPA_SU_PERFCOUNTER0_SELECT1__CI__VI            0xD901
#define mmPA_SU_PERFCOUNTER0_SELECT__CI__VI             0xD900
#define mmPA_SU_PERFCOUNTER0_SELECT__SI                 0x2288
#define mmPA_SU_PERFCOUNTER1_HI__CI__VI                 0xD103
#define mmPA_SU_PERFCOUNTER1_HI__SI                     0x228F
#define mmPA_SU_PERFCOUNTER1_LO__CI__VI                 0xD102
#define mmPA_SU_PERFCOUNTER1_LO__SI                     0x228E
#define mmPA_SU_PERFCOUNTER1_SELECT1__CI__VI            0xD903
#define mmPA_SU_PERFCOUNTER1_SELECT__CI__VI             0xD902
#define mmPA_SU_PERFCOUNTER1_SELECT__SI                 0x2289
#define mmPA_SU_PERFCOUNTER2_HI__CI__VI                 0xD105
#define mmPA_SU_PERFCOUNTER2_HI__SI                     0x2291
#define mmPA_SU_PERFCOUNTER2_LO__CI__VI                 0xD104
#define mmPA_SU_PERFCOUNTER2_LO__SI                     0x2290
#define mmPA_SU_PERFCOUNTER2_SELECT__CI__VI             0xD904
#define mmPA_SU_PERFCOUNTER2_SELECT__SI                 0x228A
#define mmPA_SU_PERFCOUNTER3_HI__CI__VI                 0xD107
#define mmPA_SU_PERFCOUNTER3_HI__SI                     0x2293
#define mmPA_SU_PERFCOUNTER3_LO__CI__VI                 0xD106
#define mmPA_SU_PERFCOUNTER3_LO__SI                     0x2292
#define mmPA_SU_PERFCOUNTER3_SELECT__CI__VI             0xD905
#define mmPA_SU_PERFCOUNTER3_SELECT__SI                 0x228B
#define mmPA_SU_POINT_MINMAX                            0xA281
#define mmPA_SU_POINT_SIZE                              0xA280
#define mmPA_SU_POLY_OFFSET_BACK_OFFSET                 0xA2E3
#define mmPA_SU_POLY_OFFSET_BACK_SCALE                  0xA2E2
#define mmPA_SU_POLY_OFFSET_CLAMP                       0xA2DF
#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                 0xA2DE
#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                0xA2E1
#define mmPA_SU_POLY_OFFSET_FRONT_SCALE                 0xA2E0
#define mmPA_SU_PRIM_FILTER_CNTL                        0xA20B
#define mmPA_SU_SC_MODE_CNTL                            0xA205
#define mmPA_SU_VTX_CNTL                                0xA2F9
#define mmPCIE_DATA_2__CI__VI                           0x000D
#define mmPCIE_DATA__CI__VI                             0x000F
#define mmPCIE_DATA__SI                                 0x000D
#define mmPCIE_INDEX_2__CI__VI                          0x000C
#define mmPCIE_INDEX__CI__VI                            0x000E
#define mmPCIE_INDEX__SI                                0x000C
#define mmPEER0_FB_OFFSET_HI__CI__VI                    0x14F3
#define mmPEER0_FB_OFFSET_LO__CI__VI                    0x14F2
#define mmPEER1_FB_OFFSET_HI__CI__VI                    0x14F1
#define mmPEER1_FB_OFFSET_LO__CI__VI                    0x14F0
#define mmPEER2_FB_OFFSET_HI__CI__VI                    0x14EF
#define mmPEER2_FB_OFFSET_LO__CI__VI                    0x14EE
#define mmPEER3_FB_OFFSET_HI__CI__VI                    0x14ED
#define mmPEER3_FB_OFFSET_LO__CI__VI                    0x14EC
#define mmPEER_REG_RANGE0                               0x153E
#define mmPEER_REG_RANGE1                               0x153F
#define mmPHY_AUX_CNTL__SI                              0x1953
#define mmPIPE0_ARBITRATION_CONTROL3__SI                0x02FC
#define mmPIPE1_ARBITRATION_CONTROL3__SI                0x0300
#define mmPIPE2_ARBITRATION_CONTROL3__SI                0x0304
#define mmPIPE3_ARBITRATION_CONTROL3__SI                0x0308
#define mmPIPE4_ARBITRATION_CONTROL3__SI                0x030C
#define mmPIPE5_ARBITRATION_CONTROL3__SI                0x0310
#define mmPIXCLK1_RESYNC_CNTL__SI                       0x0126
#define mmPIXCLK2_RESYNC_CNTL__SI                       0x0127
#define mmPLL_TEST_CNTL__SI                             0x0199
#define mmRAS_BCI_SIGNATURE0                            0x339E
#define mmRAS_BCI_SIGNATURE1                            0x339F
#define mmRAS_CB_SIGNATURE0                             0x339D
#define mmRAS_DB_SIGNATURE0                             0x338B
#define mmRAS_IA_SIGNATURE0                             0x3397
#define mmRAS_IA_SIGNATURE1                             0x3398
#define mmRAS_PA_SIGNATURE0                             0x338C
#define mmRAS_SC_SIGNATURE0                             0x338F
#define mmRAS_SC_SIGNATURE1                             0x3390
#define mmRAS_SC_SIGNATURE2                             0x3391
#define mmRAS_SC_SIGNATURE3                             0x3392
#define mmRAS_SC_SIGNATURE4                             0x3393
#define mmRAS_SC_SIGNATURE5                             0x3394
#define mmRAS_SC_SIGNATURE6                             0x3395
#define mmRAS_SC_SIGNATURE7                             0x3396
#define mmRAS_SIGNATURE_CONTROL                         0x3380
#define mmRAS_SIGNATURE_MASK                            0x3381
#define mmRAS_SPI_SIGNATURE0                            0x3399
#define mmRAS_SPI_SIGNATURE1                            0x339A
#define mmRAS_SQ_SIGNATURE0                             0x338E
#define mmRAS_SX_SIGNATURE0                             0x3382
#define mmRAS_SX_SIGNATURE1                             0x3383
#define mmRAS_SX_SIGNATURE2                             0x3384
#define mmRAS_SX_SIGNATURE3                             0x3385
#define mmRAS_TA_SIGNATURE0                             0x339B
#define mmRAS_TD_SIGNATURE0                             0x339C
#define mmRAS_VGT_SIGNATURE0                            0x338D
#define mmRCU_MISC_CTRL__SI                             0x0043
#define mmRCU_UC_EVENTS__SI                             0x0045
#define mmRLC_AUTO_PG_CTRL__CI                          0x3115
#define mmRLC_AUTO_PG_CTRL__SI                          0x310D
#define mmRLC_CAPTURE_GPU_CLOCK_COUNT__CI               0x30E6
#define mmRLC_CAPTURE_GPU_CLOCK_COUNT__SI               0x30D0
#define mmRLC_CGCG_CGLS_CTRL__CI                        0x3109
#define mmRLC_CGCG_CGLS_CTRL__SI                        0x3101
#define mmRLC_CGCG_RAMP_CTRL__CI                        0x310A
#define mmRLC_CGCG_RAMP_CTRL__SI                        0x3102
#define mmRLC_CGTT_MGCG_OVERRIDE__CI                    0x3108
#define mmRLC_CGTT_MGCG_OVERRIDE__SI                    0x3100
#define mmRLC_CU_STATUS__CI                             0x310E
#define mmRLC_CU_STATUS__SI                             0x3106
#define mmRLC_DEBUG_SELECT__CI                          0x30C1
#define mmRLC_DEBUG_SELECT__SI                          0x30C9
#define mmRLC_DEBUG__CI                                 0x30C2
#define mmRLC_DEBUG__SI                                 0x30CA
#define mmRLC_DRIVER_CPDMA_STATUS__CI                   0x30DE
#define mmRLC_DRIVER_CPDMA_STATUS__SI                   0x30C7
#define mmRLC_DYN_PG_REQUEST__CI                        0x310C
#define mmRLC_DYN_PG_REQUEST__SI                        0x3104
#define mmRLC_DYN_PG_STATUS__CI                         0x310B
#define mmRLC_DYN_PG_STATUS__SI                         0x3103
#define mmRLC_GPM_CU_PD_TIMEOUT__CI                     0x312B
#define mmRLC_GPM_DEBUG_SELECT__CI                      0x30E0
#define mmRLC_GPM_DEBUG__CI                             0x30E1
#define mmRLC_GPM_GENERAL_0__CI                         0x3123
#define mmRLC_GPM_GENERAL_1__CI                         0x3124
#define mmRLC_GPM_GENERAL_2__CI                         0x3125
#define mmRLC_GPM_GENERAL_3__CI                         0x3126
#define mmRLC_GPM_GENERAL_4__CI                         0x3127
#define mmRLC_GPM_GENERAL_5__CI                         0x3128
#define mmRLC_GPM_GENERAL_6__CI                         0x3129
#define mmRLC_GPM_GENERAL_7__CI                         0x312A
#define mmRLC_GPM_LOG_ADDR__CI                          0x3136
#define mmRLC_GPM_LOG_CONT__CI                          0x3138
#define mmRLC_GPM_LOG_SIZE__CI                          0x3137
#define mmRLC_GPM_PERF_COUNT_0__CI                      0x312F
#define mmRLC_GPM_PERF_COUNT_1__CI                      0x3130
#define mmRLC_GPM_SCRATCH_ADDR__CI                      0x312C
#define mmRLC_GPM_SCRATCH_DATA__CI                      0x312D
#define mmRLC_GPM_STAT__CI                              0x3100
#define mmRLC_GPM_THREAD_ENABLE__CI                     0x3105
#define mmRLC_GPM_THREAD_PRIORITY__CI                   0x3104
#define mmRLC_GPM_UCODE_ADDR__CI                        0x30E2
#define mmRLC_GPM_UCODE_DATA__CI                        0x30E3
#define mmRLC_GPM_VMID_THREAD0__CI                      0x3106
#define mmRLC_GPM_VMID_THREAD1__CI                      0x3107
#define mmRLC_GPR_REG1__CI                              0x3139
#define mmRLC_GPR_REG2__CI                              0x313A
#define mmRLC_GPU_CLOCK_32_RES_SEL__CI                  0x3101
#define mmRLC_GPU_CLOCK_32_RES_SEL__SI                  0x30D4
#define mmRLC_GPU_CLOCK_32__CI                          0x3102
#define mmRLC_GPU_CLOCK_32__SI                          0x30D5
#define mmRLC_GPU_CLOCK_COUNT_LSB__CI                   0x30E4
#define mmRLC_GPU_CLOCK_COUNT_LSB__SI                   0x30CE
#define mmRLC_GPU_CLOCK_COUNT_MSB__CI                   0x30E5
#define mmRLC_GPU_CLOCK_COUNT_MSB__SI                   0x30CF
#define mmRLC_JUMP_TABLE_RESTORE__CI                    0x30DE
#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__CI              0x3110
#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__SI              0x3108
#define mmRLC_LB_CNTL__CI                               0x30D9
#define mmRLC_LB_CNTL__SI                               0x30C3
#define mmRLC_LB_CNTR_INIT__CI                          0x30DB
#define mmRLC_LB_CNTR_INIT__SI                          0x30C6
#define mmRLC_LB_CNTR_MAX__CI                           0x30D2
#define mmRLC_LB_CNTR_MAX__SI                           0x30C5
#define mmRLC_LB_INIT_CU_MASK__CI                       0x310F
#define mmRLC_LB_INIT_CU_MASK__SI                       0x3107
#define mmRLC_LB_PARAMS__CI                             0x3111
#define mmRLC_LB_PARAMS__SI                             0x3109
#define mmRLC_LOAD_BALANCE_CNTR__CI                     0x30DC
#define mmRLC_LOAD_BALANCE_CNTR__SI                     0x30F6
#define mmRLC_MAX_PG_CU__CI                             0x3114
#define mmRLC_MAX_PG_CU__SI                             0x310C
#define mmRLC_MC_CNTL__CI                               0x30C3
#define mmRLC_MC_CNTL__SI                               0x30D1
#define mmRLC_MEM_SLP_CNTL__CI                          0x30C6
#define mmRLC_MEM_SLP_CNTL__SI                          0x30D8
#define mmRLC_PERFCOUNTER0_HI__CI__VI                   0xD481
#define mmRLC_PERFCOUNTER0_HI__SI                       0x30DC
#define mmRLC_PERFCOUNTER0_LO__CI__VI                   0xD480
#define mmRLC_PERFCOUNTER0_LO__SI                       0x30DB
#define mmRLC_PERFCOUNTER0_SELECT__CI__VI               0xDCC1
#define mmRLC_PERFCOUNTER0_SELECT__SI                   0x30DA
#define mmRLC_PERFCOUNTER1_HI__CI__VI                   0xD483
#define mmRLC_PERFCOUNTER1_HI__SI                       0x30DF
#define mmRLC_PERFCOUNTER1_LO__CI__VI                   0xD482
#define mmRLC_PERFCOUNTER1_LO__SI                       0x30DE
#define mmRLC_PERFCOUNTER1_SELECT__CI__VI               0xDCC2
#define mmRLC_PERFCOUNTER1_SELECT__SI                   0x30DD
#define mmRLC_PERFMON_CNTL__CI__VI                      0xDCC0
#define mmRLC_PERFMON_CNTL__SI                          0x30D9
#define mmRLC_PG_ALWAYS_ON_CU_MASK__CI                  0x3113
#define mmRLC_PG_ALWAYS_ON_CU_MASK__SI                  0x310B
#define mmRLC_PG_CNTL__CI                               0x3103
#define mmRLC_PG_CNTL__SI                               0x30D7
#define mmRLC_PG_DELAY_2__CI                            0x30DF
#define mmRLC_PG_DELAY__CI                              0x310D
#define mmRLC_SAFE_MODE__CI                             0x313A
#define mmRLC_SAVE_AND_RESTORE_BASE__CI                 0x30DD
#define mmRLC_SAVE_AND_RESTORE_BASE__SI                 0x30C4
#define mmRLC_SERDES_CU_MASTER_BUSY__CI                 0x3121
#define mmRLC_SERDES_NONCU_MASTER_BUSY__CI              0x3122
#define mmRLC_SERDES_RD_DATA_0__CI                      0x311A
#define mmRLC_SERDES_RD_DATA_0__SI                      0x3112
#define mmRLC_SERDES_RD_DATA_1__CI                      0x311B
#define mmRLC_SERDES_RD_DATA_1__SI                      0x3113
#define mmRLC_SERDES_RD_DATA_2__CI                      0x311C
#define mmRLC_SERDES_RD_DATA_2__SI                      0x3114
#define mmRLC_SERDES_RD_MASTER_INDEX__CI                0x3119
#define mmRLC_SERDES_RD_MASTER_INDEX__SI                0x3111
#define mmRLC_SERDES_WR_CTRL__CI                        0x311F
#define mmRLC_SERDES_WR_CTRL__SI                        0x3117
#define mmRLC_SERDES_WR_CU_MASTER_MASK__CI              0x311D
#define mmRLC_SERDES_WR_DATA__CI                        0x3120
#define mmRLC_SERDES_WR_DATA__SI                        0x3118
#define mmRLC_SERDES_WR_NONCU_MASTER_MASK__CI           0x311E
#define mmRLC_SMU_GRBM_REG_SAVE_CTRL__CI                0x3116
#define mmRLC_SMU_GRBM_REG_SAVE_CTRL__SI                0x310E
#define mmRLC_SMU_PG_CTRL__CI                           0x3117
#define mmRLC_SMU_PG_CTRL__SI                           0x310F
#define mmRLC_SMU_PG_WAKE_UP_CTRL__CI                   0x3118
#define mmRLC_SMU_PG_WAKE_UP_CTRL__SI                   0x3110
#define mmRLC_SOFT_RESET_GPU__CI                        0x30C5
#define mmRLC_SOFT_RESET_GPU__SI                        0x30D6
#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI       0xDC8A
#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI      0xDC88
#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI      0xDC89
#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI      0xDC87
#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI       0xDC8B
#define mmRLC_SPM_DEBUG_SELECT__CI                      0x3134
#define mmRLC_SPM_DEBUG__CI                             0x3135
#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI      0xDC8D
#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI            0xDC9B
#define mmRLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI            0xDC9C
#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI       0xDC8E
#define mmRLC_SPM_INT_CNTL__CI                          0x3132
#define mmRLC_SPM_INT_STATUS__CI                        0x3133
#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI       0xDC8C
#define mmRLC_SPM_PERFMON_CNTL__CI__VI                  0xDC80
#define mmRLC_SPM_PERFMON_RING_BASE_HI__CI__VI          0xDC82
#define mmRLC_SPM_PERFMON_RING_BASE_LO__CI__VI          0xDC81
#define mmRLC_SPM_PERFMON_RING_SIZE__CI__VI             0xDC83
#define mmRLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI          0xDC84
#define mmRLC_SPM_RING_RDPTR__CI__VI                    0xDC9D
#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI       0xDC90
#define mmRLC_SPM_SEGMENT_THRESHOLD__CI__VI             0xDC9E
#define mmRLC_SPM_SE_MUXSEL_ADDR__CI__VI                0xDC85
#define mmRLC_SPM_SE_MUXSEL_DATA__CI__VI                0xDC86
#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI      0xDC97
#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI      0xDC98
#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI       0xDC9A
#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI       0xDC94
#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI      0xDC92
#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI      0xDC91
#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI      0xDC93
#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI          0xDC99
#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI       0xDC95
#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI      0xDC96
#define mmRLC_SPM_VMID__CI                              0x3131
#define mmRLC_STATIC_PG_STATUS__CI                      0x312E
#define mmRLC_STAT__CI                                  0x30C4
#define mmRLC_STAT__SI                                  0x30D3
#define mmRLC_THREAD1_DELAY__CI                         0x3112
#define mmRLC_THREAD1_DELAY__SI                         0x310A
#define mmRLC_UCODE_CNTL__CI                            0x30E7
#define mmRLC_UCODE_CNTL__SI                            0x30D2
#define mmROM_CNTL__SI                                  0x0580
#define mmROM_DATA__SI                                  0x002B
#define mmROM_INDEX__SI                                 0x002A
#define mmROM_SMC_IND_DATA__CI__VI                      0x0081
#define mmROM_SMC_IND_INDEX__CI__VI                     0x0080
#define mmROM_START__SI                                 0x0585
#define mmROM_STATUS__SI                                0x0582
#define mmROM_SW_CNTL__SI                               0x0586
#define mmROM_SW_COMMAND__SI                            0x0588
#define mmROM_SW_DATA_10__SI                            0x0592
#define mmROM_SW_DATA_11__SI                            0x0593
#define mmROM_SW_DATA_12__SI                            0x0594
#define mmROM_SW_DATA_13__SI                            0x0595
#define mmROM_SW_DATA_14__SI                            0x0596
#define mmROM_SW_DATA_15__SI                            0x0597
#define mmROM_SW_DATA_16__SI                            0x0598
#define mmROM_SW_DATA_17__SI                            0x0599
#define mmROM_SW_DATA_18__SI                            0x059A
#define mmROM_SW_DATA_19__SI                            0x059B
#define mmROM_SW_DATA_1__SI                             0x0589
#define mmROM_SW_DATA_20__SI                            0x059C
#define mmROM_SW_DATA_21__SI                            0x059D
#define mmROM_SW_DATA_22__SI                            0x059E
#define mmROM_SW_DATA_23__SI                            0x059F
#define mmROM_SW_DATA_24__SI                            0x05A0
#define mmROM_SW_DATA_25__SI                            0x05A1
#define mmROM_SW_DATA_26__SI                            0x05A2
#define mmROM_SW_DATA_27__SI                            0x05A3
#define mmROM_SW_DATA_28__SI                            0x05A4
#define mmROM_SW_DATA_29__SI                            0x05A5
#define mmROM_SW_DATA_2__SI                             0x058A
#define mmROM_SW_DATA_30__SI                            0x05A6
#define mmROM_SW_DATA_31__SI                            0x05A7
#define mmROM_SW_DATA_32__SI                            0x05A8
#define mmROM_SW_DATA_33__SI                            0x05A9
#define mmROM_SW_DATA_34__SI                            0x05AA
#define mmROM_SW_DATA_35__SI                            0x05AB
#define mmROM_SW_DATA_36__SI                            0x05AC
#define mmROM_SW_DATA_37__SI                            0x05AD
#define mmROM_SW_DATA_38__SI                            0x05AE
#define mmROM_SW_DATA_39__SI                            0x05AF
#define mmROM_SW_DATA_3__SI                             0x058B
#define mmROM_SW_DATA_40__SI                            0x05B0
#define mmROM_SW_DATA_41__SI                            0x05B1
#define mmROM_SW_DATA_42__SI                            0x05B2
#define mmROM_SW_DATA_43__SI                            0x05B3
#define mmROM_SW_DATA_44__SI                            0x05B4
#define mmROM_SW_DATA_45__SI                            0x05B5
#define mmROM_SW_DATA_46__SI                            0x05B6
#define mmROM_SW_DATA_47__SI                            0x05B7
#define mmROM_SW_DATA_48__SI                            0x05B8
#define mmROM_SW_DATA_49__SI                            0x05B9
#define mmROM_SW_DATA_4__SI                             0x058C
#define mmROM_SW_DATA_50__SI                            0x05BA
#define mmROM_SW_DATA_51__SI                            0x05BB
#define mmROM_SW_DATA_52__SI                            0x05BC
#define mmROM_SW_DATA_53__SI                            0x05BD
#define mmROM_SW_DATA_54__SI                            0x05BE
#define mmROM_SW_DATA_55__SI                            0x05BF
#define mmROM_SW_DATA_56__SI                            0x05C0
#define mmROM_SW_DATA_57__SI                            0x05C1
#define mmROM_SW_DATA_58__SI                            0x05C2
#define mmROM_SW_DATA_59__SI                            0x05C3
#define mmROM_SW_DATA_5__SI                             0x058D
#define mmROM_SW_DATA_60__SI                            0x05C4
#define mmROM_SW_DATA_61__SI                            0x05C5
#define mmROM_SW_DATA_62__SI                            0x05C6
#define mmROM_SW_DATA_63__SI                            0x05C7
#define mmROM_SW_DATA_64__SI                            0x05C8
#define mmROM_SW_DATA_6__SI                             0x058E
#define mmROM_SW_DATA_7__SI                             0x058F
#define mmROM_SW_DATA_8__SI                             0x0590
#define mmROM_SW_DATA_9__SI                             0x0591
#define mmROM_SW_STATUS__SI                             0x0587
#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT__SI__VI          0x1B5E
#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM__SI__VI          0x1B5F
#define mmSCL0_SCL_ALU_CONTROL__SI__VI                  0x1B54
#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL__SI__VI       0x1B47
#define mmSCL0_SCL_BYPASS_CONTROL__SI__VI               0x1B45
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS__SI__VI     0x1B55
#define mmSCL0_SCL_COEF_RAM_SELECT__SI__VI              0x1B40
#define mmSCL0_SCL_COEF_RAM_TAP_DATA__SI__VI            0x1B41
#define mmSCL0_SCL_CONTROL__SI__VI                      0x1B44
#define mmSCL0_SCL_DEBUG__SI__VI                        0x1B6A
#define mmSCL0_SCL_F_SHARP_CONTROL__SI__VI              0x1B53
#define mmSCL0_SCL_HORZ_FILTER_CONTROL__SI              0x1B4A
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SI          0x1B4B
#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL__SI__VI     0x1B46
#define mmSCL0_SCL_MODE_CHANGE_DET1__SI__VI             0x1B60
#define mmSCL0_SCL_MODE_CHANGE_DET2__SI__VI             0x1B61
#define mmSCL0_SCL_MODE_CHANGE_DET3__SI__VI             0x1B62
#define mmSCL0_SCL_MODE_CHANGE_MASK__SI__VI             0x1B63
#define mmSCL0_SCL_TAP_CONTROL__SI__VI                  0x1B43
#define mmSCL0_SCL_TEST_DEBUG_DATA__SI__VI              0x1B6C
#define mmSCL0_SCL_TEST_DEBUG_INDEX__SI__VI             0x1B6B
#define mmSCL0_SCL_UPDATE__SI__VI                       0x1B51
#define mmSCL0_SCL_VERT_FILTER_CONTROL__SI              0x1B4E
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT__SI             0x1B57
#define mmSCL0_SCL_VERT_FILTER_INIT__SI                 0x1B50
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO__SI          0x1B4F
#define mmSCL0_VIEWPORT_SIZE__SI__VI                    0x1B5D
#define mmSCL0_VIEWPORT_START__SI__VI                   0x1B5C
#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT__SI              0x1E5E
#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM__SI              0x1E5F
#define mmSCL1_SCL_ALU_CONTROL__SI                      0x1E54
#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL__SI           0x1E47
#define mmSCL1_SCL_BYPASS_CONTROL__SI                   0x1E45
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS__SI         0x1E55
#define mmSCL1_SCL_COEF_RAM_SELECT__SI                  0x1E40
#define mmSCL1_SCL_COEF_RAM_TAP_DATA__SI                0x1E41
#define mmSCL1_SCL_CONTROL__SI                          0x1E44
#define mmSCL1_SCL_DEBUG__SI                            0x1E6A
#define mmSCL1_SCL_F_SHARP_CONTROL__SI                  0x1E53
#define mmSCL1_SCL_HORZ_FILTER_CONTROL__SI              0x1E4A
#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SI          0x1E4B
#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL__SI         0x1E46
#define mmSCL1_SCL_MODE_CHANGE_DET1__SI                 0x1E60
#define mmSCL1_SCL_MODE_CHANGE_DET2__SI                 0x1E61
#define mmSCL1_SCL_MODE_CHANGE_DET3__SI                 0x1E62
#define mmSCL1_SCL_MODE_CHANGE_MASK__SI                 0x1E63
#define mmSCL1_SCL_TAP_CONTROL__SI                      0x1E43
#define mmSCL1_SCL_TEST_DEBUG_DATA__SI                  0x1E6C
#define mmSCL1_SCL_TEST_DEBUG_INDEX__SI                 0x1E6B
#define mmSCL1_SCL_UPDATE__SI                           0x1E51
#define mmSCL1_SCL_VERT_FILTER_CONTROL__SI              0x1E4E
#define mmSCL1_SCL_VERT_FILTER_INIT_BOT__SI             0x1E57
#define mmSCL1_SCL_VERT_FILTER_INIT__SI                 0x1E50
#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO__SI          0x1E4F
#define mmSCL1_VIEWPORT_SIZE__SI                        0x1E5D
#define mmSCL1_VIEWPORT_START__SI                       0x1E5C
#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT__SI              0x415E
#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM__SI              0x415F
#define mmSCL2_SCL_ALU_CONTROL__SI                      0x4154
#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL__SI           0x4147
#define mmSCL2_SCL_BYPASS_CONTROL__SI                   0x4145
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS__SI         0x4155
#define mmSCL2_SCL_COEF_RAM_SELECT__SI                  0x4140
#define mmSCL2_SCL_COEF_RAM_TAP_DATA__SI                0x4141
#define mmSCL2_SCL_CONTROL__SI                          0x4144
#define mmSCL2_SCL_DEBUG__SI                            0x416A
#define mmSCL2_SCL_F_SHARP_CONTROL__SI                  0x4153
#define mmSCL2_SCL_HORZ_FILTER_CONTROL__SI              0x414A
#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SI          0x414B
#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL__SI         0x4146
#define mmSCL2_SCL_MODE_CHANGE_DET1__SI                 0x4160
#define mmSCL2_SCL_MODE_CHANGE_DET2__SI                 0x4161
#define mmSCL2_SCL_MODE_CHANGE_DET3__SI                 0x4162
#define mmSCL2_SCL_MODE_CHANGE_MASK__SI                 0x4163
#define mmSCL2_SCL_TAP_CONTROL__SI                      0x4143
#define mmSCL2_SCL_TEST_DEBUG_DATA__SI                  0x416C
#define mmSCL2_SCL_TEST_DEBUG_INDEX__SI                 0x416B
#define mmSCL2_SCL_UPDATE__SI                           0x4151
#define mmSCL2_SCL_VERT_FILTER_CONTROL__SI              0x414E
#define mmSCL2_SCL_VERT_FILTER_INIT_BOT__SI             0x4157
#define mmSCL2_SCL_VERT_FILTER_INIT__SI                 0x4150
#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO__SI          0x414F
#define mmSCL2_VIEWPORT_SIZE__SI                        0x415D
#define mmSCL2_VIEWPORT_START__SI                       0x415C
#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT__SI              0x445E
#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM__SI              0x445F
#define mmSCL3_SCL_ALU_CONTROL__SI                      0x4454
#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL__SI           0x4447
#define mmSCL3_SCL_BYPASS_CONTROL__SI                   0x4445
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS__SI         0x4455
#define mmSCL3_SCL_COEF_RAM_SELECT__SI                  0x4440
#define mmSCL3_SCL_COEF_RAM_TAP_DATA__SI                0x4441
#define mmSCL3_SCL_CONTROL__SI                          0x4444
#define mmSCL3_SCL_DEBUG__SI                            0x446A
#define mmSCL3_SCL_F_SHARP_CONTROL__SI                  0x4453
#define mmSCL3_SCL_HORZ_FILTER_CONTROL__SI              0x444A
#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SI          0x444B
#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL__SI         0x4446
#define mmSCL3_SCL_MODE_CHANGE_DET1__SI                 0x4460
#define mmSCL3_SCL_MODE_CHANGE_DET2__SI                 0x4461
#define mmSCL3_SCL_MODE_CHANGE_DET3__SI                 0x4462
#define mmSCL3_SCL_MODE_CHANGE_MASK__SI                 0x4463
#define mmSCL3_SCL_TAP_CONTROL__SI                      0x4443
#define mmSCL3_SCL_TEST_DEBUG_DATA__SI                  0x446C
#define mmSCL3_SCL_TEST_DEBUG_INDEX__SI                 0x446B
#define mmSCL3_SCL_UPDATE__SI                           0x4451
#define mmSCL3_SCL_VERT_FILTER_CONTROL__SI              0x444E
#define mmSCL3_SCL_VERT_FILTER_INIT_BOT__SI             0x4457
#define mmSCL3_SCL_VERT_FILTER_INIT__SI                 0x4450
#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO__SI          0x444F
#define mmSCL3_VIEWPORT_SIZE__SI                        0x445D
#define mmSCL3_VIEWPORT_START__SI                       0x445C
#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT__SI              0x475E
#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM__SI              0x475F
#define mmSCL4_SCL_ALU_CONTROL__SI                      0x4754
#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL__SI           0x4747
#define mmSCL4_SCL_BYPASS_CONTROL__SI                   0x4745
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS__SI         0x4755
#define mmSCL4_SCL_COEF_RAM_SELECT__SI                  0x4740
#define mmSCL4_SCL_COEF_RAM_TAP_DATA__SI                0x4741
#define mmSCL4_SCL_CONTROL__SI                          0x4744
#define mmSCL4_SCL_DEBUG__SI                            0x476A
#define mmSCL4_SCL_F_SHARP_CONTROL__SI                  0x4753
#define mmSCL4_SCL_HORZ_FILTER_CONTROL__SI              0x474A
#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SI          0x474B
#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL__SI         0x4746
#define mmSCL4_SCL_MODE_CHANGE_DET1__SI                 0x4760
#define mmSCL4_SCL_MODE_CHANGE_DET2__SI                 0x4761
#define mmSCL4_SCL_MODE_CHANGE_DET3__SI                 0x4762
#define mmSCL4_SCL_MODE_CHANGE_MASK__SI                 0x4763
#define mmSCL4_SCL_TAP_CONTROL__SI                      0x4743
#define mmSCL4_SCL_TEST_DEBUG_DATA__SI                  0x476C
#define mmSCL4_SCL_TEST_DEBUG_INDEX__SI                 0x476B
#define mmSCL4_SCL_UPDATE__SI                           0x4751
#define mmSCL4_SCL_VERT_FILTER_CONTROL__SI              0x474E
#define mmSCL4_SCL_VERT_FILTER_INIT_BOT__SI             0x4757
#define mmSCL4_SCL_VERT_FILTER_INIT__SI                 0x4750
#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO__SI          0x474F
#define mmSCL4_VIEWPORT_SIZE__SI                        0x475D
#define mmSCL4_VIEWPORT_START__SI                       0x475C
#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT__SI              0x4A5E
#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM__SI              0x4A5F
#define mmSCL5_SCL_ALU_CONTROL__SI                      0x4A54
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL__SI           0x4A47
#define mmSCL5_SCL_BYPASS_CONTROL__SI                   0x4A45
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS__SI         0x4A55
#define mmSCL5_SCL_COEF_RAM_SELECT__SI                  0x4A40
#define mmSCL5_SCL_COEF_RAM_TAP_DATA__SI                0x4A41
#define mmSCL5_SCL_CONTROL__SI                          0x4A44
#define mmSCL5_SCL_DEBUG__SI                            0x4A6A
#define mmSCL5_SCL_F_SHARP_CONTROL__SI                  0x4A53
#define mmSCL5_SCL_HORZ_FILTER_CONTROL__SI              0x4A4A
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SI          0x4A4B
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL__SI         0x4A46
#define mmSCL5_SCL_MODE_CHANGE_DET1__SI                 0x4A60
#define mmSCL5_SCL_MODE_CHANGE_DET2__SI                 0x4A61
#define mmSCL5_SCL_MODE_CHANGE_DET3__SI                 0x4A62
#define mmSCL5_SCL_MODE_CHANGE_MASK__SI                 0x4A63
#define mmSCL5_SCL_TAP_CONTROL__SI                      0x4A43
#define mmSCL5_SCL_TEST_DEBUG_DATA__SI                  0x4A6C
#define mmSCL5_SCL_TEST_DEBUG_INDEX__SI                 0x4A6B
#define mmSCL5_SCL_UPDATE__SI                           0x4A51
#define mmSCL5_SCL_VERT_FILTER_CONTROL__SI              0x4A4E
#define mmSCL5_SCL_VERT_FILTER_INIT_BOT__SI             0x4A57
#define mmSCL5_SCL_VERT_FILTER_INIT__SI                 0x4A50
#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO__SI          0x4A4F
#define mmSCL5_VIEWPORT_SIZE__SI                        0x4A5D
#define mmSCL5_VIEWPORT_START__SI                       0x4A5C
#define mmSCLK_CGTT_BLK_CTRL_REG__SI                    0x0129
#define mmSCLK_PWRMGT_CNTL__SI                          0x01E2
#define mmSCL_ALU_CONTROL__SI__VI                       0x1B54
#define mmSCL_AUTOMATIC_MODE_CONTROL__SI__VI            0x1B47
#define mmSCL_BYPASS_CONTROL__SI__VI                    0x1B45
#define mmSCL_COEF_RAM_CONFLICT_STATUS__SI__VI          0x1B55
#define mmSCL_COEF_RAM_SELECT__SI__VI                   0x1B40
#define mmSCL_COEF_RAM_TAP_DATA__SI__VI                 0x1B41
#define mmSCL_CONTROL__SI__VI                           0x1B44
#define mmSCL_DEBUG__SI__VI                             0x1B6A
#define mmSCL_F_SHARP_CONTROL__SI__VI                   0x1B53
#define mmSCL_HORZ_FILTER_CONTROL__SI                   0x1B4A
#define mmSCL_HORZ_FILTER_SCALE_RATIO__SI               0x1B4B
#define mmSCL_MANUAL_REPLICATE_CONTROL__SI__VI          0x1B46
#define mmSCL_MODE_CHANGE_DET1__SI__VI                  0x1B60
#define mmSCL_MODE_CHANGE_DET2__SI__VI                  0x1B61
#define mmSCL_MODE_CHANGE_DET3__SI__VI                  0x1B62
#define mmSCL_MODE_CHANGE_MASK__SI__VI                  0x1B63
#define mmSCL_TAP_CONTROL__SI__VI                       0x1B43
#define mmSCL_TEST_DEBUG_DATA__SI__VI                   0x1B6C
#define mmSCL_TEST_DEBUG_INDEX__SI__VI                  0x1B6B
#define mmSCL_UPDATE__SI__VI                            0x1B51
#define mmSCL_VERT_FILTER_CONTROL__SI                   0x1B4E
#define mmSCL_VERT_FILTER_INIT_BOT__SI                  0x1B57
#define mmSCL_VERT_FILTER_INIT__SI                      0x1B50
#define mmSCL_VERT_FILTER_SCALE_RATIO__SI               0x1B4F
#define mmSCRATCH_ADDR__CI__VI                          0xC051
#define mmSCRATCH_ADDR__SI                              0x2151
#define mmSCRATCH_REG0__CI__VI                          0xC040
#define mmSCRATCH_REG0__SI                              0x2140
#define mmSCRATCH_REG1__CI__VI                          0xC041
#define mmSCRATCH_REG1__SI                              0x2141
#define mmSCRATCH_REG2__CI__VI                          0xC042
#define mmSCRATCH_REG2__SI                              0x2142
#define mmSCRATCH_REG3__CI__VI                          0xC043
#define mmSCRATCH_REG3__SI                              0x2143
#define mmSCRATCH_REG4__CI__VI                          0xC044
#define mmSCRATCH_REG4__SI                              0x2144
#define mmSCRATCH_REG5__CI__VI                          0xC045
#define mmSCRATCH_REG5__SI                              0x2145
#define mmSCRATCH_REG6__CI__VI                          0xC046
#define mmSCRATCH_REG6__SI                              0x2146
#define mmSCRATCH_REG7__CI__VI                          0xC047
#define mmSCRATCH_REG7__SI                              0x2147
#define mmSCRATCH_UMSK__CI__VI                          0xC050
#define mmSCRATCH_UMSK__SI                              0x2150
#define mmSDMA0_CHICKEN_BITS__CI__VI                    0x3405
#define mmSDMA0_CLK_CTRL__CI__VI                        0x3403
#define mmSDMA0_CNTL__CI__VI                            0x3404
#define mmSDMA0_F32_CNTL__CI__VI                        0x3412
#define mmSDMA0_FREEZE__CI__VI                          0x3413
#define mmSDMA0_GFX_APE1_CNTL__CI__VI                   0x34A8
#define mmSDMA0_GFX_CONTEXT_CNTL__CI__VI                0x3493
#define mmSDMA0_GFX_CONTEXT_STATUS__CI__VI              0x3491
#define mmSDMA0_GFX_IB_BASE_HI__CI__VI                  0x348E
#define mmSDMA0_GFX_IB_BASE_LO__CI__VI                  0x348D
#define mmSDMA0_GFX_IB_CNTL__CI__VI                     0x348A
#define mmSDMA0_GFX_IB_OFFSET__CI__VI                   0x348C
#define mmSDMA0_GFX_IB_RPTR__CI__VI                     0x348B
#define mmSDMA0_GFX_IB_SIZE__CI__VI                     0x348F
#define mmSDMA0_GFX_RB_BASE_HI__CI__VI                  0x3482
#define mmSDMA0_GFX_RB_BASE__CI__VI                     0x3481
#define mmSDMA0_GFX_RB_CNTL__CI__VI                     0x3480
#define mmSDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI             0x3488
#define mmSDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI             0x3489
#define mmSDMA0_GFX_RB_RPTR__CI__VI                     0x3483
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI        0x3486
#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI        0x3487
#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI           0x3485
#define mmSDMA0_GFX_RB_WPTR__CI__VI                     0x3484
#define mmSDMA0_GFX_SKIP_CNTL__CI__VI                   0x3490
#define mmSDMA0_GFX_VIRTUAL_ADDR__CI__VI                0x34A7
#define mmSDMA0_HASH__CI__VI                            0x3407
#define mmSDMA0_IB_OFFSET_FETCH__CI__VI                 0x340B
#define mmSDMA0_PERFCOUNTER0_RESULT__CI                 0x3410
#define mmSDMA0_PERFCOUNTER1_RESULT__CI                 0x3411
#define mmSDMA0_PERFMON_CNTL__CI                        0x340F
#define mmSDMA0_PHASE0_QUANTUM__CI__VI                  0x3414
#define mmSDMA0_PHASE1_QUANTUM__CI__VI                  0x3415
#define mmSDMA0_POWER_CNTL__CI__VI                      0x3402
#define mmSDMA0_PROGRAM__CI__VI                         0x340C
#define mmSDMA0_RB_RPTR_FETCH__CI__VI                   0x340A
#define mmSDMA0_RLC0_APE1_CNTL__CI__VI                  0x3528
#define mmSDMA0_RLC0_CONTEXT_STATUS__CI__VI             0x3511
#define mmSDMA0_RLC0_DOORBELL_LOG__CI__VI               0x3529
#define mmSDMA0_RLC0_DOORBELL__CI__VI                   0x3512
#define mmSDMA0_RLC0_IB_BASE_HI__CI__VI                 0x350E
#define mmSDMA0_RLC0_IB_BASE_LO__CI__VI                 0x350D
#define mmSDMA0_RLC0_IB_CNTL__CI__VI                    0x350A
#define mmSDMA0_RLC0_IB_OFFSET__CI__VI                  0x350C
#define mmSDMA0_RLC0_IB_RPTR__CI__VI                    0x350B
#define mmSDMA0_RLC0_IB_SIZE__CI__VI                    0x350F
#define mmSDMA0_RLC0_RB_BASE_HI__CI__VI                 0x3502
#define mmSDMA0_RLC0_RB_BASE__CI__VI                    0x3501
#define mmSDMA0_RLC0_RB_CNTL__CI__VI                    0x3500
#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI            0x3508
#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI            0x3509
#define mmSDMA0_RLC0_RB_RPTR__CI__VI                    0x3503
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI       0x3506
#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI       0x3507
#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI          0x3505
#define mmSDMA0_RLC0_RB_WPTR__CI__VI                    0x3504
#define mmSDMA0_RLC0_SKIP_CNTL__CI__VI                  0x3510
#define mmSDMA0_RLC0_VIRTUAL_ADDR__CI__VI               0x3527
#define mmSDMA0_RLC1_APE1_CNTL__CI__VI                  0x35A8
#define mmSDMA0_RLC1_CONTEXT_STATUS__CI__VI             0x3591
#define mmSDMA0_RLC1_DOORBELL_LOG__CI__VI               0x35A9
#define mmSDMA0_RLC1_DOORBELL__CI__VI                   0x3592
#define mmSDMA0_RLC1_IB_BASE_HI__CI__VI                 0x358E
#define mmSDMA0_RLC1_IB_BASE_LO__CI__VI                 0x358D
#define mmSDMA0_RLC1_IB_CNTL__CI__VI                    0x358A
#define mmSDMA0_RLC1_IB_OFFSET__CI__VI                  0x358C
#define mmSDMA0_RLC1_IB_RPTR__CI__VI                    0x358B
#define mmSDMA0_RLC1_IB_SIZE__CI__VI                    0x358F
#define mmSDMA0_RLC1_RB_BASE_HI__CI__VI                 0x3582
#define mmSDMA0_RLC1_RB_BASE__CI__VI                    0x3581
#define mmSDMA0_RLC1_RB_CNTL__CI__VI                    0x3580
#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI            0x3588
#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI            0x3589
#define mmSDMA0_RLC1_RB_RPTR__CI__VI                    0x3583
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI       0x3586
#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI       0x3587
#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI          0x3585
#define mmSDMA0_RLC1_RB_WPTR__CI__VI                    0x3584
#define mmSDMA0_RLC1_SKIP_CNTL__CI__VI                  0x3590
#define mmSDMA0_RLC1_VIRTUAL_ADDR__CI__VI               0x35A7
#define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI           0x3408
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI        0x3409
#define mmSDMA0_STATUS1_REG__CI__VI                     0x340E
#define mmSDMA0_STATUS_REG__CI__VI                      0x340D
#define mmSDMA0_TILING_CONFIG__CI__VI                   0x3406
#define mmSDMA0_UCODE_ADDR__CI__VI                      0x3400
#define mmSDMA0_UCODE_DATA__CI__VI                      0x3401
#define mmSDMA1_CHICKEN_BITS__CI__VI                    0x3605
#define mmSDMA1_CLK_CTRL__CI__VI                        0x3603
#define mmSDMA1_CNTL__CI__VI                            0x3604
#define mmSDMA1_CONFIG__CI__VI                          0x0F92
#define mmSDMA1_F32_CNTL__CI__VI                        0x3612
#define mmSDMA1_FREEZE__CI__VI                          0x3613
#define mmSDMA1_GFX_APE1_CNTL__CI__VI                   0x36A8
#define mmSDMA1_GFX_CONTEXT_CNTL__CI__VI                0x3693
#define mmSDMA1_GFX_CONTEXT_STATUS__CI__VI              0x3691
#define mmSDMA1_GFX_IB_BASE_HI__CI__VI                  0x368E
#define mmSDMA1_GFX_IB_BASE_LO__CI__VI                  0x368D
#define mmSDMA1_GFX_IB_CNTL__CI__VI                     0x368A
#define mmSDMA1_GFX_IB_OFFSET__CI__VI                   0x368C
#define mmSDMA1_GFX_IB_RPTR__CI__VI                     0x368B
#define mmSDMA1_GFX_IB_SIZE__CI__VI                     0x368F
#define mmSDMA1_GFX_RB_BASE_HI__CI__VI                  0x3682
#define mmSDMA1_GFX_RB_BASE__CI__VI                     0x3681
#define mmSDMA1_GFX_RB_CNTL__CI__VI                     0x3680
#define mmSDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI             0x3688
#define mmSDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI             0x3689
#define mmSDMA1_GFX_RB_RPTR__CI__VI                     0x3683
#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI        0x3686
#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI        0x3687
#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI           0x3685
#define mmSDMA1_GFX_RB_WPTR__CI__VI                     0x3684
#define mmSDMA1_GFX_SKIP_CNTL__CI__VI                   0x3690
#define mmSDMA1_GFX_VIRTUAL_ADDR__CI__VI                0x36A7
#define mmSDMA1_HASH__CI__VI                            0x3607
#define mmSDMA1_IB_OFFSET_FETCH__CI__VI                 0x360B
#define mmSDMA1_PERFCOUNTER0_RESULT__CI                 0x3610
#define mmSDMA1_PERFCOUNTER1_RESULT__CI                 0x3611
#define mmSDMA1_PERFMON_CNTL__CI                        0x360F
#define mmSDMA1_PHASE0_QUANTUM__CI__VI                  0x3614
#define mmSDMA1_PHASE1_QUANTUM__CI__VI                  0x3615
#define mmSDMA1_POWER_CNTL__CI__VI                      0x3602
#define mmSDMA1_PROGRAM__CI__VI                         0x360C
#define mmSDMA1_RB_RPTR_FETCH__CI__VI                   0x360A
#define mmSDMA1_RLC0_APE1_CNTL__CI__VI                  0x3728
#define mmSDMA1_RLC0_CONTEXT_STATUS__CI__VI             0x3711
#define mmSDMA1_RLC0_DOORBELL_LOG__CI__VI               0x3729
#define mmSDMA1_RLC0_DOORBELL__CI__VI                   0x3712
#define mmSDMA1_RLC0_IB_BASE_HI__CI__VI                 0x370E
#define mmSDMA1_RLC0_IB_BASE_LO__CI__VI                 0x370D
#define mmSDMA1_RLC0_IB_CNTL__CI__VI                    0x370A
#define mmSDMA1_RLC0_IB_OFFSET__CI__VI                  0x370C
#define mmSDMA1_RLC0_IB_RPTR__CI__VI                    0x370B
#define mmSDMA1_RLC0_IB_SIZE__CI__VI                    0x370F
#define mmSDMA1_RLC0_RB_BASE_HI__CI__VI                 0x3702
#define mmSDMA1_RLC0_RB_BASE__CI__VI                    0x3701
#define mmSDMA1_RLC0_RB_CNTL__CI__VI                    0x3700
#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI            0x3708
#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI            0x3709
#define mmSDMA1_RLC0_RB_RPTR__CI__VI                    0x3703
#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI       0x3706
#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI       0x3707
#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI          0x3705
#define mmSDMA1_RLC0_RB_WPTR__CI__VI                    0x3704
#define mmSDMA1_RLC0_SKIP_CNTL__CI__VI                  0x3710
#define mmSDMA1_RLC0_VIRTUAL_ADDR__CI__VI               0x3727
#define mmSDMA1_RLC1_APE1_CNTL__CI__VI                  0x37A8
#define mmSDMA1_RLC1_CONTEXT_STATUS__CI__VI             0x3791
#define mmSDMA1_RLC1_DOORBELL_LOG__CI__VI               0x37A9
#define mmSDMA1_RLC1_DOORBELL__CI__VI                   0x3792
#define mmSDMA1_RLC1_IB_BASE_HI__CI__VI                 0x378E
#define mmSDMA1_RLC1_IB_BASE_LO__CI__VI                 0x378D
#define mmSDMA1_RLC1_IB_CNTL__CI__VI                    0x378A
#define mmSDMA1_RLC1_IB_OFFSET__CI__VI                  0x378C
#define mmSDMA1_RLC1_IB_RPTR__CI__VI                    0x378B
#define mmSDMA1_RLC1_IB_SIZE__CI__VI                    0x378F
#define mmSDMA1_RLC1_RB_BASE_HI__CI__VI                 0x3782
#define mmSDMA1_RLC1_RB_BASE__CI__VI                    0x3781
#define mmSDMA1_RLC1_RB_CNTL__CI__VI                    0x3780
#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI            0x3788
#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI            0x3789
#define mmSDMA1_RLC1_RB_RPTR__CI__VI                    0x3783
#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI       0x3786
#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI       0x3787
#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI          0x3785
#define mmSDMA1_RLC1_RB_WPTR__CI__VI                    0x3784
#define mmSDMA1_RLC1_SKIP_CNTL__CI__VI                  0x3790
#define mmSDMA1_RLC1_VIRTUAL_ADDR__CI__VI               0x37A7
#define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI           0x3608
#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI        0x3609
#define mmSDMA1_STATUS1_REG__CI__VI                     0x360E
#define mmSDMA1_STATUS_REG__CI__VI                      0x360D
#define mmSDMA1_TILING_CONFIG__CI__VI                   0x3606
#define mmSDMA1_UCODE_ADDR__CI__VI                      0x3600
#define mmSDMA1_UCODE_DATA__CI__VI                      0x3601
#define mmSDMA_CONFIG__CI__VI                           0x0F91
#define mmSDMA_PGFSM_CONFIG__CI__VI                     0x3417
#define mmSDMA_PGFSM_READ__CI__VI                       0x3419
#define mmSDMA_PGFSM_WRITE__CI__VI                      0x3418
#define mmSDMA_POWER_GATING__CI__VI                     0x3416
#define mmSEM_CHICKEN_BITS__CI__VI                      0x0F9E
#define mmSEM_EDC_CONFIG__CI__VI                        0x0F9A
#define mmSEM_MAILBOX_CLIENTCONFIG__CI__VI              0x0F9B
#define mmSEM_MAILBOX_CLIENTCONFIG__SI                  0x0F9A
#define mmSEM_MAILBOX_CONTROL__CI__VI                   0x0F9D
#define mmSEM_MAILBOX_CONTROL__SI                       0x0F9C
#define mmSEM_MAILBOX__CI__VI                           0x0F9C
#define mmSEM_MAILBOX__SI                               0x0F9B
#define mmSEM_MCIF_CONFIG                               0x0F90
#define mmSEM_STATUS__CI__VI                            0x0F99
#define mmSEQ8_DATA__SI__VI                             0x00F1
#define mmSEQ8_IDX__SI__VI                              0x00F1
#define mmSH_HIDDEN_PRIVATE_BASE_VMID__CI__VI           0x2580
#define mmSH_MEM_APE1_BASE__CI__VI                      0x230B
#define mmSH_MEM_APE1_LIMIT__CI__VI                     0x230C
#define mmSH_MEM_BASES__CI__VI                          0x230A
#define mmSH_MEM_CONFIG__CI__VI                         0x230D
#define mmSH_STATIC_MEM_CONFIG__CI__VI                  0x2581
#define mmSLAVE_COMM_CMD_REG__SI__VI                    0x1624
#define mmSLAVE_COMM_CNTL_REG__SI__VI                   0x1625
#define mmSLAVE_COMM_DATA_REG1__SI__VI                  0x1621
#define mmSLAVE_COMM_DATA_REG2__SI__VI                  0x1622
#define mmSLAVE_COMM_DATA_REG3__SI__VI                  0x1623
#define mmSLAVE_HANG_ERROR                              0x153B
#define mmSLAVE_HANG_PROTECTION_CNTL                    0x1536
#define mmSLAVE_REQ_CREDIT_CNTL                         0x1517
#define mmSMBCLK_PAD_CNTL__CI                           0x1523
#define mmSMBDAT_PAD_CNTL__CI                           0x1522
#define mmSMBUS_SLV_CNTL__CI                            0x14FD
#define mmSMC_IND_ACCESS_CNTL__CI__VI                   0x0090
#define mmSMC_IND_ACCESS_CNTL__SI                       0x008A
#define mmSMC_IND_DATA                                  0x0081
#define mmSMC_IND_DATA_0__CI__VI                        0x0081
#define mmSMC_IND_DATA_1__CI__VI                        0x0083
#define mmSMC_IND_DATA_2__CI__VI                        0x0085
#define mmSMC_IND_DATA_3__CI__VI                        0x0087
#define mmSMC_IND_DATA_4__CI__VI                        0x0089
#define mmSMC_IND_DATA_5__CI__VI                        0x008B
#define mmSMC_IND_DATA_6__CI__VI                        0x008D
#define mmSMC_IND_DATA_7__CI__VI                        0x008F
#define mmSMC_IND_INDEX                                 0x0080
#define mmSMC_IND_INDEX_0__CI__VI                       0x0080
#define mmSMC_IND_INDEX_1__CI__VI                       0x0082
#define mmSMC_IND_INDEX_2__CI__VI                       0x0084
#define mmSMC_IND_INDEX_3__CI__VI                       0x0086
#define mmSMC_IND_INDEX_4__CI__VI                       0x0088
#define mmSMC_IND_INDEX_5__CI__VI                       0x008A
#define mmSMC_IND_INDEX_6__CI__VI                       0x008C
#define mmSMC_IND_INDEX_7__CI__VI                       0x008E
#define mmSMC_MESSAGE_0__CI__VI                         0x0094
#define mmSMC_MESSAGE_0__SI                             0x008B
#define mmSMC_MESSAGE_10__CI__VI                        0x00B9
#define mmSMC_MESSAGE_11__CI__VI                        0x00BB
#define mmSMC_MESSAGE_1__CI__VI                         0x0096
#define mmSMC_MESSAGE_1__SI                             0x008D
#define mmSMC_MESSAGE_2__CI__VI                         0x0098
#define mmSMC_MESSAGE_3__CI__VI                         0x009A
#define mmSMC_MESSAGE_4__CI__VI                         0x009C
#define mmSMC_MESSAGE_5__CI__VI                         0x009E
#define mmSMC_MESSAGE_6__CI__VI                         0x00A0
#define mmSMC_MESSAGE_7__CI__VI                         0x00A2
#define mmSMC_MESSAGE_8__CI__VI                         0x00B5
#define mmSMC_MESSAGE_9__CI__VI                         0x00B7
#define mmSMC_MSG_ARG_0__CI__VI                         0x00A4
#define mmSMC_MSG_ARG_10__CI__VI                        0x00BF
#define mmSMC_MSG_ARG_11__CI                            0x0091
#define mmSMC_MSG_ARG_1__CI__VI                         0x00A5
#define mmSMC_MSG_ARG_2__CI__VI                         0x00A6
#define mmSMC_MSG_ARG_3__CI__VI                         0x00A7
#define mmSMC_MSG_ARG_4__CI__VI                         0x00A8
#define mmSMC_MSG_ARG_5__CI__VI                         0x00A9
#define mmSMC_MSG_ARG_6__CI__VI                         0x00AA
#define mmSMC_MSG_ARG_7__CI__VI                         0x00AB
#define mmSMC_MSG_ARG_8__CI__VI                         0x00BD
#define mmSMC_MSG_ARG_9__CI__VI                         0x00BE
#define mmSMC_RESP_0__CI__VI                            0x0095
#define mmSMC_RESP_0__SI                                0x008C
#define mmSMC_RESP_10__CI__VI                           0x00BA
#define mmSMC_RESP_11__CI__VI                           0x00BC
#define mmSMC_RESP_1__CI__VI                            0x0097
#define mmSMC_RESP_1__SI                                0x008E
#define mmSMC_RESP_2__CI__VI                            0x0099
#define mmSMC_RESP_3__CI__VI                            0x009B
#define mmSMC_RESP_4__CI__VI                            0x009D
#define mmSMC_RESP_5__CI__VI                            0x009F
#define mmSMC_RESP_6__CI__VI                            0x00A1
#define mmSMC_RESP_7__CI__VI                            0x00A3
#define mmSMC_RESP_8__CI__VI                            0x00B6
#define mmSMC_RESP_9__CI__VI                            0x00B8
#define mmSMC_SCRATCH9__SI                              0x022A
#define mmSMU_SMC_IND_DATA__CI__VI                      0x0081
#define mmSMU_SMC_IND_INDEX__CI__VI                     0x0080
#define mmSPI_ARB_CYCLES_0__CI__VI                      0x31C1
#define mmSPI_ARB_CYCLES_0__SI                          0x243D
#define mmSPI_ARB_CYCLES_1__CI__VI                      0x31C2
#define mmSPI_ARB_CYCLES_1__SI                          0x243E
#define mmSPI_ARB_PRIORITY__CI__VI                      0x31C0
#define mmSPI_ARB_PRIORITY__SI                          0x243C
#define mmSPI_BARYC_CNTL                                0xA1B8
#define mmSPI_CDBG_SYS_CS0__CI__VI                      0x31C5
#define mmSPI_CDBG_SYS_CS1__CI__VI                      0x31C6
#define mmSPI_CDBG_SYS_GFX__CI__VI                      0x31C3
#define mmSPI_CDBG_SYS_HP3D__CI__VI                     0x31C4
#define mmSPI_COMPUTE_QUEUE_RESET__CI__VI               0x31DB
#define mmSPI_CONFIG_CNTL                               0x2440
#define mmSPI_CONFIG_CNTL_1                             0x244F
#define mmSPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI             0x24DC
#define mmSPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI             0x24DD
#define mmSPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI             0x24DE
#define mmSPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI             0x24DF
#define mmSPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI             0x24E0
#define mmSPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI             0x24E1
#define mmSPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI             0x24E2
#define mmSPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI             0x24E3
#define mmSPI_CSQ_WF_ACTIVE_STATUS__CI__VI              0x24DB
#define mmSPI_DEBUG_BUSY                                0x2450
#define mmSPI_DEBUG_CNTL                                0x2441
#define mmSPI_DEBUG_READ                                0x2442
#define mmSPI_GDBG_TBA_HI__CI__VI                       0x31D5
#define mmSPI_GDBG_TBA_LO__CI__VI                       0x31D4
#define mmSPI_GDBG_TMA_HI__CI__VI                       0x31D7
#define mmSPI_GDBG_TMA_LO__CI__VI                       0x31D6
#define mmSPI_GDBG_TRAP_CONFIG__CI__VI                  0x31D2
#define mmSPI_GDBG_TRAP_DATA0__CI__VI                   0x31D8
#define mmSPI_GDBG_TRAP_DATA1__CI__VI                   0x31D9
#define mmSPI_GDBG_TRAP_MASK__CI__VI                    0x31D3
#define mmSPI_GDBG_WAVE_CNTL__CI__VI                    0x31D1
#define mmSPI_GDS_CREDITS                               0x24D8
#define mmSPI_INTERP_CONTROL_0                          0xA1B5
#define mmSPI_LB_CTR_CTRL                               0x24D4
#define mmSPI_LB_CU_MASK                                0x24D5
#define mmSPI_LB_DATA_REG                               0x24D6
#define mmSPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI            0x24F0
#define mmSPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI            0x24ED
#define mmSPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI            0x24EC
#define mmSPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI            0x24EF
#define mmSPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI            0x24EE
#define mmSPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI            0x24F5
#define mmSPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI            0x24F2
#define mmSPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI            0x24F1
#define mmSPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI            0x24F4
#define mmSPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI            0x24F3
#define mmSPI_PERFCOUNTER0_HI__CI__VI                   0xD180
#define mmSPI_PERFCOUNTER0_HI__SI                       0x2447
#define mmSPI_PERFCOUNTER0_LO__CI__VI                   0xD181
#define mmSPI_PERFCOUNTER0_LO__SI                       0x2448
#define mmSPI_PERFCOUNTER0_SELECT1__CI__VI              0xD984
#define mmSPI_PERFCOUNTER0_SELECT__CI__VI               0xD980
#define mmSPI_PERFCOUNTER0_SELECT__SI                   0x2443
#define mmSPI_PERFCOUNTER1_HI__CI__VI                   0xD182
#define mmSPI_PERFCOUNTER1_HI__SI                       0x2449
#define mmSPI_PERFCOUNTER1_LO__CI__VI                   0xD183
#define mmSPI_PERFCOUNTER1_LO__SI                       0x244A
#define mmSPI_PERFCOUNTER1_SELECT1__CI__VI              0xD985
#define mmSPI_PERFCOUNTER1_SELECT__CI__VI               0xD981
#define mmSPI_PERFCOUNTER1_SELECT__SI                   0x2444
#define mmSPI_PERFCOUNTER2_HI__CI__VI                   0xD184
#define mmSPI_PERFCOUNTER2_HI__SI                       0x244B
#define mmSPI_PERFCOUNTER2_LO__CI__VI                   0xD185
#define mmSPI_PERFCOUNTER2_LO__SI                       0x244C
#define mmSPI_PERFCOUNTER2_SELECT1__CI__VI              0xD986
#define mmSPI_PERFCOUNTER2_SELECT__CI__VI               0xD982
#define mmSPI_PERFCOUNTER2_SELECT__SI                   0x2445
#define mmSPI_PERFCOUNTER3_HI__CI__VI                   0xD186
#define mmSPI_PERFCOUNTER3_HI__SI                       0x244D
#define mmSPI_PERFCOUNTER3_LO__CI__VI                   0xD187
#define mmSPI_PERFCOUNTER3_LO__SI                       0x244E
#define mmSPI_PERFCOUNTER3_SELECT1__CI__VI              0xD987
#define mmSPI_PERFCOUNTER3_SELECT__CI__VI               0xD983
#define mmSPI_PERFCOUNTER3_SELECT__SI                   0x2446
#define mmSPI_PERFCOUNTER4_HI__CI__VI                   0xD188
#define mmSPI_PERFCOUNTER4_LO__CI__VI                   0xD189
#define mmSPI_PERFCOUNTER4_SELECT__CI__VI               0xD988
#define mmSPI_PERFCOUNTER5_HI__CI__VI                   0xD18A
#define mmSPI_PERFCOUNTER5_LO__CI__VI                   0xD18B
#define mmSPI_PERFCOUNTER5_SELECT__CI__VI               0xD989
#define mmSPI_PERFCOUNTER_BINS__CI__VI                  0xD98A
#define mmSPI_PERFCOUNTER_BINS__SI                      0x243F
#define mmSPI_PG_ENABLE_STATIC_CU_MASK                  0x24D7
#define mmSPI_PS_INPUT_ADDR                             0xA1B4
#define mmSPI_PS_INPUT_CNTL_0                           0xA191
#define mmSPI_PS_INPUT_CNTL_1                           0xA192
#define mmSPI_PS_INPUT_CNTL_10                          0xA19B
#define mmSPI_PS_INPUT_CNTL_11                          0xA19C
#define mmSPI_PS_INPUT_CNTL_12                          0xA19D
#define mmSPI_PS_INPUT_CNTL_13                          0xA19E
#define mmSPI_PS_INPUT_CNTL_14                          0xA19F
#define mmSPI_PS_INPUT_CNTL_15                          0xA1A0
#define mmSPI_PS_INPUT_CNTL_16                          0xA1A1
#define mmSPI_PS_INPUT_CNTL_17                          0xA1A2
#define mmSPI_PS_INPUT_CNTL_18                          0xA1A3
#define mmSPI_PS_INPUT_CNTL_19                          0xA1A4
#define mmSPI_PS_INPUT_CNTL_2                           0xA193
#define mmSPI_PS_INPUT_CNTL_20                          0xA1A5
#define mmSPI_PS_INPUT_CNTL_21                          0xA1A6
#define mmSPI_PS_INPUT_CNTL_22                          0xA1A7
#define mmSPI_PS_INPUT_CNTL_23                          0xA1A8
#define mmSPI_PS_INPUT_CNTL_24                          0xA1A9
#define mmSPI_PS_INPUT_CNTL_25                          0xA1AA
#define mmSPI_PS_INPUT_CNTL_26                          0xA1AB
#define mmSPI_PS_INPUT_CNTL_27                          0xA1AC
#define mmSPI_PS_INPUT_CNTL_28                          0xA1AD
#define mmSPI_PS_INPUT_CNTL_29                          0xA1AE
#define mmSPI_PS_INPUT_CNTL_3                           0xA194
#define mmSPI_PS_INPUT_CNTL_30                          0xA1AF
#define mmSPI_PS_INPUT_CNTL_31                          0xA1B0
#define mmSPI_PS_INPUT_CNTL_4                           0xA195
#define mmSPI_PS_INPUT_CNTL_5                           0xA196
#define mmSPI_PS_INPUT_CNTL_6                           0xA197
#define mmSPI_PS_INPUT_CNTL_7                           0xA198
#define mmSPI_PS_INPUT_CNTL_8                           0xA199
#define mmSPI_PS_INPUT_CNTL_9                           0xA19A
#define mmSPI_PS_INPUT_ENA                              0xA1B3
#define mmSPI_PS_IN_CONTROL                             0xA1B6
#define mmSPI_PS_MAX_WAVE_ID__CI__VI                    0x243A
#define mmSPI_PS_MAX_WAVE_ID__SI                        0x243B
#define mmSPI_RESET_DEBUG__CI__VI                       0x31DA
#define mmSPI_RESOURCE_RESERVE_CU_0__CI__VI             0x31DC
#define mmSPI_RESOURCE_RESERVE_CU_10__CI__VI            0x31F0
#define mmSPI_RESOURCE_RESERVE_CU_11__CI__VI            0x31F1
#define mmSPI_RESOURCE_RESERVE_CU_1__CI__VI             0x31DD
#define mmSPI_RESOURCE_RESERVE_CU_2__CI__VI             0x31DE
#define mmSPI_RESOURCE_RESERVE_CU_3__CI__VI             0x31DF
#define mmSPI_RESOURCE_RESERVE_CU_4__CI__VI             0x31E0
#define mmSPI_RESOURCE_RESERVE_CU_5__CI__VI             0x31E1
#define mmSPI_RESOURCE_RESERVE_CU_6__CI__VI             0x31E2
#define mmSPI_RESOURCE_RESERVE_CU_7__CI__VI             0x31E3
#define mmSPI_RESOURCE_RESERVE_CU_8__CI__VI             0x31E4
#define mmSPI_RESOURCE_RESERVE_CU_9__CI__VI             0x31E5
#define mmSPI_RESOURCE_RESERVE_EN_CU_0__CI__VI          0x31E6
#define mmSPI_RESOURCE_RESERVE_EN_CU_10__CI__VI         0x31F2
#define mmSPI_RESOURCE_RESERVE_EN_CU_11__CI__VI         0x31F3
#define mmSPI_RESOURCE_RESERVE_EN_CU_1__CI__VI          0x31E7
#define mmSPI_RESOURCE_RESERVE_EN_CU_2__CI__VI          0x31E8
#define mmSPI_RESOURCE_RESERVE_EN_CU_3__CI__VI          0x31E9
#define mmSPI_RESOURCE_RESERVE_EN_CU_4__CI__VI          0x31EA
#define mmSPI_RESOURCE_RESERVE_EN_CU_5__CI__VI          0x31EB
#define mmSPI_RESOURCE_RESERVE_EN_CU_6__CI__VI          0x31EC
#define mmSPI_RESOURCE_RESERVE_EN_CU_7__CI__VI          0x31ED
#define mmSPI_RESOURCE_RESERVE_EN_CU_8__CI__VI          0x31EE
#define mmSPI_RESOURCE_RESERVE_EN_CU_9__CI__VI          0x31EF
#define mmSPI_SHADER_COL_FORMAT                         0xA1C5
#define mmSPI_SHADER_LATE_ALLOC_VS__CI__VI              0x2C47
#define mmSPI_SHADER_PGM_HI_ES                          0x2CC9
#define mmSPI_SHADER_PGM_HI_GS                          0x2C89
#define mmSPI_SHADER_PGM_HI_HS                          0x2D09
#define mmSPI_SHADER_PGM_HI_LS                          0x2D49
#define mmSPI_SHADER_PGM_HI_PS                          0x2C09
#define mmSPI_SHADER_PGM_HI_VS                          0x2C49
#define mmSPI_SHADER_PGM_LO_ES                          0x2CC8
#define mmSPI_SHADER_PGM_LO_GS                          0x2C88
#define mmSPI_SHADER_PGM_LO_HS                          0x2D08
#define mmSPI_SHADER_PGM_LO_LS                          0x2D48
#define mmSPI_SHADER_PGM_LO_PS                          0x2C08
#define mmSPI_SHADER_PGM_LO_VS                          0x2C48
#define mmSPI_SHADER_PGM_RSRC1_ES                       0x2CCA
#define mmSPI_SHADER_PGM_RSRC1_GS                       0x2C8A
#define mmSPI_SHADER_PGM_RSRC1_HS                       0x2D0A
#define mmSPI_SHADER_PGM_RSRC1_LS                       0x2D4A
#define mmSPI_SHADER_PGM_RSRC1_PS                       0x2C0A
#define mmSPI_SHADER_PGM_RSRC1_VS                       0x2C4A
#define mmSPI_SHADER_PGM_RSRC2_ES                       0x2CCB
#define mmSPI_SHADER_PGM_RSRC2_ES_GS__CI__VI            0x2CBC
#define mmSPI_SHADER_PGM_RSRC2_ES_VS__CI__VI            0x2C7C
#define mmSPI_SHADER_PGM_RSRC2_GS                       0x2C8B
#define mmSPI_SHADER_PGM_RSRC2_HS                       0x2D0B
#define mmSPI_SHADER_PGM_RSRC2_LS                       0x2D4B
#define mmSPI_SHADER_PGM_RSRC2_LS_ES__CI__VI            0x2CFD
#define mmSPI_SHADER_PGM_RSRC2_LS_HS__CI__VI            0x2D3D
#define mmSPI_SHADER_PGM_RSRC2_LS_VS__CI__VI            0x2C7D
#define mmSPI_SHADER_PGM_RSRC2_PS                       0x2C0B
#define mmSPI_SHADER_PGM_RSRC2_VS                       0x2C4B
#define mmSPI_SHADER_PGM_RSRC3_ES__CI__VI               0x2CC7
#define mmSPI_SHADER_PGM_RSRC3_GS__CI__VI               0x2C87
#define mmSPI_SHADER_PGM_RSRC3_HS__CI__VI               0x2D07
#define mmSPI_SHADER_PGM_RSRC3_LS__CI__VI               0x2D47
#define mmSPI_SHADER_PGM_RSRC3_PS__CI__VI               0x2C07
#define mmSPI_SHADER_PGM_RSRC3_VS__CI__VI               0x2C46
#define mmSPI_SHADER_POS_FORMAT                         0xA1C3
#define mmSPI_SHADER_TBA_HI_ES                          0x2CC1
#define mmSPI_SHADER_TBA_HI_GS                          0x2C81
#define mmSPI_SHADER_TBA_HI_HS                          0x2D01
#define mmSPI_SHADER_TBA_HI_LS                          0x2D41
#define mmSPI_SHADER_TBA_HI_PS                          0x2C01
#define mmSPI_SHADER_TBA_HI_VS                          0x2C41
#define mmSPI_SHADER_TBA_LO_ES                          0x2CC0
#define mmSPI_SHADER_TBA_LO_GS                          0x2C80
#define mmSPI_SHADER_TBA_LO_HS                          0x2D00
#define mmSPI_SHADER_TBA_LO_LS                          0x2D40
#define mmSPI_SHADER_TBA_LO_PS                          0x2C00
#define mmSPI_SHADER_TBA_LO_VS                          0x2C40
#define mmSPI_SHADER_TMA_HI_ES                          0x2CC3
#define mmSPI_SHADER_TMA_HI_GS                          0x2C83
#define mmSPI_SHADER_TMA_HI_HS                          0x2D03
#define mmSPI_SHADER_TMA_HI_LS                          0x2D43
#define mmSPI_SHADER_TMA_HI_PS                          0x2C03
#define mmSPI_SHADER_TMA_HI_VS                          0x2C43
#define mmSPI_SHADER_TMA_LO_ES                          0x2CC2
#define mmSPI_SHADER_TMA_LO_GS                          0x2C82
#define mmSPI_SHADER_TMA_LO_HS                          0x2D02
#define mmSPI_SHADER_TMA_LO_LS                          0x2D42
#define mmSPI_SHADER_TMA_LO_PS                          0x2C02
#define mmSPI_SHADER_TMA_LO_VS                          0x2C42
#define mmSPI_SHADER_USER_DATA_ES_0                     0x2CCC
#define mmSPI_SHADER_USER_DATA_ES_1                     0x2CCD
#define mmSPI_SHADER_USER_DATA_ES_10                    0x2CD6
#define mmSPI_SHADER_USER_DATA_ES_11                    0x2CD7
#define mmSPI_SHADER_USER_DATA_ES_12                    0x2CD8
#define mmSPI_SHADER_USER_DATA_ES_13                    0x2CD9
#define mmSPI_SHADER_USER_DATA_ES_14                    0x2CDA
#define mmSPI_SHADER_USER_DATA_ES_15                    0x2CDB
#define mmSPI_SHADER_USER_DATA_ES_2                     0x2CCE
#define mmSPI_SHADER_USER_DATA_ES_3                     0x2CCF
#define mmSPI_SHADER_USER_DATA_ES_4                     0x2CD0
#define mmSPI_SHADER_USER_DATA_ES_5                     0x2CD1
#define mmSPI_SHADER_USER_DATA_ES_6                     0x2CD2
#define mmSPI_SHADER_USER_DATA_ES_7                     0x2CD3
#define mmSPI_SHADER_USER_DATA_ES_8                     0x2CD4
#define mmSPI_SHADER_USER_DATA_ES_9                     0x2CD5
#define mmSPI_SHADER_USER_DATA_GS_0                     0x2C8C
#define mmSPI_SHADER_USER_DATA_GS_1                     0x2C8D
#define mmSPI_SHADER_USER_DATA_GS_10                    0x2C96
#define mmSPI_SHADER_USER_DATA_GS_11                    0x2C97
#define mmSPI_SHADER_USER_DATA_GS_12                    0x2C98
#define mmSPI_SHADER_USER_DATA_GS_13                    0x2C99
#define mmSPI_SHADER_USER_DATA_GS_14                    0x2C9A
#define mmSPI_SHADER_USER_DATA_GS_15                    0x2C9B
#define mmSPI_SHADER_USER_DATA_GS_2                     0x2C8E
#define mmSPI_SHADER_USER_DATA_GS_3                     0x2C8F
#define mmSPI_SHADER_USER_DATA_GS_4                     0x2C90
#define mmSPI_SHADER_USER_DATA_GS_5                     0x2C91
#define mmSPI_SHADER_USER_DATA_GS_6                     0x2C92
#define mmSPI_SHADER_USER_DATA_GS_7                     0x2C93
#define mmSPI_SHADER_USER_DATA_GS_8                     0x2C94
#define mmSPI_SHADER_USER_DATA_GS_9                     0x2C95
#define mmSPI_SHADER_USER_DATA_HS_0                     0x2D0C
#define mmSPI_SHADER_USER_DATA_HS_1                     0x2D0D
#define mmSPI_SHADER_USER_DATA_HS_10                    0x2D16
#define mmSPI_SHADER_USER_DATA_HS_11                    0x2D17
#define mmSPI_SHADER_USER_DATA_HS_12                    0x2D18
#define mmSPI_SHADER_USER_DATA_HS_13                    0x2D19
#define mmSPI_SHADER_USER_DATA_HS_14                    0x2D1A
#define mmSPI_SHADER_USER_DATA_HS_15                    0x2D1B
#define mmSPI_SHADER_USER_DATA_HS_2                     0x2D0E
#define mmSPI_SHADER_USER_DATA_HS_3                     0x2D0F
#define mmSPI_SHADER_USER_DATA_HS_4                     0x2D10
#define mmSPI_SHADER_USER_DATA_HS_5                     0x2D11
#define mmSPI_SHADER_USER_DATA_HS_6                     0x2D12
#define mmSPI_SHADER_USER_DATA_HS_7                     0x2D13
#define mmSPI_SHADER_USER_DATA_HS_8                     0x2D14
#define mmSPI_SHADER_USER_DATA_HS_9                     0x2D15
#define mmSPI_SHADER_USER_DATA_LS_0                     0x2D4C
#define mmSPI_SHADER_USER_DATA_LS_1                     0x2D4D
#define mmSPI_SHADER_USER_DATA_LS_10                    0x2D56
#define mmSPI_SHADER_USER_DATA_LS_11                    0x2D57
#define mmSPI_SHADER_USER_DATA_LS_12                    0x2D58
#define mmSPI_SHADER_USER_DATA_LS_13                    0x2D59
#define mmSPI_SHADER_USER_DATA_LS_14                    0x2D5A
#define mmSPI_SHADER_USER_DATA_LS_15                    0x2D5B
#define mmSPI_SHADER_USER_DATA_LS_2                     0x2D4E
#define mmSPI_SHADER_USER_DATA_LS_3                     0x2D4F
#define mmSPI_SHADER_USER_DATA_LS_4                     0x2D50
#define mmSPI_SHADER_USER_DATA_LS_5                     0x2D51
#define mmSPI_SHADER_USER_DATA_LS_6                     0x2D52
#define mmSPI_SHADER_USER_DATA_LS_7                     0x2D53
#define mmSPI_SHADER_USER_DATA_LS_8                     0x2D54
#define mmSPI_SHADER_USER_DATA_LS_9                     0x2D55
#define mmSPI_SHADER_USER_DATA_PS_0                     0x2C0C
#define mmSPI_SHADER_USER_DATA_PS_1                     0x2C0D
#define mmSPI_SHADER_USER_DATA_PS_10                    0x2C16
#define mmSPI_SHADER_USER_DATA_PS_11                    0x2C17
#define mmSPI_SHADER_USER_DATA_PS_12                    0x2C18
#define mmSPI_SHADER_USER_DATA_PS_13                    0x2C19
#define mmSPI_SHADER_USER_DATA_PS_14                    0x2C1A
#define mmSPI_SHADER_USER_DATA_PS_15                    0x2C1B
#define mmSPI_SHADER_USER_DATA_PS_2                     0x2C0E
#define mmSPI_SHADER_USER_DATA_PS_3                     0x2C0F
#define mmSPI_SHADER_USER_DATA_PS_4                     0x2C10
#define mmSPI_SHADER_USER_DATA_PS_5                     0x2C11
#define mmSPI_SHADER_USER_DATA_PS_6                     0x2C12
#define mmSPI_SHADER_USER_DATA_PS_7                     0x2C13
#define mmSPI_SHADER_USER_DATA_PS_8                     0x2C14
#define mmSPI_SHADER_USER_DATA_PS_9                     0x2C15
#define mmSPI_SHADER_USER_DATA_VS_0                     0x2C4C
#define mmSPI_SHADER_USER_DATA_VS_1                     0x2C4D
#define mmSPI_SHADER_USER_DATA_VS_10                    0x2C56
#define mmSPI_SHADER_USER_DATA_VS_11                    0x2C57
#define mmSPI_SHADER_USER_DATA_VS_12                    0x2C58
#define mmSPI_SHADER_USER_DATA_VS_13                    0x2C59
#define mmSPI_SHADER_USER_DATA_VS_14                    0x2C5A
#define mmSPI_SHADER_USER_DATA_VS_15                    0x2C5B
#define mmSPI_SHADER_USER_DATA_VS_2                     0x2C4E
#define mmSPI_SHADER_USER_DATA_VS_3                     0x2C4F
#define mmSPI_SHADER_USER_DATA_VS_4                     0x2C50
#define mmSPI_SHADER_USER_DATA_VS_5                     0x2C51
#define mmSPI_SHADER_USER_DATA_VS_6                     0x2C52
#define mmSPI_SHADER_USER_DATA_VS_7                     0x2C53
#define mmSPI_SHADER_USER_DATA_VS_8                     0x2C54
#define mmSPI_SHADER_USER_DATA_VS_9                     0x2C55
#define mmSPI_SHADER_Z_FORMAT                           0xA1C4
#define mmSPI_SLAVE_DEBUG_BUSY                          0x24D3
#define mmSPI_STATIC_THREAD_MGMT_3__SI                  0x243A
#define mmSPI_SX_EXPORT_BUFFER_SIZES                    0x24D9
#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                0x24DA
#define mmSPI_TMPRING_SIZE                              0xA1BA
#define mmSPI_VS_OUT_CONFIG                             0xA1B1
#define mmSPI_WCL_PIPE_PERCENT_CS0__CI__VI              0x31C9
#define mmSPI_WCL_PIPE_PERCENT_CS1__CI__VI              0x31CA
#define mmSPI_WCL_PIPE_PERCENT_CS2__CI__VI              0x31CB
#define mmSPI_WCL_PIPE_PERCENT_CS3__CI__VI              0x31CC
#define mmSPI_WCL_PIPE_PERCENT_CS4__CI__VI              0x31CD
#define mmSPI_WCL_PIPE_PERCENT_CS5__CI__VI              0x31CE
#define mmSPI_WCL_PIPE_PERCENT_CS6__CI__VI              0x31CF
#define mmSPI_WCL_PIPE_PERCENT_CS7__CI__VI              0x31D0
#define mmSPI_WCL_PIPE_PERCENT_GFX__CI__VI              0x31C7
#define mmSPI_WCL_PIPE_PERCENT_HP3D__CI__VI             0x31C8
#define mmSPI_WF_LIFETIME_CNTL__CI__VI                  0x24AA
#define mmSPI_WF_LIFETIME_DEBUG__CI__VI                 0x24CA
#define mmSPI_WF_LIFETIME_LIMIT_0__CI__VI               0x24AB
#define mmSPI_WF_LIFETIME_LIMIT_1__CI__VI               0x24AC
#define mmSPI_WF_LIFETIME_LIMIT_2__CI__VI               0x24AD
#define mmSPI_WF_LIFETIME_LIMIT_3__CI__VI               0x24AE
#define mmSPI_WF_LIFETIME_LIMIT_4__CI__VI               0x24AF
#define mmSPI_WF_LIFETIME_LIMIT_5__CI__VI               0x24B0
#define mmSPI_WF_LIFETIME_LIMIT_6__CI__VI               0x24B1
#define mmSPI_WF_LIFETIME_LIMIT_7__CI__VI               0x24B2
#define mmSPI_WF_LIFETIME_LIMIT_8__CI__VI               0x24B3
#define mmSPI_WF_LIFETIME_LIMIT_9__CI__VI               0x24B4
#define mmSPI_WF_LIFETIME_STATUS_0__CI__VI              0x24B5
#define mmSPI_WF_LIFETIME_STATUS_10__CI__VI             0x24BF
#define mmSPI_WF_LIFETIME_STATUS_11__CI__VI             0x24C0
#define mmSPI_WF_LIFETIME_STATUS_12__CI__VI             0x24C1
#define mmSPI_WF_LIFETIME_STATUS_13__CI__VI             0x24C2
#define mmSPI_WF_LIFETIME_STATUS_14__CI__VI             0x24C3
#define mmSPI_WF_LIFETIME_STATUS_15__CI__VI             0x24C4
#define mmSPI_WF_LIFETIME_STATUS_16__CI__VI             0x24C5
#define mmSPI_WF_LIFETIME_STATUS_17__CI__VI             0x24C6
#define mmSPI_WF_LIFETIME_STATUS_18__CI__VI             0x24C7
#define mmSPI_WF_LIFETIME_STATUS_19__CI__VI             0x24C8
#define mmSPI_WF_LIFETIME_STATUS_1__CI__VI              0x24B6
#define mmSPI_WF_LIFETIME_STATUS_20__CI__VI             0x24C9
#define mmSPI_WF_LIFETIME_STATUS_2__CI__VI              0x24B7
#define mmSPI_WF_LIFETIME_STATUS_3__CI__VI              0x24B8
#define mmSPI_WF_LIFETIME_STATUS_4__CI__VI              0x24B9
#define mmSPI_WF_LIFETIME_STATUS_5__CI__VI              0x24BA
#define mmSPI_WF_LIFETIME_STATUS_6__CI__VI              0x24BB
#define mmSPI_WF_LIFETIME_STATUS_7__CI__VI              0x24BC
#define mmSPI_WF_LIFETIME_STATUS_8__CI__VI              0x24BD
#define mmSPI_WF_LIFETIME_STATUS_9__CI__VI              0x24BE
#define mmSPLL_CNTL_MODE__SI                            0x0186
#define mmSQC_CACHES__CI__VI                            0xC348
#define mmSQC_CACHES__SI                                0x2302
#define mmSQC_CONFIG                                    0x2301
#define mmSQC_POLICY__CI                                0x230E
#define mmSQC_SECDED_CNT__SI__CI                        0x23A0
#define mmSQC_VOLATILE__CI                              0x230F
#define mmSQ_ALU_CLK_CTRL__CI__VI                       0xF08E
#define mmSQ_ALU_CLK_CTRL__SI                           0x2360
#define mmSQ_BUF_RSRC_WORD0                             0x23C0
#define mmSQ_BUF_RSRC_WORD1                             0x23C1
#define mmSQ_BUF_RSRC_WORD2                             0x23C2
#define mmSQ_BUF_RSRC_WORD3                             0x23C3
#define mmSQ_CMD_TIMESTAMP__CI__VI                      0x2375
#define mmSQ_CMD__CI__VI                                0x237B
#define mmSQ_CONFIG                                     0x2300
#define mmSQ_DEBUG_STS_GLOBAL                           0x2309
#define mmSQ_DEBUG_STS_GLOBAL2__CI__VI                  0x2310
#define mmSQ_DEBUG_STS_GLOBAL3__CI__VI                  0x2311
#define mmSQ_DED_CNT__SI__CI                            0x23A2
#define mmSQ_DED_INFO__SI__CI                           0x23A3
#define mmSQ_DS_0                                       0x237F
#define mmSQ_DS_1                                       0x237F
#define mmSQ_EXP_0                                      0x237F
#define mmSQ_EXP_1                                      0x237F
#define mmSQ_FIFO_SIZES                                 0x2305
#define mmSQ_FLAT_0__CI__VI                             0x237F
#define mmSQ_FLAT_1__CI__VI                             0x237F
#define mmSQ_FLAT_SCRATCH_WORD0__CI__VI                 0x23D0
#define mmSQ_FLAT_SCRATCH_WORD1__CI__VI                 0x23D1
#define mmSQ_HV_VMID_CTRL__CI__VI                       0xF840
#define mmSQ_IMG_RSRC_WORD0                             0x23C4
#define mmSQ_IMG_RSRC_WORD1                             0x23C5
#define mmSQ_IMG_RSRC_WORD2                             0x23C6
#define mmSQ_IMG_RSRC_WORD3                             0x23C7
#define mmSQ_IMG_RSRC_WORD4                             0x23C8
#define mmSQ_IMG_RSRC_WORD5                             0x23C9
#define mmSQ_IMG_RSRC_WORD6                             0x23CA
#define mmSQ_IMG_RSRC_WORD7                             0x23CB
#define mmSQ_IMG_SAMP_WORD0                             0x23CC
#define mmSQ_IMG_SAMP_WORD1                             0x23CD
#define mmSQ_IMG_SAMP_WORD2                             0x23CE
#define mmSQ_IMG_SAMP_WORD3                             0x23CF
#define mmSQ_IND_DATA                                   0x2379
#define mmSQ_IND_INDEX                                  0x2378
#define mmSQ_INST                                       0x237F
#define mmSQ_INTERRUPT_AUTO_MASK__CI__VI                0x2314
#define mmSQ_INTERRUPT_MSG_CTRL__CI__VI                 0x2315
#define mmSQ_LB_CTR_CTRL                                0x2398
#define mmSQ_LB_DATA_ALU_CYCLES                         0x2399
#define mmSQ_LB_DATA_ALU_STALLS                         0x239B
#define mmSQ_LB_DATA_TEX_CYCLES                         0x239A
#define mmSQ_LB_DATA_TEX_STALLS                         0x239C
#define mmSQ_LDS_CLK_CTRL__CI__VI                       0xF090
#define mmSQ_MIMG_0                                     0x237F
#define mmSQ_MIMG_1                                     0x237F
#define mmSQ_MTBUF_0                                    0x237F
#define mmSQ_MTBUF_1                                    0x237F
#define mmSQ_MUBUF_0                                    0x237F
#define mmSQ_MUBUF_1                                    0x237F
#define mmSQ_PERFCOUNTER0_HI__CI__VI                    0xD1C1
#define mmSQ_PERFCOUNTER0_HI__SI                        0x2321
#define mmSQ_PERFCOUNTER0_LO__CI__VI                    0xD1C0
#define mmSQ_PERFCOUNTER0_LO__SI                        0x2320
#define mmSQ_PERFCOUNTER0_SELECT__CI__VI                0xD9C0
#define mmSQ_PERFCOUNTER0_SELECT__SI                    0x2340
#define mmSQ_PERFCOUNTER10_HI__CI__VI                   0xD1D5
#define mmSQ_PERFCOUNTER10_HI__SI                       0x2335
#define mmSQ_PERFCOUNTER10_LO__CI__VI                   0xD1D4
#define mmSQ_PERFCOUNTER10_LO__SI                       0x2334
#define mmSQ_PERFCOUNTER10_SELECT__CI__VI               0xD9CA
#define mmSQ_PERFCOUNTER10_SELECT__SI                   0x234A
#define mmSQ_PERFCOUNTER11_HI__CI__VI                   0xD1D7
#define mmSQ_PERFCOUNTER11_HI__SI                       0x2337
#define mmSQ_PERFCOUNTER11_LO__CI__VI                   0xD1D6
#define mmSQ_PERFCOUNTER11_LO__SI                       0x2336
#define mmSQ_PERFCOUNTER11_SELECT__CI__VI               0xD9CB
#define mmSQ_PERFCOUNTER11_SELECT__SI                   0x234B
#define mmSQ_PERFCOUNTER12_HI__CI__VI                   0xD1D9
#define mmSQ_PERFCOUNTER12_HI__SI                       0x2339
#define mmSQ_PERFCOUNTER12_LO__CI__VI                   0xD1D8
#define mmSQ_PERFCOUNTER12_LO__SI                       0x2338
#define mmSQ_PERFCOUNTER12_SELECT__CI__VI               0xD9CC
#define mmSQ_PERFCOUNTER12_SELECT__SI                   0x234C
#define mmSQ_PERFCOUNTER13_HI__CI__VI                   0xD1DB
#define mmSQ_PERFCOUNTER13_HI__SI                       0x233B
#define mmSQ_PERFCOUNTER13_LO__CI__VI                   0xD1DA
#define mmSQ_PERFCOUNTER13_LO__SI                       0x233A
#define mmSQ_PERFCOUNTER13_SELECT__CI__VI               0xD9CD
#define mmSQ_PERFCOUNTER13_SELECT__SI                   0x234D
#define mmSQ_PERFCOUNTER14_HI__CI__VI                   0xD1DD
#define mmSQ_PERFCOUNTER14_HI__SI                       0x233D
#define mmSQ_PERFCOUNTER14_LO__CI__VI                   0xD1DC
#define mmSQ_PERFCOUNTER14_LO__SI                       0x233C
#define mmSQ_PERFCOUNTER14_SELECT__CI__VI               0xD9CE
#define mmSQ_PERFCOUNTER14_SELECT__SI                   0x234E
#define mmSQ_PERFCOUNTER15_HI__CI__VI                   0xD1DF
#define mmSQ_PERFCOUNTER15_HI__SI                       0x233F
#define mmSQ_PERFCOUNTER15_LO__CI__VI                   0xD1DE
#define mmSQ_PERFCOUNTER15_LO__SI                       0x233E
#define mmSQ_PERFCOUNTER15_SELECT__CI__VI               0xD9CF
#define mmSQ_PERFCOUNTER15_SELECT__SI                   0x234F
#define mmSQ_PERFCOUNTER1_HI__CI__VI                    0xD1C3
#define mmSQ_PERFCOUNTER1_HI__SI                        0x2323
#define mmSQ_PERFCOUNTER1_LO__CI__VI                    0xD1C2
#define mmSQ_PERFCOUNTER1_LO__SI                        0x2322
#define mmSQ_PERFCOUNTER1_SELECT__CI__VI                0xD9C1
#define mmSQ_PERFCOUNTER1_SELECT__SI                    0x2341
#define mmSQ_PERFCOUNTER2_HI__CI__VI                    0xD1C5
#define mmSQ_PERFCOUNTER2_HI__SI                        0x2325
#define mmSQ_PERFCOUNTER2_LO__CI__VI                    0xD1C4
#define mmSQ_PERFCOUNTER2_LO__SI                        0x2324
#define mmSQ_PERFCOUNTER2_SELECT__CI__VI                0xD9C2
#define mmSQ_PERFCOUNTER2_SELECT__SI                    0x2342
#define mmSQ_PERFCOUNTER3_HI__CI__VI                    0xD1C7
#define mmSQ_PERFCOUNTER3_HI__SI                        0x2327
#define mmSQ_PERFCOUNTER3_LO__CI__VI                    0xD1C6
#define mmSQ_PERFCOUNTER3_LO__SI                        0x2326
#define mmSQ_PERFCOUNTER3_SELECT__CI__VI                0xD9C3
#define mmSQ_PERFCOUNTER3_SELECT__SI                    0x2343
#define mmSQ_PERFCOUNTER4_HI__CI__VI                    0xD1C9
#define mmSQ_PERFCOUNTER4_HI__SI                        0x2329
#define mmSQ_PERFCOUNTER4_LO__CI__VI                    0xD1C8
#define mmSQ_PERFCOUNTER4_LO__SI                        0x2328
#define mmSQ_PERFCOUNTER4_SELECT__CI__VI                0xD9C4
#define mmSQ_PERFCOUNTER4_SELECT__SI                    0x2344
#define mmSQ_PERFCOUNTER5_HI__CI__VI                    0xD1CB
#define mmSQ_PERFCOUNTER5_HI__SI                        0x232B
#define mmSQ_PERFCOUNTER5_LO__CI__VI                    0xD1CA
#define mmSQ_PERFCOUNTER5_LO__SI                        0x232A
#define mmSQ_PERFCOUNTER5_SELECT__CI__VI                0xD9C5
#define mmSQ_PERFCOUNTER5_SELECT__SI                    0x2345
#define mmSQ_PERFCOUNTER6_HI__CI__VI                    0xD1CD
#define mmSQ_PERFCOUNTER6_HI__SI                        0x232D
#define mmSQ_PERFCOUNTER6_LO__CI__VI                    0xD1CC
#define mmSQ_PERFCOUNTER6_LO__SI                        0x232C
#define mmSQ_PERFCOUNTER6_SELECT__CI__VI                0xD9C6
#define mmSQ_PERFCOUNTER6_SELECT__SI                    0x2346
#define mmSQ_PERFCOUNTER7_HI__CI__VI                    0xD1CF
#define mmSQ_PERFCOUNTER7_HI__SI                        0x232F
#define mmSQ_PERFCOUNTER7_LO__CI__VI                    0xD1CE
#define mmSQ_PERFCOUNTER7_LO__SI                        0x232E
#define mmSQ_PERFCOUNTER7_SELECT__CI__VI                0xD9C7
#define mmSQ_PERFCOUNTER7_SELECT__SI                    0x2347
#define mmSQ_PERFCOUNTER8_HI__CI__VI                    0xD1D1
#define mmSQ_PERFCOUNTER8_HI__SI                        0x2331
#define mmSQ_PERFCOUNTER8_LO__CI__VI                    0xD1D0
#define mmSQ_PERFCOUNTER8_LO__SI                        0x2330
#define mmSQ_PERFCOUNTER8_SELECT__CI__VI                0xD9C8
#define mmSQ_PERFCOUNTER8_SELECT__SI                    0x2348
#define mmSQ_PERFCOUNTER9_HI__CI__VI                    0xD1D3
#define mmSQ_PERFCOUNTER9_HI__SI                        0x2333
#define mmSQ_PERFCOUNTER9_LO__CI__VI                    0xD1D2
#define mmSQ_PERFCOUNTER9_LO__SI                        0x2332
#define mmSQ_PERFCOUNTER9_SELECT__CI__VI                0xD9C9
#define mmSQ_PERFCOUNTER9_SELECT__SI                    0x2349
#define mmSQ_PERFCOUNTER_CTRL2__CI__VI                  0xD9E2
#define mmSQ_PERFCOUNTER_CTRL__CI__VI                   0xD9E0
#define mmSQ_PERFCOUNTER_CTRL__SI                       0x2306
#define mmSQ_PERFCOUNTER_MASK__CI__VI                   0xD9E1
#define mmSQ_POWER_THROTTLE2__CI__VI                    0xF092
#define mmSQ_POWER_THROTTLE2__SI                        0x2397
#define mmSQ_POWER_THROTTLE__CI__VI                     0xF091
#define mmSQ_POWER_THROTTLE__SI                         0x2396
#define mmSQ_RANDOM_WAVE_PRI                            0x2303
#define mmSQ_REG_CREDITS                                0x2304
#define mmSQ_REG_TIMESTAMP__CI__VI                      0x2374
#define mmSQ_SEC_CNT__SI__CI                            0x23A1
#define mmSQ_SMRD__SI__CI                               0x237F
#define mmSQ_SOP1                                       0x237F
#define mmSQ_SOP2                                       0x237F
#define mmSQ_SOPC                                       0x237F
#define mmSQ_SOPK                                       0x237F
#define mmSQ_SOPP                                       0x237F
#define mmSQ_TEX_CLK_CTRL__CI__VI                       0xF08F
#define mmSQ_TEX_CLK_CTRL__SI                           0x2361
#define mmSQ_THREAD_TRACE_BASE2__CI                     0x2385
#define mmSQ_THREAD_TRACE_CNTR                          0x2390
#define mmSQ_THREAD_TRACE_TOKEN_MASK2__CI               0x2386
#define mmSQ_THREAD_TRACE_USERDATA_0__CI__VI            0xC340
#define mmSQ_THREAD_TRACE_USERDATA_0__SI                0x2388
#define mmSQ_THREAD_TRACE_USERDATA_1__CI__VI            0xC341
#define mmSQ_THREAD_TRACE_USERDATA_1__SI                0x2389
#define mmSQ_THREAD_TRACE_USERDATA_2__CI__VI            0xC342
#define mmSQ_THREAD_TRACE_USERDATA_2__SI                0x238A
#define mmSQ_THREAD_TRACE_USERDATA_3__CI__VI            0xC343
#define mmSQ_THREAD_TRACE_USERDATA_3__SI                0x238B
#define mmSQ_THREAD_TRACE_WORD_CMN                      0x23B0
#define mmSQ_THREAD_TRACE_WORD_EVENT                    0x23B0
#define mmSQ_THREAD_TRACE_WORD_INST                     0x23B0
#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2           0x23B0
#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2           0x23B1
#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2     0x23B0
#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2     0x23B1
#define mmSQ_THREAD_TRACE_WORD_ISSUE                    0x23B0
#define mmSQ_THREAD_TRACE_WORD_MISC                     0x23B0
#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2              0x23B0
#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2              0x23B1
#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2               0x23B0
#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2               0x23B0
#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI    0x23B0
#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI    0x23B0
#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2         0x23B0
#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2         0x23B1
#define mmSQ_THREAD_TRACE_WORD_TIME__SI                 0x23B0
#define mmSQ_THREAD_TRACE_WORD_WAVE                     0x23B0
#define mmSQ_THREAD_TRACE_WORD_WAVE_START               0x23B0
#define mmSQ_TIME_HI                                    0x237C
#define mmSQ_TIME_LO                                    0x237D
#define mmSQ_VINTRP                                     0x237F
#define mmSQ_VOP1                                       0x237F
#define mmSQ_VOP2                                       0x237F
#define mmSQ_VOP3_0                                     0x237F
#define mmSQ_VOP3_0_SDST_ENC                            0x237F
#define mmSQ_VOP3_1                                     0x237F
#define mmSQ_VOPC                                       0x237F
#define mmSRBM_CHIP_REVISION                            0x039B
#define mmSRBM_CNTL                                     0x0390
#define mmSRBM_DEBUG                                    0x03A4
#define mmSRBM_DEBUG_CNTL                               0x0399
#define mmSRBM_DEBUG_DATA                               0x039A
#define mmSRBM_DEBUG_SNAPSHOT                           0x03A5
#define mmSRBM_GFX_CNTL                                 0x0391
#define mmSRBM_INT_ACK                                  0x03AA
#define mmSRBM_INT_CNTL                                 0x03A8
#define mmSRBM_INT_STATUS                               0x03A9
#define mmSRBM_MC_CLKEN_CNTL__CI__VI                    0x03B3
#define mmSRBM_READ_ERROR                               0x03A6
#define mmSRBM_SAM_CLKEN_CNTL__CI__VI                   0x03B8
#define mmSRBM_SDMA_CLKEN_CNTL__CI__VI                  0x03B7
#define mmSRBM_SOFT_RESET                               0x0398
#define mmSRBM_STATUS                                   0x0394
#define mmSRBM_STATUS2                                  0x0393
#define mmSRBM_SYS_CLKEN_CNTL                           0x03B4
#define mmSRBM_UVD_CLKEN_CNTL                           0x03B6
#define mmSRBM_VCE_CLKEN_CNTL                           0x03B5
#define mmSX_DEBUG_1                                    0x2418
#define mmSX_DEBUG_BUSY                                 0x2414
#define mmSX_DEBUG_BUSY_2                               0x2415
#define mmSX_DEBUG_BUSY_3                               0x2416
#define mmSX_DEBUG_BUSY_4                               0x2417
#define mmSX_PERFCOUNTER0_HI__CI__VI                    0xD241
#define mmSX_PERFCOUNTER0_HI__SI                        0x2421
#define mmSX_PERFCOUNTER0_LO__CI__VI                    0xD240
#define mmSX_PERFCOUNTER0_LO__SI                        0x2420
#define mmSX_PERFCOUNTER0_SELECT1__CI__VI               0xDA44
#define mmSX_PERFCOUNTER0_SELECT__CI__VI                0xDA40
#define mmSX_PERFCOUNTER0_SELECT__SI                    0x241C
#define mmSX_PERFCOUNTER1_HI__CI__VI                    0xD243
#define mmSX_PERFCOUNTER1_HI__SI                        0x2423
#define mmSX_PERFCOUNTER1_LO__CI__VI                    0xD242
#define mmSX_PERFCOUNTER1_LO__SI                        0x2422
#define mmSX_PERFCOUNTER1_SELECT1__CI__VI               0xDA45
#define mmSX_PERFCOUNTER1_SELECT__CI__VI                0xDA41
#define mmSX_PERFCOUNTER1_SELECT__SI                    0x241D
#define mmSX_PERFCOUNTER2_HI__CI__VI                    0xD245
#define mmSX_PERFCOUNTER2_HI__SI                        0x2425
#define mmSX_PERFCOUNTER2_LO__CI__VI                    0xD244
#define mmSX_PERFCOUNTER2_LO__SI                        0x2424
#define mmSX_PERFCOUNTER2_SELECT__CI__VI                0xDA42
#define mmSX_PERFCOUNTER2_SELECT__SI                    0x241E
#define mmSX_PERFCOUNTER3_HI__CI__VI                    0xD247
#define mmSX_PERFCOUNTER3_HI__SI                        0x2427
#define mmSX_PERFCOUNTER3_LO__CI__VI                    0xD246
#define mmSX_PERFCOUNTER3_LO__SI                        0x2426
#define mmSX_PERFCOUNTER3_SELECT__CI__VI                0xDA43
#define mmSX_PERFCOUNTER3_SELECT__SI                    0x241F
#define mmTARGET_AND_CURRENT_PROFILE_INDEX_1__SI        0x021D
#define mmTARGET_AND_CURRENT_PROFILE_INDEX__SI          0x01E6
#define mmTA_BC_BASE_ADDR                               0xA020
#define mmTA_BC_BASE_ADDR_HI__CI__VI                    0xA021
#define mmTA_CGTT_CTRL__CI__VI                          0xF09D
#define mmTA_CGTT_CTRL__SI                              0x2544
#define mmTA_CNTL                                       0x2541
#define mmTA_CNTL_AUX                                   0x2542
#define mmTA_CS_BC_BASE_ADDR_HI__CI__VI                 0xC381
#define mmTA_CS_BC_BASE_ADDR__CI__VI                    0xC380
#define mmTA_CS_BC_BASE_ADDR__SI                        0x2543
#define mmTA_DEBUG_DATA                                 0x254D
#define mmTA_DEBUG_INDEX                                0x254C
#define mmTA_PERFCOUNTER0_HI__CI__VI                    0xD2C1
#define mmTA_PERFCOUNTER0_HI__SI                        0x2556
#define mmTA_PERFCOUNTER0_LO__CI__VI                    0xD2C0
#define mmTA_PERFCOUNTER0_LO__SI                        0x2555
#define mmTA_PERFCOUNTER0_SELECT1__CI__VI               0xDAC1
#define mmTA_PERFCOUNTER0_SELECT__CI__VI                0xDAC0
#define mmTA_PERFCOUNTER0_SELECT__SI                    0x2554
#define mmTA_PERFCOUNTER1_HI__CI__VI                    0xD2C3
#define mmTA_PERFCOUNTER1_HI__SI                        0x2562
#define mmTA_PERFCOUNTER1_LO__CI__VI                    0xD2C2
#define mmTA_PERFCOUNTER1_LO__SI                        0x2561
#define mmTA_PERFCOUNTER1_SELECT__CI__VI                0xDAC2
#define mmTA_PERFCOUNTER1_SELECT__SI                    0x2560
#define mmTA_RESERVED_010C__CI__VI                      0x2543
#define mmTA_SCRATCH                                    0x2564
#define mmTA_STATUS                                     0x2548
#define mmTCA_CGTT_SCLK_CTRL__CI__VI                    0xF0AD
#define mmTCA_CGTT_SCLK_CTRL__SI                        0x2BC1
#define mmTCA_CTRL                                      0x2BC0
#define mmTCA_PERFCOUNTER0_HI__CI__VI                   0xD391
#define mmTCA_PERFCOUNTER0_HI__SI                       0x2BD2
#define mmTCA_PERFCOUNTER0_LO__CI__VI                   0xD390
#define mmTCA_PERFCOUNTER0_LO__SI                       0x2BD1
#define mmTCA_PERFCOUNTER0_SELECT1__CI__VI              0xDB91
#define mmTCA_PERFCOUNTER0_SELECT__CI__VI               0xDB90
#define mmTCA_PERFCOUNTER0_SELECT__SI                   0x2BD0
#define mmTCA_PERFCOUNTER1_HI__CI__VI                   0xD393
#define mmTCA_PERFCOUNTER1_HI__SI                       0x2BD5
#define mmTCA_PERFCOUNTER1_LO__CI__VI                   0xD392
#define mmTCA_PERFCOUNTER1_LO__SI                       0x2BD4
#define mmTCA_PERFCOUNTER1_SELECT1__CI__VI              0xDB93
#define mmTCA_PERFCOUNTER1_SELECT__CI__VI               0xDB92
#define mmTCA_PERFCOUNTER1_SELECT__SI                   0x2BD3
#define mmTCA_PERFCOUNTER2_HI__CI__VI                   0xD395
#define mmTCA_PERFCOUNTER2_HI__SI                       0x2BD8
#define mmTCA_PERFCOUNTER2_LO__CI__VI                   0xD394
#define mmTCA_PERFCOUNTER2_LO__SI                       0x2BD7
#define mmTCA_PERFCOUNTER2_SELECT__CI__VI               0xDB94
#define mmTCA_PERFCOUNTER2_SELECT__SI                   0x2BD6
#define mmTCA_PERFCOUNTER3_HI__CI__VI                   0xD397
#define mmTCA_PERFCOUNTER3_HI__SI                       0x2BDB
#define mmTCA_PERFCOUNTER3_LO__CI__VI                   0xD396
#define mmTCA_PERFCOUNTER3_LO__SI                       0x2BDA
#define mmTCA_PERFCOUNTER3_SELECT__CI__VI               0xDB95
#define mmTCA_PERFCOUNTER3_SELECT__SI                   0x2BD9
#define mmTCC_CGTT_SCLK_CTRL__CI__VI                    0xF0AC
#define mmTCC_CGTT_SCLK_CTRL__SI                        0x2B81
#define mmTCC_CTRL                                      0x2B80
#define mmTCC_EDC_COUNTER__SI__CI                       0x2B82
#define mmTCC_PERFCOUNTER0_HI__CI__VI                   0xD381
#define mmTCC_PERFCOUNTER0_HI__SI                       0x2B92
#define mmTCC_PERFCOUNTER0_LO__CI__VI                   0xD380
#define mmTCC_PERFCOUNTER0_LO__SI                       0x2B91
#define mmTCC_PERFCOUNTER0_SELECT1__CI__VI              0xDB81
#define mmTCC_PERFCOUNTER0_SELECT__CI__VI               0xDB80
#define mmTCC_PERFCOUNTER0_SELECT__SI                   0x2B90
#define mmTCC_PERFCOUNTER1_HI__CI__VI                   0xD383
#define mmTCC_PERFCOUNTER1_HI__SI                       0x2B95
#define mmTCC_PERFCOUNTER1_LO__CI__VI                   0xD382
#define mmTCC_PERFCOUNTER1_LO__SI                       0x2B94
#define mmTCC_PERFCOUNTER1_SELECT1__CI__VI              0xDB83
#define mmTCC_PERFCOUNTER1_SELECT__CI__VI               0xDB82
#define mmTCC_PERFCOUNTER1_SELECT__SI                   0x2B93
#define mmTCC_PERFCOUNTER2_HI__CI__VI                   0xD385
#define mmTCC_PERFCOUNTER2_HI__SI                       0x2B98
#define mmTCC_PERFCOUNTER2_LO__CI__VI                   0xD384
#define mmTCC_PERFCOUNTER2_LO__SI                       0x2B97
#define mmTCC_PERFCOUNTER2_SELECT__CI__VI               0xDB84
#define mmTCC_PERFCOUNTER2_SELECT__SI                   0x2B96
#define mmTCC_PERFCOUNTER3_HI__CI__VI                   0xD387
#define mmTCC_PERFCOUNTER3_HI__SI                       0x2B9B
#define mmTCC_PERFCOUNTER3_LO__CI__VI                   0xD386
#define mmTCC_PERFCOUNTER3_LO__SI                       0x2B9A
#define mmTCC_PERFCOUNTER3_SELECT__CI__VI               0xDB85
#define mmTCC_PERFCOUNTER3_SELECT__SI                   0x2B99
#define mmTCC_REDUNDANCY__CI__VI                        0x2B83
#define mmTCI_CNTL_1                                    0x2B62
#define mmTCI_CNTL_2                                    0x2B63
#define mmTCI_STATUS                                    0x2B61
#define mmTCP_ADDR_CONFIG                               0x2B05
#define mmTCP_BUFFER_ADDR_HASH_CNTL                     0x2B16
#define mmTCP_CHAN_STEER_HI                             0x2B04
#define mmTCP_CHAN_STEER_LO                             0x2B03
#define mmTCP_CNTL                                      0x2B02
#define mmTCP_CREDIT                                    0x2B06
#define mmTCP_EDC_COUNTER__SI__CI                       0x2B17
#define mmTCP_INVALIDATE                                0x2B00
#define mmTCP_PERFCOUNTER0_HI__CI__VI                   0xD341
#define mmTCP_PERFCOUNTER0_HI__SI                       0x2B0A
#define mmTCP_PERFCOUNTER0_LO__CI__VI                   0xD340
#define mmTCP_PERFCOUNTER0_LO__SI                       0x2B0B
#define mmTCP_PERFCOUNTER0_SELECT1__CI__VI              0xDB41
#define mmTCP_PERFCOUNTER0_SELECT__CI__VI               0xDB40
#define mmTCP_PERFCOUNTER0_SELECT__SI                   0x2B09
#define mmTCP_PERFCOUNTER1_HI__CI__VI                   0xD343
#define mmTCP_PERFCOUNTER1_HI__SI                       0x2B0D
#define mmTCP_PERFCOUNTER1_LO__CI__VI                   0xD342
#define mmTCP_PERFCOUNTER1_LO__SI                       0x2B0E
#define mmTCP_PERFCOUNTER1_SELECT1__CI__VI              0xDB43
#define mmTCP_PERFCOUNTER1_SELECT__CI__VI               0xDB42
#define mmTCP_PERFCOUNTER1_SELECT__SI                   0x2B0C
#define mmTCP_PERFCOUNTER2_HI__CI__VI                   0xD345
#define mmTCP_PERFCOUNTER2_HI__SI                       0x2B10
#define mmTCP_PERFCOUNTER2_LO__CI__VI                   0xD344
#define mmTCP_PERFCOUNTER2_LO__SI                       0x2B11
#define mmTCP_PERFCOUNTER2_SELECT__CI__VI               0xDB44
#define mmTCP_PERFCOUNTER2_SELECT__SI                   0x2B0F
#define mmTCP_PERFCOUNTER3_HI__CI__VI                   0xD347
#define mmTCP_PERFCOUNTER3_HI__SI                       0x2B13
#define mmTCP_PERFCOUNTER3_LO__CI__VI                   0xD346
#define mmTCP_PERFCOUNTER3_LO__SI                       0x2B14
#define mmTCP_PERFCOUNTER3_SELECT__CI__VI               0xDB45
#define mmTCP_PERFCOUNTER3_SELECT__SI                   0x2B12
#define mmTCP_STATUS                                    0x2B01
#define mmTCP_WATCH0_ADDR_H__CI__VI                     0x32A0
#define mmTCP_WATCH0_ADDR_L__CI__VI                     0x32A1
#define mmTCP_WATCH0_CNTL__CI__VI                       0x32A2
#define mmTCP_WATCH1_ADDR_H__CI__VI                     0x32A3
#define mmTCP_WATCH1_ADDR_L__CI__VI                     0x32A4
#define mmTCP_WATCH1_CNTL__CI__VI                       0x32A5
#define mmTCP_WATCH2_ADDR_H__CI__VI                     0x32A6
#define mmTCP_WATCH2_ADDR_L__CI__VI                     0x32A7
#define mmTCP_WATCH2_CNTL__CI__VI                       0x32A8
#define mmTCP_WATCH3_ADDR_H__CI__VI                     0x32A9
#define mmTCP_WATCH3_ADDR_L__CI__VI                     0x32AA
#define mmTCP_WATCH3_CNTL__CI__VI                       0x32AB
#define mmTCS_CGTT_SCLK_CTRL__CI                        0xF0AE
#define mmTCS_CTRL__CI                                  0x2BE0
#define mmTCS_PERFCOUNTER0_HI__CI                       0xD3A1
#define mmTCS_PERFCOUNTER0_LO__CI                       0xD3A0
#define mmTCS_PERFCOUNTER0_SELECT1__CI                  0xDBA1
#define mmTCS_PERFCOUNTER0_SELECT__CI                   0xDBA0
#define mmTCS_PERFCOUNTER1_HI__CI                       0xD3A3
#define mmTCS_PERFCOUNTER1_LO__CI                       0xD3A2
#define mmTCS_PERFCOUNTER1_SELECT__CI                   0xDBA2
#define mmTCS_PERFCOUNTER2_HI__CI                       0xD3A5
#define mmTCS_PERFCOUNTER2_LO__CI                       0xD3A4
#define mmTCS_PERFCOUNTER2_SELECT__CI                   0xDBA3
#define mmTCS_PERFCOUNTER3_HI__CI                       0xD3A7
#define mmTCS_PERFCOUNTER3_LO__CI                       0xD3A6
#define mmTCS_PERFCOUNTER3_SELECT__CI                   0xDBA4
#define mmTC_CFG_L1_LOAD_POLICY0__CI__VI                0x2B1A
#define mmTC_CFG_L1_LOAD_POLICY1__CI__VI                0x2B1B
#define mmTC_CFG_L1_STORE_POLICY__CI__VI                0x2B1C
#define mmTC_CFG_L1_VOLATILE__CI__VI                    0x2B22
#define mmTC_CFG_L2_ATOMIC_POLICY__CI__VI               0x2B21
#define mmTC_CFG_L2_LOAD_POLICY0__CI__VI                0x2B1D
#define mmTC_CFG_L2_LOAD_POLICY1__CI__VI                0x2B1E
#define mmTC_CFG_L2_STORE_POLICY0__CI__VI               0x2B1F
#define mmTC_CFG_L2_STORE_POLICY1__CI__VI               0x2B20
#define mmTC_CFG_L2_VOLATILE__CI__VI                    0x2B23
#define mmTD_CGTT_CTRL__CI__VI                          0xF09C
#define mmTD_CGTT_CTRL__SI                              0x2527
#define mmTD_CNTL                                       0x2525
#define mmTD_DEBUG_DATA                                 0x2529
#define mmTD_DEBUG_INDEX                                0x2528
#define mmTD_PERFCOUNTER0_HI__CI__VI                    0xD301
#define mmTD_PERFCOUNTER0_HI__SI                        0x252E
#define mmTD_PERFCOUNTER0_LO__CI__VI                    0xD300
#define mmTD_PERFCOUNTER0_LO__SI                        0x252D
#define mmTD_PERFCOUNTER0_SELECT1__CI__VI               0xDB01
#define mmTD_PERFCOUNTER0_SELECT__CI__VI                0xDB00
#define mmTD_PERFCOUNTER0_SELECT__SI                    0x252C
#define mmTD_PERFCOUNTER1_HI__CI__VI                    0xD303
#define mmTD_PERFCOUNTER1_LO__CI__VI                    0xD302
#define mmTD_PERFCOUNTER1_SELECT__CI__VI                0xDB02
#define mmTD_SCRATCH__CI__VI                            0x2533
#define mmTD_SCRATCH__SI                                0x2530
#define mmTD_STATUS                                     0x2526
#define mmTHM_CLK_CNTL__SI                              0x019A
#define mmTMDS_CNTL__SI                                 0x1C7C
#define mmTMDS_CONTROL0_FEEDBACK__SI                    0x1C7E
#define mmTMDS_CONTROL_CHAR__SI                         0x1C7D
#define mmTMDS_CTL0_1_GEN_CNTL__SI                      0x1C86
#define mmTMDS_CTL2_3_GEN_CNTL__SI                      0x1C87
#define mmTMDS_CTL_BITS__SI                             0x1C83
#define mmTMDS_DCBALANCER_CONTROL__SI                   0x1C84
#define mmTMDS_DEBUG__SI                                0x1C82
#define mmTMDS_STEREOSYNC_CTL_SEL__SI                   0x1C7F
#define mmTMDS_SYNC_CHAR_PATTERN_0_1__SI                0x1C80
#define mmTMDS_SYNC_CHAR_PATTERN_2_3__SI                0x1C81
#define mmUNIPHY_DATA_SYNCHRONIZATION__SI               0x1984
#define mmUNIPHY_IMPCAL_LINKA__SI                       0x1947
#define mmUNIPHY_IMPCAL_LINKB__SI                       0x1948
#define mmUNIPHY_IMPCAL_LINKC__SI                       0x194D
#define mmUNIPHY_IMPCAL_LINKD__SI                       0x194E
#define mmUNIPHY_IMPCAL_LINKE__SI                       0x1950
#define mmUNIPHY_IMPCAL_LINKF__SI                       0x1951
#define mmUNIPHY_IMPCAL_PERIOD__SI                      0x1949
#define mmUNIPHY_REG_TEST_OUTPUT__SI                    0x1986
#define mmUSER_SQC_BANK_DISABLE                         0x2308
#define mmUVD_CGC_CTRL__SI__VI                          0x3D2C
#define mmUVD_CGC_GATE__SI__VI                          0x3D2A
#define mmUVD_CGC_STATUS__SI__VI                        0x3D2B
#define mmUVD_CONFIG__CI__VI                            0x0F93
#define mmUVD_CONFIG__SI                                0x0F98
#define mmUVD_CONTEXT_ID__SI__VI                        0x3DBD
#define mmUVD_CTX_DATA__SI__VI                          0x3D29
#define mmUVD_CTX_INDEX__SI__VI                         0x3D28
#define mmUVD_ENGINE_CNTL__SI__VI                       0x3BC6
#define mmUVD_GPCOM_VCPU_CMD__SI__VI                    0x3BC3
#define mmUVD_GPCOM_VCPU_DATA0__SI__VI                  0x3BC4
#define mmUVD_GPCOM_VCPU_DATA1__SI__VI                  0x3BC5
#define mmUVD_LMI_ADDR_EXT__SI__VI                      0x3D65
#define mmUVD_LMI_CTRL2__SI__VI                         0x3D3D
#define mmUVD_LMI_CTRL__SI__VI                          0x3D66
#define mmUVD_LMI_EXT40_ADDR__SI__VI                    0x3D26
#define mmUVD_LMI_STATUS__SI__VI                        0x3D67
#define mmUVD_LMI_SWAP_CNTL__SI__VI                     0x3D6D
#define mmUVD_MASTINT_EN__SI__VI                        0x3D40
#define mmUVD_MPC_CNTL__SI__VI                          0x3D77
#define mmUVD_MPC_SET_ALU__SI__VI                       0x3D7E
#define mmUVD_MPC_SET_MUXA0__SI__VI                     0x3D79
#define mmUVD_MPC_SET_MUXA1__SI__VI                     0x3D7A
#define mmUVD_MPC_SET_MUXB0__SI__VI                     0x3D7B
#define mmUVD_MPC_SET_MUXB1__SI__VI                     0x3D7C
#define mmUVD_MPC_SET_MUX__SI__VI                       0x3D7D
#define mmUVD_MP_SWAP_CNTL__SI__VI                      0x3D6F
#define mmUVD_RBC_IB_BASE__SI                           0x3DA1
#define mmUVD_RBC_IB_SIZE__SI__VI                       0x3DA2
#define mmUVD_RBC_RB_BASE__SI                           0x3DA3
#define mmUVD_RBC_RB_CNTL__SI__VI                       0x3DA9
#define mmUVD_RBC_RB_RPTR_ADDR__SI__VI                  0x3DAA
#define mmUVD_RBC_RB_RPTR__SI__VI                       0x3DA4
#define mmUVD_RBC_RB_WPTR__SI__VI                       0x3DA5
#define mmUVD_SEMA_ADDR_HIGH__SI__VI                    0x3BC1
#define mmUVD_SEMA_ADDR_LOW__SI__VI                     0x3BC0
#define mmUVD_SEMA_CMD__SI__VI                          0x3BC2
#define mmUVD_SEMA_CNTL__SI__VI                         0x3D00
#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI__VI 0x3DB3
#define mmUVD_SEMA_TIMEOUT_STATUS__SI__VI               0x3DB0
#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI__VI      0x3DB2
#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI__VI 0x3DB1
#define mmUVD_SOFT_RESET__SI__VI                        0x3DA0
#define mmUVD_STATUS__SI__VI                            0x3DAF
#define mmUVD_VCPU_CACHE_OFFSET0__SI__VI                0x3D82
#define mmUVD_VCPU_CACHE_OFFSET1__SI__VI                0x3D84
#define mmUVD_VCPU_CACHE_OFFSET2__SI__VI                0x3D86
#define mmUVD_VCPU_CACHE_SIZE0__SI__VI                  0x3D83
#define mmUVD_VCPU_CACHE_SIZE1__SI__VI                  0x3D85
#define mmUVD_VCPU_CACHE_SIZE2__SI__VI                  0x3D87
#define mmUVD_VCPU_CNTL__SI__VI                         0x3D98
#define mmVBLANK_STATUS__SI                             0x1AEF
#define mmVCE_CONFIG__CI__VI                            0x0F94
#define mmVGA25_PPLL_FB_DIV__SI                         0x00DE
#define mmVGA25_PPLL_POST_DIV__SI                       0x00E2
#define mmVGA25_PPLL_REF_DIV__SI                        0x00D9
#define mmVGA28_PPLL_FB_DIV__SI                         0x00DF
#define mmVGA28_PPLL_POST_DIV__SI                       0x00E4
#define mmVGA28_PPLL_REF_DIV__SI                        0x00DB
#define mmVGA41_PPLL_FB_DIV__SI                         0x00E0
#define mmVGA41_PPLL_POST_DIV__SI                       0x00E6
#define mmVGA41_PPLL_REF_DIV__SI                        0x00DD
#define mmVGA_CACHE_CONTROL__SI__VI                     0x00CB
#define mmVGA_DEBUG_READBACK_DATA__SI__VI               0x00D7
#define mmVGA_DEBUG_READBACK_INDEX__SI__VI              0x00D6
#define mmVGA_DISPBUF1_SURFACE_ADDR__SI__VI             0x00C6
#define mmVGA_DISPBUF2_SURFACE_ADDR__SI__VI             0x00C8
#define mmVGA_HDP_CONTROL__SI__VI                       0x00CA
#define mmVGA_HW_DEBUG__SI__VI                          0x00CF
#define mmVGA_INTERRUPT_CONTROL__SI__VI                 0x00D1
#define mmVGA_INTERRUPT_STATUS__SI__VI                  0x00D3
#define mmVGA_MAIN_CONTROL__SI__VI                      0x00D4
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH__SI__VI          0x00C9
#define mmVGA_MEMORY_BASE_ADDRESS__SI__VI               0x00C4
#define mmVGA_MEM_READ_PAGE_ADDR__SI__VI                0x0013
#define mmVGA_MEM_WRITE_PAGE_ADDR__SI__VI               0x0012
#define mmVGA_MODE_CONTROL__SI__VI                      0x00C2
#define mmVGA_RENDER_CONTROL__SI__VI                    0x00C0
#define mmVGA_SEQUENCER_RESET_CONTROL__SI__VI           0x00C1
#define mmVGA_SOURCE_SELECT__SI__VI                     0x00FC
#define mmVGA_STATUS_CLEAR__SI__VI                      0x00D2
#define mmVGA_STATUS__SI__VI                            0x00D0
#define mmVGA_SURFACE_PITCH_SELECT__SI__VI              0x00C3
#define mmVGA_TEST_CONTROL__SI__VI                      0x00D5
#define mmVGA_TEST_DEBUG_DATA__SI__VI                   0x00C7
#define mmVGA_TEST_DEBUG_INDEX__SI__VI                  0x00C5
#define mmVGT_CACHE_INVALIDATION                        0x2231
#define mmVGT_CNTL_STATUS                               0x223C
#define mmVGT_DEBUG_CNTL                                0x2238
#define mmVGT_DEBUG_DATA                                0x2239
#define mmVGT_DMA_BASE                                  0xA1FA
#define mmVGT_DMA_BASE_HI                               0xA1F9
#define mmVGT_DMA_CONTROL__CI__VI                       0x2272
#define mmVGT_DMA_DATA_FIFO_DEPTH                       0x222D
#define mmVGT_DMA_INDEX_TYPE                            0xA29F
#define mmVGT_DMA_LS_HS_CONFIG__CI__VI                  0x2273
#define mmVGT_DMA_MAX_SIZE                              0xA29E
#define mmVGT_DMA_NUM_INSTANCES                         0xA2A2
#define mmVGT_DMA_PRIMITIVE_TYPE__CI__VI                0x2271
#define mmVGT_DMA_REQ_FIFO_DEPTH                        0x222E
#define mmVGT_DMA_SIZE                                  0xA29D
#define mmVGT_DRAW_INITIATOR                            0xA1FC
#define mmVGT_DRAW_INIT_FIFO_DEPTH                      0x222F
#define mmVGT_ENHANCE                                   0xA294
#define mmVGT_ESGS_RING_ITEMSIZE                        0xA2AB
#define mmVGT_ESGS_RING_SIZE__CI__VI                    0xC240
#define mmVGT_ESGS_RING_SIZE__SI                        0x2232
#define mmVGT_ES_PER_GS                                 0xA296
#define mmVGT_EVENT_ADDRESS_REG                         0xA1FE
#define mmVGT_EVENT_INITIATOR                           0xA2A4
#define mmVGT_FIFO_DEPTHS                               0x2234
#define mmVGT_GROUP_DECR                                0xA28B
#define mmVGT_GROUP_FIRST_DECR                          0xA28A
#define mmVGT_GROUP_PRIM_TYPE                           0xA289
#define mmVGT_GROUP_VECT_0_CNTL                         0xA28C
#define mmVGT_GROUP_VECT_0_FMT_CNTL                     0xA28E
#define mmVGT_GROUP_VECT_1_CNTL                         0xA28D
#define mmVGT_GROUP_VECT_1_FMT_CNTL                     0xA28F
#define mmVGT_GSVS_RING_ITEMSIZE                        0xA2AC
#define mmVGT_GSVS_RING_OFFSET_1                        0xA298
#define mmVGT_GSVS_RING_OFFSET_2                        0xA299
#define mmVGT_GSVS_RING_OFFSET_3                        0xA29A
#define mmVGT_GSVS_RING_SIZE__CI__VI                    0xC241
#define mmVGT_GSVS_RING_SIZE__SI                        0x2233
#define mmVGT_GS_INSTANCE_CNT                           0xA2E4
#define mmVGT_GS_MAX_VERT_OUT                           0xA2CE
#define mmVGT_GS_MODE                                   0xA290
#define mmVGT_GS_ONCHIP_CNTL__CI__VI                    0xA291
#define mmVGT_GS_OUT_PRIM_TYPE                          0xA29B
#define mmVGT_GS_PER_ES                                 0xA295
#define mmVGT_GS_PER_VS                                 0xA297
#define mmVGT_GS_VERTEX_REUSE                           0x2235
#define mmVGT_GS_VERT_ITEMSIZE                          0xA2D7
#define mmVGT_GS_VERT_ITEMSIZE_1                        0xA2D8
#define mmVGT_GS_VERT_ITEMSIZE_2                        0xA2D9
#define mmVGT_GS_VERT_ITEMSIZE_3                        0xA2DA
#define mmVGT_HOS_CNTL                                  0xA285
#define mmVGT_HOS_MAX_TESS_LEVEL                        0xA286
#define mmVGT_HOS_MIN_TESS_LEVEL                        0xA287
#define mmVGT_HOS_REUSE_DEPTH                           0xA288
#define mmVGT_HS_OFFCHIP_PARAM__CI__VI                  0xC24F
#define mmVGT_HS_OFFCHIP_PARAM__SI                      0x226C
#define mmVGT_IMMED_DATA                                0xA1FD
#define mmVGT_INDEX_TYPE__CI__VI                        0xC243
#define mmVGT_INDEX_TYPE__SI                            0x2257
#define mmVGT_INDX_OFFSET                               0xA102
#define mmVGT_INSTANCE_STEP_RATE_0                      0xA2A8
#define mmVGT_INSTANCE_STEP_RATE_1                      0xA2A9
#define mmVGT_LAST_COPY_STATE                           0x2230
#define mmVGT_LS_HS_CONFIG                              0xA2D6
#define mmVGT_MAX_VTX_INDX                              0xA100
#define mmVGT_MC_LAT_CNTL                               0x2236
#define mmVGT_MIN_VTX_INDX                              0xA101
#define mmVGT_MULTI_PRIM_IB_RESET_EN                    0xA2A5
#define mmVGT_MULTI_PRIM_IB_RESET_INDX                  0xA103
#define mmVGT_NUM_INDICES__CI__VI                       0xC24C
#define mmVGT_NUM_INDICES__SI                           0x225C
#define mmVGT_NUM_INSTANCES__CI__VI                     0xC24D
#define mmVGT_NUM_INSTANCES__SI                         0x225D
#define mmVGT_OUTPUT_PATH_CNTL                          0xA284
#define mmVGT_OUT_DEALLOC_CNTL                          0xA317
#define mmVGT_PERFCOUNTER0_HI__CI__VI                   0xD091
#define mmVGT_PERFCOUNTER0_HI__SI                       0x224D
#define mmVGT_PERFCOUNTER0_LO__CI__VI                   0xD090
#define mmVGT_PERFCOUNTER0_LO__SI                       0x224C
#define mmVGT_PERFCOUNTER0_SELECT1__CI__VI              0xD890
#define mmVGT_PERFCOUNTER0_SELECT__CI__VI               0xD88C
#define mmVGT_PERFCOUNTER0_SELECT__SI                   0x2248
#define mmVGT_PERFCOUNTER1_HI__CI__VI                   0xD093
#define mmVGT_PERFCOUNTER1_HI__SI                       0x224F
#define mmVGT_PERFCOUNTER1_LO__CI__VI                   0xD092
#define mmVGT_PERFCOUNTER1_LO__SI                       0x224E
#define mmVGT_PERFCOUNTER1_SELECT1__CI__VI              0xD891
#define mmVGT_PERFCOUNTER1_SELECT__CI__VI               0xD88D
#define mmVGT_PERFCOUNTER1_SELECT__SI                   0x2249
#define mmVGT_PERFCOUNTER2_HI__CI__VI                   0xD095
#define mmVGT_PERFCOUNTER2_HI__SI                       0x2251
#define mmVGT_PERFCOUNTER2_LO__CI__VI                   0xD094
#define mmVGT_PERFCOUNTER2_LO__SI                       0x2250
#define mmVGT_PERFCOUNTER2_SELECT__CI__VI               0xD88E
#define mmVGT_PERFCOUNTER2_SELECT__SI                   0x224A
#define mmVGT_PERFCOUNTER3_HI__CI__VI                   0xD097
#define mmVGT_PERFCOUNTER3_HI__SI                       0x2253
#define mmVGT_PERFCOUNTER3_LO__CI__VI                   0xD096
#define mmVGT_PERFCOUNTER3_LO__SI                       0x2252
#define mmVGT_PERFCOUNTER3_SELECT__CI__VI               0xD88F
#define mmVGT_PERFCOUNTER3_SELECT__SI                   0x224B
#define mmVGT_PERFCOUNTER_SEID_MASK__CI__VI             0xD894
#define mmVGT_PERFCOUNTER_SEID_MASK__SI                 0x2247
#define mmVGT_PRIMITIVEID_EN                            0xA2A1
#define mmVGT_PRIMITIVEID_RESET                         0xA2A3
#define mmVGT_PRIMITIVE_TYPE__CI__VI                    0xC242
#define mmVGT_PRIMITIVE_TYPE__SI                        0x2256
#define mmVGT_RESET_DEBUG__CI__VI                       0x2232
#define mmVGT_REUSE_OFF                                 0xA2AD
#define mmVGT_SHADER_STAGES_EN                          0xA2D5
#define mmVGT_STRMOUT_BUFFER_CONFIG                     0xA2E6
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0__CI__VI      0xC244
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0__SI          0x2258
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1__CI__VI      0xC245
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1__SI          0x2259
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2__CI__VI      0xC246
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2__SI          0x225A
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3__CI__VI      0xC247
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3__SI          0x225B
#define mmVGT_STRMOUT_BUFFER_OFFSET_0                   0xA2B7
#define mmVGT_STRMOUT_BUFFER_OFFSET_1                   0xA2BB
#define mmVGT_STRMOUT_BUFFER_OFFSET_2                   0xA2BF
#define mmVGT_STRMOUT_BUFFER_OFFSET_3                   0xA2C3
#define mmVGT_STRMOUT_BUFFER_SIZE_0                     0xA2B4
#define mmVGT_STRMOUT_BUFFER_SIZE_1                     0xA2B8
#define mmVGT_STRMOUT_BUFFER_SIZE_2                     0xA2BC
#define mmVGT_STRMOUT_BUFFER_SIZE_3                     0xA2C0
#define mmVGT_STRMOUT_CONFIG                            0xA2E5
#define mmVGT_STRMOUT_DELAY__CI__VI                     0x2233
#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE    0xA2CB
#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                0xA2CA
#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE         0xA2CC
#define mmVGT_STRMOUT_VTX_STRIDE_0                      0xA2B5
#define mmVGT_STRMOUT_VTX_STRIDE_1                      0xA2B9
#define mmVGT_STRMOUT_VTX_STRIDE_2                      0xA2BD
#define mmVGT_STRMOUT_VTX_STRIDE_3                      0xA2C1
#define mmVGT_SYS_CONFIG                                0x2263
#define mmVGT_TF_MEMORY_BASE__CI__VI                    0xC250
#define mmVGT_TF_MEMORY_BASE__SI                        0x226E
#define mmVGT_TF_PARAM                                  0xA2DB
#define mmVGT_TF_RING_SIZE__CI__VI                      0xC24E
#define mmVGT_TF_RING_SIZE__SI                          0x2262
#define mmVGT_VERTEX_REUSE_BLOCK_CNTL                   0xA316
#define mmVGT_VS_MAX_WAVE_ID__CI__VI                    0x2268
#define mmVGT_VTX_CNT_EN                                0xA2AE
#define mmVGT_VTX_VECT_EJECT_REG                        0x222C
#define mmVIEWPORT_SIZE__SI__VI                         0x1B5D
#define mmVIEWPORT_START__SI__VI                        0x1B5C
#define mmVLINE_STATUS__SI                              0x1AEE
#define mmVM_CONTEXT0_CNTL                              0x0504
#define mmVM_CONTEXT0_CNTL2                             0x050C
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR              0x054F
#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR               0x055F
#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR             0x0557
#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR             0x053E
#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR     0x0546
#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI 0x0538
#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS           0x0536
#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR             0x0510
#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR             0x0511
#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR             0x0512
#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR             0x0513
#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR             0x0514
#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR             0x0515
#define mmVM_CONTEXT1_CNTL                              0x0505
#define mmVM_CONTEXT1_CNTL2                             0x050D
#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR              0x0550
#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR               0x0560
#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR             0x0558
#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR             0x053F
#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR     0x0547
#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI 0x0539
#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS           0x0537
#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR              0x0551
#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR              0x0552
#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR              0x0553
#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR              0x0554
#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR              0x0555
#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR              0x0556
#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR              0x050E
#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR              0x050F
#define mmVM_CONTEXTS_DISABLE                           0x0535
#define mmVM_DEBUG                                      0x056F
#define mmVM_DUMMY_PAGE_FAULT_ADDR                      0x0507
#define mmVM_DUMMY_PAGE_FAULT_CNTL                      0x0506
#define mmVM_FAULT_CLIENT_ID                            0x054E
#define mmVM_INVALIDATE_REQUEST                         0x051E
#define mmVM_INVALIDATE_RESPONSE                        0x051F
#define mmVM_L2_BANK_SELECT_MASKA                       0x0572
#define mmVM_L2_BANK_SELECT_MASKB                       0x0573
#define mmVM_L2_CG                                      0x0570
#define mmVM_L2_CNTL                                    0x0500
#define mmVM_L2_CNTL2                                   0x0501
#define mmVM_L2_CNTL3                                   0x0502
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR    0x0576
#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR     0x0575
#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET        0x0577
#define mmVM_L2_STATUS                                  0x0503
#define mmVM_PRT_APERTURE0_HIGH_ADDR                    0x0530
#define mmVM_PRT_APERTURE0_LOW_ADDR                     0x052C
#define mmVM_PRT_APERTURE1_HIGH_ADDR                    0x0531
#define mmVM_PRT_APERTURE1_LOW_ADDR                     0x052D
#define mmVM_PRT_APERTURE2_HIGH_ADDR                    0x0532
#define mmVM_PRT_APERTURE2_LOW_ADDR                     0x052E
#define mmVM_PRT_APERTURE3_HIGH_ADDR                    0x0533
#define mmVM_PRT_APERTURE3_LOW_ADDR                     0x052F
#define mmVM_PRT_CNTL                                   0x0534
#define mmWD_CNTL_STATUS__CI__VI                        0x223F
#define mmWD_DEBUG_CNTL__CI__VI                         0x223D
#define mmWD_DEBUG_DATA__CI__VI                         0x223E
#define mmWD_ENHANCE__CI__VI                            0xA2A0
#define mmWD_PERFCOUNTER0_HI__CI__VI                    0xD081
#define mmWD_PERFCOUNTER0_LO__CI__VI                    0xD080
#define mmWD_PERFCOUNTER0_SELECT__CI__VI                0xD880
#define mmWD_PERFCOUNTER1_HI__CI__VI                    0xD083
#define mmWD_PERFCOUNTER1_LO__CI__VI                    0xD082
#define mmWD_PERFCOUNTER1_SELECT__CI__VI                0xD881
#define mmWD_PERFCOUNTER2_HI__CI__VI                    0xD085
#define mmWD_PERFCOUNTER2_LO__CI__VI                    0xD084
#define mmWD_PERFCOUNTER2_SELECT__CI__VI                0xD882
#define mmWD_PERFCOUNTER3_HI__CI__VI                    0xD087
#define mmWD_PERFCOUNTER3_LO__CI__VI                    0xD086
#define mmWD_PERFCOUNTER3_SELECT__CI__VI                0xD883
#define mmXDMA_SLV_FLIP_PENDING__CI__VI                 0x046C
#define mmXDMA_SLV_FLIP_PENDING__SI                     0x0407
#define pciADAPTER_ID                                   0x000B
#define pciADAPTER_ID_W                                 0x0013
#define pciBASE_ADDR_1                                  0x0004
#define pciBASE_ADDR_2                                  0x0005
#define pciBASE_ADDR_3                                  0x0006
#define pciBASE_ADDR_4                                  0x0007
#define pciBASE_ADDR_5                                  0x0008
#define pciBASE_ADDR_6                                  0x0009
#define pciBASE_CLASS                                   0x0002
#define pciBIST                                         0x0003
#define pciCACHE_LINE                                   0x0003
#define pciCAP_PTR                                      0x000D
#define pciCOMMAND                                      0x0001
#define pciDEVICE_CAP                                   0x0017
#define pciDEVICE_CAP2                                  0x001F
#define pciDEVICE_CNTL                                  0x0018
#define pciDEVICE_CNTL2                                 0x0020
#define pciDEVICE_ID                                    0x0000
#define pciDEVICE_STATUS                                0x0018
#define pciDEVICE_STATUS2                               0x0020
#define pciHEADER                                       0x0003
#define pciINTERRUPT_LINE                               0x000F
#define pciINTERRUPT_PIN                                0x000F
#define pciLATENCY                                      0x0003
#define pciLINK_CAP                                     0x0019
#define pciLINK_CAP2                                    0x0021
#define pciLINK_CNTL                                    0x001A
#define pciLINK_CNTL2                                   0x0022
#define pciLINK_STATUS                                  0x001A
#define pciLINK_STATUS2                                 0x0022
#define pciMAX_LATENCY                                  0x000F
#define pciMIN_GRANT                                    0x000F
#define pciMSI_CAP_LIST                                 0x0028
#define pciMSI_MSG_ADDR_HI                              0x002A
#define pciMSI_MSG_ADDR_LO                              0x0029
#define pciMSI_MSG_CNTL                                 0x0028
#define pciMSI_MSG_DATA                                 0x002A
#define pciMSI_MSG_DATA_64                              0x002B
#define pciPCIE_ACS_CAP__CI__VI                         0x00A9
#define pciPCIE_ACS_CNTL__CI__VI                        0x00A9
#define pciPCIE_ACS_ENH_CAP_LIST__CI__VI                0x00A8
#define pciPCIE_ADV_ERR_CAP_CNTL                        0x005A
#define pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST                0x0054
#define pciPCIE_ATS_CAP__CI__VI                         0x00AD
#define pciPCIE_ATS_CNTL__CI__VI                        0x00AD
#define pciPCIE_ATS_ENH_CAP_LIST__CI__VI                0x00AC
#define pciPCIE_BAR1_CAP__CI__VI                        0x0081
#define pciPCIE_BAR1_CNTL__CI__VI                       0x0082
#define pciPCIE_BAR2_CAP__CI__VI                        0x0083
#define pciPCIE_BAR2_CNTL__CI__VI                       0x0084
#define pciPCIE_BAR3_CAP__CI__VI                        0x0085
#define pciPCIE_BAR3_CNTL__CI__VI                       0x0086
#define pciPCIE_BAR4_CAP__CI__VI                        0x0087
#define pciPCIE_BAR4_CNTL__CI__VI                       0x0088
#define pciPCIE_BAR5_CAP__CI__VI                        0x0089
#define pciPCIE_BAR5_CNTL__CI__VI                       0x008A
#define pciPCIE_BAR6_CAP__CI__VI                        0x008B
#define pciPCIE_BAR6_CNTL__CI__VI                       0x008C
#define pciPCIE_BAR_ENH_CAP_LIST__CI__VI                0x0080
#define pciPCIE_CAP                                     0x0016
#define pciPCIE_CAP_LIST                                0x0016
#define pciPCIE_CORR_ERR_MASK                           0x0059
#define pciPCIE_CORR_ERR_STATUS                         0x0058
#define pciPCIE_DEV_SERIAL_NUM_DW1                      0x0051
#define pciPCIE_DEV_SERIAL_NUM_DW2                      0x0052
#define pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST             0x0050
#define pciPCIE_DPA_CAP__CI__VI                         0x0095
#define pciPCIE_DPA_CNTL__CI__VI                        0x0097
#define pciPCIE_DPA_ENH_CAP_LIST__CI__VI                0x0094
#define pciPCIE_DPA_LATENCY_INDICATOR__CI__VI           0x0096
#define pciPCIE_DPA_STATUS__CI__VI                      0x0097
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI        0x0098
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI        0x0098
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI        0x0098
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI        0x0098
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI        0x0099
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI        0x0099
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI        0x0099
#define pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI        0x0099
#define pciPCIE_HDR_LOG0                                0x005B
#define pciPCIE_HDR_LOG1                                0x005C
#define pciPCIE_HDR_LOG2                                0x005D
#define pciPCIE_HDR_LOG3                                0x005E
#define pciPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI        0x009F
#define pciPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI       0x00A4
#define pciPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI       0x00A4
#define pciPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI       0x00A5
#define pciPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI       0x00A5
#define pciPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI       0x00A6
#define pciPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI       0x00A6
#define pciPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI        0x009F
#define pciPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI        0x00A0
#define pciPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI        0x00A0
#define pciPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI        0x00A1
#define pciPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI        0x00A1
#define pciPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI        0x00A2
#define pciPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI        0x00A2
#define pciPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI        0x00A3
#define pciPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI        0x00A3
#define pciPCIE_LANE_ERROR_STATUS__CI__VI               0x009E
#define pciPCIE_LINK_CNTL3__CI__VI                      0x009D
#define pciPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI         0x00B3
#define pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI      0x00B2
#define pciPCIE_PAGE_REQ_CNTL__CI__VI                   0x00B1
#define pciPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI           0x00B0
#define pciPCIE_PAGE_REQ_STATUS__CI__VI                 0x00B1
#define pciPCIE_PASID_CAP__CI__VI                       0x00B5
#define pciPCIE_PASID_CNTL__CI__VI                      0x00B5
#define pciPCIE_PASID_ENH_CAP_LIST__CI__VI              0x00B4
#define pciPCIE_PORT_VC_CAP_REG1                        0x0045
#define pciPCIE_PORT_VC_CAP_REG2                        0x0046
#define pciPCIE_PORT_VC_CNTL                            0x0047
#define pciPCIE_PORT_VC_STATUS                          0x0047
#define pciPCIE_PWR_BUDGET_CAP__CI__VI                  0x0093
#define pciPCIE_PWR_BUDGET_DATA_SELECT__CI__VI          0x0091
#define pciPCIE_PWR_BUDGET_DATA__CI__VI                 0x0092
#define pciPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI         0x0090
#define pciPCIE_SECONDARY_ENH_CAP_LIST__CI__VI          0x009C
#define pciPCIE_TLP_PREFIX_LOG0__CI__VI                 0x0062
#define pciPCIE_TLP_PREFIX_LOG1__CI__VI                 0x0063
#define pciPCIE_TLP_PREFIX_LOG2__CI__VI                 0x0064
#define pciPCIE_TLP_PREFIX_LOG3__CI__VI                 0x0065
#define pciPCIE_UNCORR_ERR_MASK                         0x0056
#define pciPCIE_UNCORR_ERR_SEVERITY                     0x0057
#define pciPCIE_UNCORR_ERR_STATUS                       0x0055
#define pciPCIE_VC0_RESOURCE_CAP                        0x0048
#define pciPCIE_VC0_RESOURCE_CNTL                       0x0049
#define pciPCIE_VC0_RESOURCE_STATUS                     0x004A
#define pciPCIE_VC1_RESOURCE_CAP                        0x004B
#define pciPCIE_VC1_RESOURCE_CNTL                       0x004C
#define pciPCIE_VC1_RESOURCE_STATUS                     0x004D
#define pciPCIE_VC_ENH_CAP_LIST                         0x0044
#define pciPCIE_VENDOR_SPECIFIC1                        0x0042
#define pciPCIE_VENDOR_SPECIFIC2                        0x0043
#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST            0x0040
#define pciPCIE_VENDOR_SPECIFIC_HDR                     0x0041
#define pciPMI_CAP                                      0x0014
#define pciPMI_CAP_LIST                                 0x0014
#define pciPMI_STATUS_CNTL                              0x0015
#define pciPROG_INTERFACE                               0x0002
#define pciREVISION_ID                                  0x0002
#define pciROM_BASE_ADDR                                0x000C
#define pciSTATUS                                       0x0001
#define pciSUB_CLASS                                    0x0002
#define pciVENDOR_CAP_LIST__CI__VI                      0x0012
#define pciVENDOR_ID                                    0x0000

//Merged Defines

#define cfgMSI_MASK__VI                                 0x002B
#define cfgMSI_MASK_64__VI                              0x002C
#define cfgMSI_PENDING__VI                              0x002C
#define cfgMSI_PENDING_64__VI                           0x002D
#define cfgPCIE_ARI_CAP__VI                             0x00CB
#define cfgPCIE_ARI_CNTL__VI                            0x00CB
#define cfgPCIE_ARI_ENH_CAP_LIST__VI                    0x00CA
#define cfgPCIE_LTR_CAP__VI                             0x00C9
#define cfgPCIE_LTR_ENH_CAP_LIST__VI                    0x00C8
#define cfgPCIE_MC_ADDR0__VI                            0x00BE
#define cfgPCIE_MC_ADDR1__VI                            0x00BF
#define cfgPCIE_MC_BLOCK_ALL0__VI                       0x00C2
#define cfgPCIE_MC_BLOCK_ALL1__VI                       0x00C3
#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0__VI             0x00C4
#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1__VI             0x00C5
#define cfgPCIE_MC_CAP__VI                              0x00BD
#define cfgPCIE_MC_CNTL__VI                             0x00BD
#define cfgPCIE_MC_ENH_CAP_LIST__VI                     0x00BC
#define cfgPCIE_MC_RCV0__VI                             0x00C0
#define cfgPCIE_MC_RCV1__VI                             0x00C1
#define cfgPCIE_SRIOV_CAP__VI                           0x00CD
#define cfgPCIE_SRIOV_CONTROL__VI                       0x00CE
#define cfgPCIE_SRIOV_ENH_CAP_LIST__VI                  0x00CC
#define cfgPCIE_SRIOV_FIRST_VF_OFFSET__VI               0x00D1
#define cfgPCIE_SRIOV_FUNC_DEP_LINK__VI                 0x00D0
#define cfgPCIE_SRIOV_INITIAL_VFS__VI                   0x00CF
#define cfgPCIE_SRIOV_NUM_VFS__VI                       0x00D0
#define cfgPCIE_SRIOV_STATUS__VI                        0x00CE
#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI           0x00D3
#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI              0x00D4
#define cfgPCIE_SRIOV_TOTAL_VFS__VI                     0x00CF
#define cfgPCIE_SRIOV_VF_BASE_ADDR_0__VI                0x00D5
#define cfgPCIE_SRIOV_VF_BASE_ADDR_1__VI                0x00D6
#define cfgPCIE_SRIOV_VF_BASE_ADDR_2__VI                0x00D7
#define cfgPCIE_SRIOV_VF_BASE_ADDR_3__VI                0x00D8
#define cfgPCIE_SRIOV_VF_BASE_ADDR_4__VI                0x00D9
#define cfgPCIE_SRIOV_VF_BASE_ADDR_5__VI                0x00DA
#define cfgPCIE_SRIOV_VF_DEVICE_ID__VI                  0x00D2
#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI 0x00DB
#define cfgPCIE_SRIOV_VF_STRIDE__VI                     0x00D1
#define cfgPCIE_TPH_REQR_CAP__VI                        0x00B9
#define cfgPCIE_TPH_REQR_CNTL__VI                       0x00BA
#define cfgPCIE_TPH_REQR_ENH_CAP_LIST__VI               0x00B8
#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI 0x0100
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI          0x0101
#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI 0x0105
#define mmAFMT_60958_0__VI                              0x4A38
#define mmAFMT_60958_1__VI                              0x4A39
#define mmAFMT_60958_2__VI                              0x4A3F
#define mmAFMT_AUDIO_CRC_CONTROL__VI                    0x4A3A
#define mmAFMT_AUDIO_CRC_RESULT__VI                     0x4A40
#define mmAFMT_AUDIO_DBG_DTO_CNTL__VI                   0x4A46
#define mmAFMT_AUDIO_INFO0__VI                          0x4A36
#define mmAFMT_AUDIO_INFO1__VI                          0x4A37
#define mmAFMT_AUDIO_PACKET_CONTROL__VI                 0x4A42
#define mmAFMT_AUDIO_PACKET_CONTROL2__VI                0x4A14
#define mmAFMT_AUDIO_SRC_CONTROL__VI                    0x4A45
#define mmAFMT_AVI_INFO0__VI                            0x4A1E
#define mmAFMT_AVI_INFO1__VI                            0x4A1F
#define mmAFMT_AVI_INFO2__VI                            0x4A20
#define mmAFMT_AVI_INFO3__VI                            0x4A21
#define mmAFMT_GENERIC_0__VI                            0x4A25
#define mmAFMT_GENERIC_1__VI                            0x4A26
#define mmAFMT_GENERIC_2__VI                            0x4A27
#define mmAFMT_GENERIC_3__VI                            0x4A28
#define mmAFMT_GENERIC_4__VI                            0x4A29
#define mmAFMT_GENERIC_5__VI                            0x4A2A
#define mmAFMT_GENERIC_6__VI                            0x4A2B
#define mmAFMT_GENERIC_7__VI                            0x4A2C
#define mmAFMT_GENERIC_HDR__VI                          0x4A24
#define mmAFMT_INFOFRAME_CONTROL0__VI                   0x4A44
#define mmAFMT_ISRC1_0__VI                              0x4A15
#define mmAFMT_ISRC1_1__VI                              0x4A16
#define mmAFMT_ISRC1_2__VI                              0x4A17
#define mmAFMT_ISRC1_3__VI                              0x4A18
#define mmAFMT_ISRC1_4__VI                              0x4A19
#define mmAFMT_ISRC2_0__VI                              0x4A1A
#define mmAFMT_ISRC2_1__VI                              0x4A1B
#define mmAFMT_ISRC2_2__VI                              0x4A1C
#define mmAFMT_ISRC2_3__VI                              0x4A1D
#define mmAFMT_MPEG_INFO0__VI                           0x4A22
#define mmAFMT_MPEG_INFO1__VI                           0x4A23
#define mmAFMT_RAMP_CONTROL0__VI                        0x4A3B
#define mmAFMT_RAMP_CONTROL1__VI                        0x4A3C
#define mmAFMT_RAMP_CONTROL2__VI                        0x4A3D
#define mmAFMT_RAMP_CONTROL3__VI                        0x4A3E
#define mmAFMT_STATUS__VI                               0x4A41
#define mmAFMT_VBI_PACKET_CONTROL__VI                   0x4A43
#define mmALPHA_CONTROL__VI                             0x1ABC
#define mmATC_ATS_FAULT_STATUS_INFO2__VI                0x0CD2
#define mmATC_ATS_SMU_STATUS__VI                        0x0D08
#define mmATC_ATS_VMID_STATUS__VI                       0x0D07
#define mmATC_L1RD_DEBUG2_TLB__VI                       0x0CE2
#define mmATC_L1WR_DEBUG2_TLB__VI                       0x0CE3
#define mmATC_L2_CACHE_DATA0__VI                        0x0CD9
#define mmATC_L2_CACHE_DATA1__VI                        0x0CDA
#define mmATC_L2_CACHE_DATA2__VI                        0x0CDB
#define mmATC_L2_CNTL3__VI                              0x0D08
#define mmATC_L2_STATUS__VI                             0x0D09
#define mmATC_L2_STATUS2__VI                            0x0D0A
#define mmAUXN_IMPCAL__VI                               0x483C
#define mmAUXP_IMPCAL__VI                               0x483B
#define mmAUX_ARB_CONTROL__VI                           0x5C02
#define mmAUX_CONTROL__VI                               0x5C00
#define mmAUX_DPHY_RX_CONTROL0__VI                      0x5C0A
#define mmAUX_DPHY_RX_CONTROL1__VI                      0x5C0B
#define mmAUX_DPHY_RX_STATUS__VI                        0x5C0D
#define mmAUX_DPHY_TX_CONTROL__VI                       0x5C09
#define mmAUX_DPHY_TX_REF_CONTROL__VI                   0x5C08
#define mmAUX_DPHY_TX_STATUS__VI                        0x5C0C
#define mmAUX_GTC_SYNC_CONTROL__VI                      0x5C0E
#define mmAUX_GTC_SYNC_CONTROLLER_STATUS__VI            0x5C10
#define mmAUX_GTC_SYNC_DATA__VI                         0x5C12
#define mmAUX_GTC_SYNC_ERROR_CONTROL__VI                0x5C0F
#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI        0x5C13
#define mmAUX_GTC_SYNC_STATUS__VI                       0x5C11
#define mmAUX_INTERRUPT_CONTROL__VI                     0x5C03
#define mmAUX_LS_DATA__VI                               0x5C07
#define mmAUX_LS_STATUS__VI                             0x5C05
#define mmAUX_SW_CONTROL__VI                            0x5C01
#define mmAUX_SW_DATA__VI                               0x5C06
#define mmAUX_SW_STATUS__VI                             0x5C04
#define mmAUX_TEST_DEBUG_DATA__VI                       0x5C15
#define mmAUX_TEST_DEBUG_INDEX__VI                      0x5C14
#define mmAVSYNC_COUNTER_CONTROL__VI                    0x012B
#define mmAVSYNC_COUNTER_READ__VI                       0x012F
#define mmAVSYNC_COUNTER_WRITE__VI                      0x012A
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__VI 0x17F3
#define mmAZALIA_AUDIO_DTO__VI                          0x17E5
#define mmAZALIA_AUDIO_DTO_CONTROL__VI                  0x17E6
#define mmAZALIA_BDL_DMA_CONTROL__VI                    0x17EA
#define mmAZALIA_CONTROLLER_CLOCK_GATING__VI            0x17E4
#define mmAZALIA_CONTROLLER_DEBUG__VI                   0x17F9
#define mmAZALIA_CORB_DMA_CONTROL__VI                   0x17EC
#define mmAZALIA_CRC0_CONTROL0__VI                      0x1805
#define mmAZALIA_CRC0_CONTROL1__VI                      0x1806
#define mmAZALIA_CRC0_CONTROL2__VI                      0x1807
#define mmAZALIA_CRC0_CONTROL3__VI                      0x1808
#define mmAZALIA_CRC0_RESULT__VI                        0x1809
#define mmAZALIA_CRC1_CONTROL0__VI                      0x180A
#define mmAZALIA_CRC1_CONTROL1__VI                      0x180B
#define mmAZALIA_CRC1_CONTROL2__VI                      0x180C
#define mmAZALIA_CRC1_CONTROL3__VI                      0x180D
#define mmAZALIA_CRC1_RESULT__VI                        0x180E
#define mmAZALIA_CYCLIC_BUFFER_SYNC__VI                 0x17F4
#define mmAZALIA_DATA_DMA_CONTROL__VI                   0x17E9
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__VI     0x182A
#define mmAZALIA_F0_CODEC_DEBUG__VI                     0x1836
#define mmAZALIA_F0_CODEC_ENDPOINT_DATA__VI             0x17A9
#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX__VI            0x17A8
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI 0x1833
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__VI 0x1830
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__VI    0x1831
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__VI 0x1832
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__VI 0x182C
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI 0x182F
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__VI 0x182E
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__VI 0x182D
#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI       0x59D5
#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI      0x59D4
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__VI       0x182B
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__VI 0x1829
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__VI 0x1828
#define mmAZALIA_F0_GTC_GROUP_OFFSET0__VI               0x1837
#define mmAZALIA_F0_GTC_GROUP_OFFSET1__VI               0x1838
#define mmAZALIA_F0_GTC_GROUP_OFFSET2__VI               0x1839
#define mmAZALIA_F0_GTC_GROUP_OFFSET3__VI               0x183A
#define mmAZALIA_F0_GTC_GROUP_OFFSET4__VI               0x183B
#define mmAZALIA_F0_GTC_GROUP_OFFSET5__VI               0x183C
#define mmAZALIA_F0_GTC_GROUP_OFFSET6__VI               0x183D
#define mmAZALIA_GLOBAL_CAPABILITIES__VI                0x17F5
#define mmAZALIA_INPUT_CRC0_CONTROL0__VI                0x17FB
#define mmAZALIA_INPUT_CRC0_CONTROL1__VI                0x17FC
#define mmAZALIA_INPUT_CRC0_CONTROL2__VI                0x17FD
#define mmAZALIA_INPUT_CRC0_CONTROL3__VI                0x17FE
#define mmAZALIA_INPUT_CRC0_RESULT__VI                  0x17FF
#define mmAZALIA_INPUT_CRC1_CONTROL0__VI                0x1800
#define mmAZALIA_INPUT_CRC1_CONTROL1__VI                0x1801
#define mmAZALIA_INPUT_CRC1_CONTROL2__VI                0x1802
#define mmAZALIA_INPUT_CRC1_CONTROL3__VI                0x1803
#define mmAZALIA_INPUT_CRC1_RESULT__VI                  0x1804
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY__VI           0x17F8
#define mmAZALIA_MEM_PWR_CTRL__VI                       0x1810
#define mmAZALIA_MEM_PWR_STATUS__VI                     0x1811
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY__VI          0x17F6
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL__VI      0x17F7
#define mmAZALIA_RIRB_AND_DP_CONTROL__VI                0x17EB
#define mmAZALIA_SCLK_CONTROL__VI                       0x17E7
#define mmAZALIA_STREAM_DATA__VI                        0x1781
#define mmAZALIA_STREAM_INDEX__VI                       0x1780
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE__VI            0x17E8
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17A9
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17A8
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17AD
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17AC
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17B1
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17B0
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17B5
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17B4
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17B9
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17B8
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17BD
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17BC
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17C1
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17C0
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__VI 0x17C5
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI 0x17C4
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59D5
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59D4
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59D9
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59D8
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59DD
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59DC
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59E1
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59E0
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59E5
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59E4
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59E9
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59E8
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59ED
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59EC
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI 0x59F1
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI 0x59F0
#define mmAZF0STREAM0_AZALIA_STREAM_DATA__VI            0x1781
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX__VI           0x1780
#define mmAZF0STREAM10_AZALIA_STREAM_DATA__VI           0x59C5
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX__VI          0x59C4
#define mmAZF0STREAM11_AZALIA_STREAM_DATA__VI           0x59C7
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX__VI          0x59C6
#define mmAZF0STREAM12_AZALIA_STREAM_DATA__VI           0x59C9
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX__VI          0x59C8
#define mmAZF0STREAM13_AZALIA_STREAM_DATA__VI           0x59CB
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX__VI          0x59CA
#define mmAZF0STREAM14_AZALIA_STREAM_DATA__VI           0x59CD
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX__VI          0x59CC
#define mmAZF0STREAM15_AZALIA_STREAM_DATA__VI           0x59CF
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX__VI          0x59CE
#define mmAZF0STREAM1_AZALIA_STREAM_DATA__VI            0x1783
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX__VI           0x1782
#define mmAZF0STREAM2_AZALIA_STREAM_DATA__VI            0x1785
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX__VI           0x1784
#define mmAZF0STREAM3_AZALIA_STREAM_DATA__VI            0x1787
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX__VI           0x1786
#define mmAZF0STREAM4_AZALIA_STREAM_DATA__VI            0x1789
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX__VI           0x1788
#define mmAZF0STREAM5_AZALIA_STREAM_DATA__VI            0x178B
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX__VI           0x178A
#define mmAZF0STREAM6_AZALIA_STREAM_DATA__VI            0x178D
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX__VI           0x178C
#define mmAZF0STREAM7_AZALIA_STREAM_DATA__VI            0x178F
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX__VI           0x178E
#define mmAZF0STREAM8_AZALIA_STREAM_DATA__VI            0x59C1
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX__VI           0x59C0
#define mmAZF0STREAM9_AZALIA_STREAM_DATA__VI            0x59C3
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX__VI           0x59C2
#define mmAZ_TEST_DEBUG_DATA__VI                        0x1820
#define mmAZ_TEST_DEBUG_INDEX__VI                       0x181F
#define mmBF_ANA_ISO_CNTL__VI                           0x14C7
#define mmBIF_ATOMIC_ERR_LOG__VI                        0x1512
#define mmBIF_BME_STATUS__VI                            0x1511
#define mmBIF_CLK_CTRL__VI                              0x14C5
#define mmBIF_DOORBELL_APER_EN__VI                      0x1501
#define mmBIF_DOORBELL_GBLAPER1_LOWER__VI               0x14FC
#define mmBIF_DOORBELL_GBLAPER1_UPPER__VI               0x14FD
#define mmBIF_DOORBELL_GBLAPER2_LOWER__VI               0x14FE
#define mmBIF_DOORBELL_GBLAPER2_UPPER__VI               0x14FF
#define mmBIF_GPUIOV_FB_TOTAL_FB_INFO__VI               0x14D8
#define mmBIF_GPUIOV_RESET_NOTIFICATION__VI             0x14D5
#define mmBIF_GPUIOV_VM_INIT_STATUS__VI                 0x14D6
#define mmBIF_IOV_FUNC_IDENTIFIER__VI                   0x1503
#define mmBIF_MM_INDACCESS_CNTL__VI                     0x1500
#define mmBIF_MST_TRANS_PENDING__VI                     0x14EA
#define mmBIF_RB_BASE__VI                               0x1531
#define mmBIF_RB_CNTL__VI                               0x1530
#define mmBIF_RB_RPTR__VI                               0x1532
#define mmBIF_RB_WPTR__VI                               0x1533
#define mmBIF_RB_WPTR_ADDR_HI__VI                       0x1534
#define mmBIF_RB_WPTR_ADDR_LO__VI                       0x1535
#define mmBIF_RFE_MST_BX_CMDSTATUS__VI                  0x1449
#define mmBIF_RFE_MST_SMBUS_CMDSTATUS__VI               0x1448
#define mmBIF_RFE_WARMRST_CNTL__VI                      0x1459
#define mmBIF_RLC_INTR_CNTL__VI                         0x1510
#define mmBIF_SLV_TRANS_PENDING__VI                     0x14E9
#define mmBIF_SMU_DATA__VI                              0x143E
#define mmBIF_SMU_INDEX__VI                             0x143D
#define mmBIF_VDDGFX_FB_CMP__VI                         0x143C
#define mmBIF_VDDGFX_GFX0_LOWER__VI                     0x1428
#define mmBIF_VDDGFX_GFX0_UPPER__VI                     0x1429
#define mmBIF_VDDGFX_GFX1_LOWER__VI                     0x142A
#define mmBIF_VDDGFX_GFX1_UPPER__VI                     0x142B
#define mmBIF_VDDGFX_GFX2_LOWER__VI                     0x142C
#define mmBIF_VDDGFX_GFX2_UPPER__VI                     0x142D
#define mmBIF_VDDGFX_GFX3_LOWER__VI                     0x142E
#define mmBIF_VDDGFX_GFX3_UPPER__VI                     0x142F
#define mmBIF_VDDGFX_GFX4_LOWER__VI                     0x1430
#define mmBIF_VDDGFX_GFX4_UPPER__VI                     0x1431
#define mmBIF_VDDGFX_GFX5_LOWER__VI                     0x1432
#define mmBIF_VDDGFX_GFX5_UPPER__VI                     0x1433
#define mmBIF_VDDGFX_RSV1_LOWER__VI                     0x1434
#define mmBIF_VDDGFX_RSV1_UPPER__VI                     0x1435
#define mmBIF_VDDGFX_RSV2_LOWER__VI                     0x1436
#define mmBIF_VDDGFX_RSV2_UPPER__VI                     0x1437
#define mmBIF_VDDGFX_RSV3_LOWER__VI                     0x1438
#define mmBIF_VDDGFX_RSV3_UPPER__VI                     0x1439
#define mmBIF_VDDGFX_RSV4_LOWER__VI                     0x143A
#define mmBIF_VDDGFX_RSV4_UPPER__VI                     0x143B
#define mmBIF_VIRT_RESET_REQ__VI                        0x14D2
#define mmBLND0_BLND_CONTROL__VI                        0x1B6D
#define mmBLND0_BLND_CONTROL2__VI                       0x1B6F
#define mmBLND0_BLND_DEBUG__VI                          0x1B74
#define mmBLND0_BLND_REG_UPDATE_STATUS__VI              0x1B77
#define mmBLND0_BLND_TEST_DEBUG_DATA__VI                0x1B76
#define mmBLND0_BLND_TEST_DEBUG_INDEX__VI               0x1B75
#define mmBLND0_BLND_UNDERFLOW_INTERRUPT__VI            0x1B71
#define mmBLND0_BLND_UPDATE__VI                         0x1B70
#define mmBLND0_BLND_V_UPDATE_LOCK__VI                  0x1B73
#define mmBLND0_SM_CONTROL2__VI                         0x1B6E
#define mmBLND1_BLND_CONTROL__VI                        0x1D6D
#define mmBLND1_BLND_CONTROL2__VI                       0x1D6F
#define mmBLND1_BLND_DEBUG__VI                          0x1D74
#define mmBLND1_BLND_REG_UPDATE_STATUS__VI              0x1D77
#define mmBLND1_BLND_TEST_DEBUG_DATA__VI                0x1D76
#define mmBLND1_BLND_TEST_DEBUG_INDEX__VI               0x1D75
#define mmBLND1_BLND_UNDERFLOW_INTERRUPT__VI            0x1D71
#define mmBLND1_BLND_UPDATE__VI                         0x1D70
#define mmBLND1_BLND_V_UPDATE_LOCK__VI                  0x1D73
#define mmBLND1_SM_CONTROL2__VI                         0x1D6E
#define mmBLND2_BLND_CONTROL__VI                        0x1F6D
#define mmBLND2_BLND_CONTROL2__VI                       0x1F6F
#define mmBLND2_BLND_DEBUG__VI                          0x1F74
#define mmBLND2_BLND_REG_UPDATE_STATUS__VI              0x1F77
#define mmBLND2_BLND_TEST_DEBUG_DATA__VI                0x1F76
#define mmBLND2_BLND_TEST_DEBUG_INDEX__VI               0x1F75
#define mmBLND2_BLND_UNDERFLOW_INTERRUPT__VI            0x1F71
#define mmBLND2_BLND_UPDATE__VI                         0x1F70
#define mmBLND2_BLND_V_UPDATE_LOCK__VI                  0x1F73
#define mmBLND2_SM_CONTROL2__VI                         0x1F6E
#define mmBLND3_BLND_CONTROL__VI                        0x416D
#define mmBLND3_BLND_CONTROL2__VI                       0x416F
#define mmBLND3_BLND_DEBUG__VI                          0x4174
#define mmBLND3_BLND_REG_UPDATE_STATUS__VI              0x4177
#define mmBLND3_BLND_TEST_DEBUG_DATA__VI                0x4176
#define mmBLND3_BLND_TEST_DEBUG_INDEX__VI               0x4175
#define mmBLND3_BLND_UNDERFLOW_INTERRUPT__VI            0x4171
#define mmBLND3_BLND_UPDATE__VI                         0x4170
#define mmBLND3_BLND_V_UPDATE_LOCK__VI                  0x4173
#define mmBLND3_SM_CONTROL2__VI                         0x416E
#define mmBLND4_BLND_CONTROL__VI                        0x436D
#define mmBLND4_BLND_CONTROL2__VI                       0x436F
#define mmBLND4_BLND_DEBUG__VI                          0x4374
#define mmBLND4_BLND_REG_UPDATE_STATUS__VI              0x4377
#define mmBLND4_BLND_TEST_DEBUG_DATA__VI                0x4376
#define mmBLND4_BLND_TEST_DEBUG_INDEX__VI               0x4375
#define mmBLND4_BLND_UNDERFLOW_INTERRUPT__VI            0x4371
#define mmBLND4_BLND_UPDATE__VI                         0x4370
#define mmBLND4_BLND_V_UPDATE_LOCK__VI                  0x4373
#define mmBLND4_SM_CONTROL2__VI                         0x436E
#define mmBLND5_BLND_CONTROL__VI                        0x456D
#define mmBLND5_BLND_CONTROL2__VI                       0x456F
#define mmBLND5_BLND_DEBUG__VI                          0x4574
#define mmBLND5_BLND_REG_UPDATE_STATUS__VI              0x4577
#define mmBLND5_BLND_TEST_DEBUG_DATA__VI                0x4576
#define mmBLND5_BLND_TEST_DEBUG_INDEX__VI               0x4575
#define mmBLND5_BLND_UNDERFLOW_INTERRUPT__VI            0x4571
#define mmBLND5_BLND_UPDATE__VI                         0x4570
#define mmBLND5_BLND_V_UPDATE_LOCK__VI                  0x4573
#define mmBLND5_SM_CONTROL2__VI                         0x456E
#define mmBLND6_BLND_CONTROL__VI                        0x476D
#define mmBLND6_BLND_CONTROL2__VI                       0x476F
#define mmBLND6_BLND_DEBUG__VI                          0x4774
#define mmBLND6_BLND_REG_UPDATE_STATUS__VI              0x4777
#define mmBLND6_BLND_TEST_DEBUG_DATA__VI                0x4776
#define mmBLND6_BLND_TEST_DEBUG_INDEX__VI               0x4775
#define mmBLND6_BLND_UNDERFLOW_INTERRUPT__VI            0x4771
#define mmBLND6_BLND_UPDATE__VI                         0x4770
#define mmBLND6_BLND_V_UPDATE_LOCK__VI                  0x4773
#define mmBLND6_SM_CONTROL2__VI                         0x476E
#define mmBLND_CONTROL__VI                              0x1B6D
#define mmBLND_CONTROL2__VI                             0x1B6F
#define mmBLND_DEBUG__VI                                0x1B74
#define mmBLND_REG_UPDATE_STATUS__VI                    0x1B77
#define mmBLND_TEST_DEBUG_DATA__VI                      0x1B76
#define mmBLND_TEST_DEBUG_INDEX__VI                     0x1B75
#define mmBLND_UNDERFLOW_INTERRUPT__VI                  0x1B71
#define mmBLND_UPDATE__VI                               0x1B70
#define mmBLND_V_UPDATE_LOCK__VI                        0x1B73
#define mmBL_PWM_CNTL__VI                               0x4820
#define mmBL_PWM_CNTL2__VI                              0x4821
#define mmBL_PWM_GRP1_REG_LOCK__VI                      0x4823
#define mmBL_PWM_PERIOD_CNTL__VI                        0x4822
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL__VI              0x48BA
#define mmBPHYC_DAC_MACRO_CNTL__VI                      0x48B9
#define mmBPHYC_PLL0_DISPPLL_BG_CNTL__VI                0x171E
#define mmBPHYC_PLL0_PLL_ANALOG__VI                     0x1708
#define mmBPHYC_PLL0_PLL_ANALOG_CNTL__VI                0x1711
#define mmBPHYC_PLL0_PLL_CNTL__VI                       0x1707
#define mmBPHYC_PLL0_PLL_DEBUG_CNTL__VI                 0x170B
#define mmBPHYC_PLL0_PLL_DS_CNTL__VI                    0x1705
#define mmBPHYC_PLL0_PLL_FB_DIV__VI                     0x1701
#define mmBPHYC_PLL0_PLL_IDCLK_CNTL__VI                 0x1706
#define mmBPHYC_PLL0_PLL_POST_DIV__VI                   0x1702
#define mmBPHYC_PLL0_PLL_REF_DIV__VI                    0x1700
#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC__VI           0x1703
#define mmBPHYC_PLL0_PLL_SS_CNTL__VI                    0x1704
#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL__VI         0x170A
#define mmBPHYC_PLL0_PLL_UPDATE_CNTL__VI                0x170D
#define mmBPHYC_PLL0_PLL_UPDATE_LOCK__VI                0x170C
#define mmBPHYC_PLL0_PLL_VREG_CNTL__VI                  0x1709
#define mmBPHYC_PLL0_PLL_XOR_LOCK__VI                   0x1710
#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL__VI            0x1721
#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG__VI          0x171F
#define mmBPHYC_PLL0_PPLL_SPARE0__VI                    0x1722
#define mmBPHYC_PLL0_PPLL_SPARE1__VI                    0x1723
#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG__VI              0x1720
#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG__VI              0x171B
#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV__VI              0x1715
#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV__VI            0x1718
#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV__VI             0x1712
#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG__VI              0x171C
#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV__VI              0x1716
#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV__VI            0x1719
#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV__VI             0x1713
#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG__VI              0x171D
#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV__VI              0x1717
#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV__VI            0x171A
#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV__VI             0x1714
#define mmBPHYC_PLL1_DISPPLL_BG_CNTL__VI                0x1748
#define mmBPHYC_PLL1_PLL_ANALOG__VI                     0x1732
#define mmBPHYC_PLL1_PLL_ANALOG_CNTL__VI                0x173B
#define mmBPHYC_PLL1_PLL_CNTL__VI                       0x1731
#define mmBPHYC_PLL1_PLL_DEBUG_CNTL__VI                 0x1735
#define mmBPHYC_PLL1_PLL_DS_CNTL__VI                    0x172F
#define mmBPHYC_PLL1_PLL_FB_DIV__VI                     0x172B
#define mmBPHYC_PLL1_PLL_IDCLK_CNTL__VI                 0x1730
#define mmBPHYC_PLL1_PLL_POST_DIV__VI                   0x172C
#define mmBPHYC_PLL1_PLL_REF_DIV__VI                    0x172A
#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC__VI           0x172D
#define mmBPHYC_PLL1_PLL_SS_CNTL__VI                    0x172E
#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL__VI         0x1734
#define mmBPHYC_PLL1_PLL_UPDATE_CNTL__VI                0x1737
#define mmBPHYC_PLL1_PLL_UPDATE_LOCK__VI                0x1736
#define mmBPHYC_PLL1_PLL_VREG_CNTL__VI                  0x1733
#define mmBPHYC_PLL1_PLL_XOR_LOCK__VI                   0x173A
#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL__VI            0x174B
#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG__VI          0x1749
#define mmBPHYC_PLL1_PPLL_SPARE0__VI                    0x174C
#define mmBPHYC_PLL1_PPLL_SPARE1__VI                    0x174D
#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG__VI              0x174A
#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG__VI              0x1745
#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV__VI              0x173F
#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV__VI            0x1742
#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV__VI             0x173C
#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG__VI              0x1746
#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV__VI              0x1740
#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV__VI            0x1743
#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV__VI             0x173D
#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG__VI              0x1747
#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV__VI              0x1741
#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV__VI            0x1744
#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV__VI             0x173E
#define mmBPHYC_PLL2_DISPPLL_BG_CNTL__VI                0x1772
#define mmBPHYC_PLL2_PLL_ANALOG__VI                     0x175C
#define mmBPHYC_PLL2_PLL_ANALOG_CNTL__VI                0x1765
#define mmBPHYC_PLL2_PLL_CNTL__VI                       0x175B
#define mmBPHYC_PLL2_PLL_DEBUG_CNTL__VI                 0x175F
#define mmBPHYC_PLL2_PLL_DS_CNTL__VI                    0x1759
#define mmBPHYC_PLL2_PLL_FB_DIV__VI                     0x1755
#define mmBPHYC_PLL2_PLL_IDCLK_CNTL__VI                 0x175A
#define mmBPHYC_PLL2_PLL_POST_DIV__VI                   0x1756
#define mmBPHYC_PLL2_PLL_REF_DIV__VI                    0x1754
#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC__VI           0x1757
#define mmBPHYC_PLL2_PLL_SS_CNTL__VI                    0x1758
#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL__VI         0x175E
#define mmBPHYC_PLL2_PLL_UPDATE_CNTL__VI                0x1761
#define mmBPHYC_PLL2_PLL_UPDATE_LOCK__VI                0x1760
#define mmBPHYC_PLL2_PLL_VREG_CNTL__VI                  0x175D
#define mmBPHYC_PLL2_PLL_XOR_LOCK__VI                   0x1764
#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL__VI            0x1775
#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG__VI          0x1773
#define mmBPHYC_PLL2_PPLL_SPARE0__VI                    0x1776
#define mmBPHYC_PLL2_PPLL_SPARE1__VI                    0x1777
#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG__VI              0x1774
#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG__VI              0x176F
#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV__VI              0x1769
#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV__VI            0x176C
#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV__VI             0x1766
#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG__VI              0x1770
#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV__VI              0x176A
#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV__VI            0x176D
#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV__VI             0x1767
#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG__VI              0x1771
#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV__VI              0x176B
#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV__VI            0x176E
#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV__VI             0x1768
#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL__VI        0x48CC
#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION__VI 0x48CA
#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG__VI                0x48D6
#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1__VI         0x48C6
#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2__VI         0x48C7
#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV__VI            0x48C5
#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL__VI          0x48C9
#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE__VI     0x48C8
#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL__VI        0x48C4
#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT__VI      0x48CB
#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2__VI     0x48CD
#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL__VI          0x48D4
#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED__VI             0x48D5
#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1__VI          0x48C0
#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2__VI          0x48C1
#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3__VI          0x48C2
#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4__VI          0x48C3
#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL__VI        0x48EC
#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION__VI 0x48EA
#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG__VI                0x48F6
#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1__VI         0x48E6
#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2__VI         0x48E7
#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV__VI            0x48E5
#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL__VI          0x48E9
#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE__VI     0x48E8
#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL__VI        0x48E4
#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT__VI      0x48EB
#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2__VI     0x48ED
#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL__VI          0x48F4
#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED__VI             0x48F5
#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1__VI          0x48E0
#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2__VI          0x48E1
#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3__VI          0x48E2
#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4__VI          0x48E3
#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL__VI        0x490C
#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION__VI 0x490A
#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG__VI                0x4916
#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1__VI         0x4906
#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2__VI         0x4907
#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV__VI            0x4905
#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL__VI          0x4909
#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE__VI     0x4908
#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL__VI        0x4904
#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT__VI      0x490B
#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2__VI     0x490D
#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL__VI          0x4914
#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED__VI             0x4915
#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1__VI          0x4900
#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2__VI          0x4901
#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3__VI          0x4902
#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4__VI          0x4903
#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL__VI        0x492C
#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION__VI 0x492A
#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG__VI                0x4936
#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1__VI         0x4926
#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2__VI         0x4927
#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV__VI            0x4925
#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL__VI          0x4929
#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE__VI     0x4928
#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL__VI        0x4924
#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT__VI      0x492B
#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2__VI     0x492D
#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL__VI          0x4934
#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED__VI             0x4935
#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1__VI          0x4920
#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2__VI          0x4921
#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3__VI          0x4922
#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4__VI          0x4923
#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL__VI        0x494C
#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION__VI 0x494A
#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG__VI                0x4956
#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1__VI         0x4946
#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2__VI         0x4947
#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV__VI            0x4945
#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL__VI          0x4949
#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE__VI     0x4948
#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL__VI        0x4944
#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT__VI      0x494B
#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2__VI     0x494D
#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL__VI          0x4954
#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED__VI             0x4955
#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1__VI          0x4940
#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2__VI          0x4941
#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3__VI          0x4942
#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4__VI          0x4943
#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL__VI        0x496C
#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION__VI 0x496A
#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG__VI                0x4976
#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1__VI         0x4966
#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2__VI         0x4967
#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV__VI            0x4965
#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL__VI          0x4969
#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE__VI     0x4968
#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL__VI        0x4964
#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT__VI      0x496B
#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2__VI     0x496D
#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL__VI          0x4974
#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED__VI             0x4975
#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1__VI          0x4960
#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2__VI          0x4961
#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3__VI          0x4962
#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4__VI          0x4963
#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL__VI        0x498C
#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION__VI 0x498A
#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG__VI                0x4996
#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1__VI         0x4986
#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2__VI         0x4987
#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV__VI            0x4985
#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL__VI          0x4989
#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE__VI     0x4988
#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL__VI        0x4984
#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT__VI      0x498B
#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2__VI     0x498D
#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL__VI          0x4994
#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED__VI             0x4995
#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1__VI          0x4980
#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2__VI          0x4981
#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3__VI          0x4982
#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4__VI          0x4983
#define mmBX_RESET_CNTL__VI                             0x1518
#define mmCB_COLOR0_DCC_BASE__VI                        0xA325
#define mmCB_COLOR0_DCC_CONTROL__VI                     0xA31E
#define mmCB_COLOR1_DCC_BASE__VI                        0xA334
#define mmCB_COLOR1_DCC_CONTROL__VI                     0xA32D
#define mmCB_COLOR2_DCC_BASE__VI                        0xA343
#define mmCB_COLOR2_DCC_CONTROL__VI                     0xA33C
#define mmCB_COLOR3_DCC_BASE__VI                        0xA352
#define mmCB_COLOR3_DCC_CONTROL__VI                     0xA34B
#define mmCB_COLOR4_DCC_BASE__VI                        0xA361
#define mmCB_COLOR4_DCC_CONTROL__VI                     0xA35A
#define mmCB_COLOR5_DCC_BASE__VI                        0xA370
#define mmCB_COLOR5_DCC_CONTROL__VI                     0xA369
#define mmCB_COLOR6_DCC_BASE__VI                        0xA37F
#define mmCB_COLOR6_DCC_CONTROL__VI                     0xA378
#define mmCB_COLOR7_DCC_BASE__VI                        0xA38E
#define mmCB_COLOR7_DCC_CONTROL__VI                     0xA387
#define mmCB_DCC_CONFIG__VI                             0x2687
#define mmCB_DCC_CONTROL__VI                            0xA109
#define mmCB_DEBUG_BUS_19__VI                           0x26AB
#define mmCB_DEBUG_BUS_20__VI                           0x26AC
#define mmCB_DEBUG_BUS_21__VI                           0x26AD
#define mmCB_DEBUG_BUS_22__VI                           0x26AE
#define mmCC_DC_PIPE_DIS__VI                            0x0312
#define mmCC_GC_SHADER_RATE_CONFIG__VI                  0x2312
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__VI   0x1835
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY__VI         0x1834
#define mmCG_FPS_CNT__VI                                0x01B6
#define mmCLKREQB_PERF_COUNTER__VI                      0x1522
#define mmCNV_CSC_C11_C12__VI                           0x5E20
#define mmCNV_CSC_C13_C14__VI                           0x5E21
#define mmCNV_CSC_C21_C22__VI                           0x5E22
#define mmCNV_CSC_C23_C24__VI                           0x5E23
#define mmCNV_CSC_C31_C32__VI                           0x5E24
#define mmCNV_CSC_C33_C34__VI                           0x5E25
#define mmCNV_CSC_CLAMP_B__VI                           0x5E2B
#define mmCNV_CSC_CLAMP_G__VI                           0x5E2A
#define mmCNV_CSC_CLAMP_R__VI                           0x5E29
#define mmCNV_CSC_CONTROL__VI                           0x5E1F
#define mmCNV_CSC_ROUND_OFFSET_B__VI                    0x5E28
#define mmCNV_CSC_ROUND_OFFSET_G__VI                    0x5E27
#define mmCNV_CSC_ROUND_OFFSET_R__VI                    0x5E26
#define mmCNV_INPUT_SELECT__VI                          0x5E33
#define mmCNV_MODE__VI                                  0x5E1A
#define mmCNV_SOURCE_SIZE__VI                           0x5E1E
#define mmCNV_TEST_CNTL__VI                             0x5E2C
#define mmCNV_TEST_CRC_BLUE__VI                         0x5E2F
#define mmCNV_TEST_CRC_GREEN__VI                        0x5E2E
#define mmCNV_TEST_CRC_RED__VI                          0x5E2D
#define mmCNV_TEST_DEBUG_DATA__VI                       0x5E35
#define mmCNV_TEST_DEBUG_INDEX__VI                      0x5E34
#define mmCNV_UPDATE__VI                                0x5E1D
#define mmCNV_WINDOW_SIZE__VI                           0x5E1C
#define mmCNV_WINDOW_START__VI                          0x5E1B
#define mmCOL_MAN_DEBUG_CONTROL__VI                     0x46E6
#define mmCOL_MAN_FP_CONVERTED_FIELD__VI                0x46C7
#define mmCOL_MAN_INPUT_CSC_CONTROL__VI                 0x46A5
#define mmCOL_MAN_OUTPUT_CSC_CONTROL__VI                0x46B6
#define mmCOL_MAN_TEST_DEBUG_DATA__VI                   0x46E5
#define mmCOL_MAN_TEST_DEBUG_INDEX__VI                  0x46E4
#define mmCOL_MAN_UPDATE__VI                            0x46A4
#define mmCOMM_MATRIXA_TRANS_C11_C12__VI                0x1A43
#define mmCOMM_MATRIXA_TRANS_C13_C14__VI                0x1A44
#define mmCOMM_MATRIXA_TRANS_C21_C22__VI                0x1A45
#define mmCOMM_MATRIXA_TRANS_C23_C24__VI                0x1A46
#define mmCOMM_MATRIXA_TRANS_C31_C32__VI                0x1A47
#define mmCOMM_MATRIXA_TRANS_C33_C34__VI                0x1A48
#define mmCOMM_MATRIXB_TRANS_C11_C12__VI                0x1A49
#define mmCOMM_MATRIXB_TRANS_C13_C14__VI                0x1A4A
#define mmCOMM_MATRIXB_TRANS_C21_C22__VI                0x1A4B
#define mmCOMM_MATRIXB_TRANS_C23_C24__VI                0x1A4C
#define mmCOMM_MATRIXB_TRANS_C31_C32__VI                0x1A4D
#define mmCOMM_MATRIXB_TRANS_C33_C34__VI                0x1A4E
#define mmCOMPUTE_DISPATCH_ID__VI                       0x2E20
#define mmCOMPUTE_NOWHERE__VI                           0x2E7F
#define mmCOMPUTE_RELAUNCH__VI                          0x2E22
#define mmCOMPUTE_THREADGROUP_ID__VI                    0x2E21
#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI__VI              0x2E24
#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO__VI              0x2E23
#define mmCOMPUTE_WAVE_RESTORE_CONTROL__VI              0x2E25
#define mmCONFIG_RESERVED__VI                           0x1502
#define mmCPLL_MACRO_CNTL_RESERVED0__VI                 0x5FD0
#define mmCPLL_MACRO_CNTL_RESERVED1__VI                 0x5FD1
#define mmCPLL_MACRO_CNTL_RESERVED10__VI                0x5FDA
#define mmCPLL_MACRO_CNTL_RESERVED11__VI                0x5FDB
#define mmCPLL_MACRO_CNTL_RESERVED2__VI                 0x5FD2
#define mmCPLL_MACRO_CNTL_RESERVED3__VI                 0x5FD3
#define mmCPLL_MACRO_CNTL_RESERVED4__VI                 0x5FD4
#define mmCPLL_MACRO_CNTL_RESERVED5__VI                 0x5FD5
#define mmCPLL_MACRO_CNTL_RESERVED6__VI                 0x5FD6
#define mmCPLL_MACRO_CNTL_RESERVED7__VI                 0x5FD7
#define mmCPLL_MACRO_CNTL_RESERVED8__VI                 0x5FD8
#define mmCPLL_MACRO_CNTL_RESERVED9__VI                 0x5FD9
#define mmCPM_CONTROL__VI                               0x14B8
#define mmCP_CE_COMPLETION_STATUS__VI                   0xC0ED
#define mmCP_CE_METADATA_BASE_ADDR__VI                  0xC0F2
#define mmCP_CE_METADATA_BASE_ADDR_HI__VI               0xC0F3
#define mmCP_CE_RB_OFFSET__VI                           0xC09B
#define mmCP_CE_UCODE_ADDR__SI__CI                      0x305A
#define mmCP_CE_UCODE_ADDR__VI                          0xF818
#define mmCP_CE_UCODE_DATA__SI__CI                      0x305B
#define mmCP_CE_UCODE_DATA__VI                          0xF819
#define mmCP_CONFIG__VI                                 0x0F96
#define mmCP_CPC_IC_BASE_CNTL__VI                       0x30BB
#define mmCP_CPC_IC_BASE_HI__VI                         0x30BA
#define mmCP_CPC_IC_BASE_LO__VI                         0x30B9
#define mmCP_CPC_IC_OP_CNTL__VI                         0x30BC
#define mmCP_CPC_MGCG_SYNC_CNTL__VI                     0x3036
#define mmCP_DFY_CMD__VI                                0x3034
#define mmCP_DISPATCH_INDR_ADDR__VI                     0xC0F6
#define mmCP_DISPATCH_INDR_ADDR_HI__VI                  0xC0F7
#define mmCP_DRAW_INDX_INDR_ADDR__VI                    0xC0F4
#define mmCP_DRAW_INDX_INDR_ADDR_HI__VI                 0xC0F5
#define mmCP_DRAW_OBJECT__VI                            0xD810
#define mmCP_DRAW_OBJECT_COUNTER__VI                    0xD811
#define mmCP_DRAW_WINDOW_CNTL__VI                       0xD815
#define mmCP_DRAW_WINDOW_HI__VI                         0xD813
#define mmCP_DRAW_WINDOW_LO__VI                         0xD814
#define mmCP_DRAW_WINDOW_MASK_HI__VI                    0xD812
#define mmCP_EOP_DONE_CNTX_ID__VI                       0xC0D7
#define mmCP_GDS_BKUP_ADDR__VI                          0xC0FB
#define mmCP_GDS_BKUP_ADDR_HI__VI                       0xC0FC
#define mmCP_HPD_STATUS0__VI                            0x3241
#define mmCP_HQD_CNTL_STACK_OFFSET__VI                  0x3273
#define mmCP_HQD_CNTL_STACK_SIZE__VI                    0x3274
#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI__VI              0x3271
#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO__VI              0x3270
#define mmCP_HQD_CTX_SAVE_CONTROL__VI                   0x3272
#define mmCP_HQD_CTX_SAVE_SIZE__VI                      0x3276
#define mmCP_HQD_EOP_BASE_ADDR__VI                      0x326A
#define mmCP_HQD_EOP_BASE_ADDR_HI__VI                   0x326B
#define mmCP_HQD_EOP_CONTROL__VI                        0x326C
#define mmCP_HQD_EOP_DONES__VI                          0x327A
#define mmCP_HQD_EOP_EVENTS__VI                         0x326F
#define mmCP_HQD_EOP_RPTR__VI                           0x326D
#define mmCP_HQD_EOP_WPTR__VI                           0x326E
#define mmCP_HQD_EOP_WPTR_MEM__VI                       0x3279
#define mmCP_HQD_ERROR__VI                              0x3278
#define mmCP_HQD_GDS_RESOURCE_STATE__VI                 0x3277
#define mmCP_HQD_HQ_CONTROL0__VI                        0x3266
#define mmCP_HQD_HQ_CONTROL1__VI                        0x3269
#define mmCP_HQD_HQ_STATUS0__VI                         0x3265
#define mmCP_HQD_HQ_STATUS1__VI                         0x3268
#define mmCP_HQD_OFFLOAD__VI                            0x325E
#define mmCP_HQD_WG_STATE_OFFSET__VI                    0x3275
#define mmCP_INDEX_BASE_ADDR__VI                        0xC0F8
#define mmCP_INDEX_BASE_ADDR_HI__VI                     0xC0F9
#define mmCP_INDEX_TYPE__VI                             0xC0FA
#define mmCP_MEC1_F32_INT_DIS__VI                       0x30BD
#define mmCP_MEC2_F32_INT_DIS__VI                       0x30BE
#define mmCP_MEC_DOORBELL_RANGE_LOWER__VI               0x305C
#define mmCP_MEC_DOORBELL_RANGE_UPPER__VI               0x305D
#define mmCP_MEC_ME1_UCODE_ADDR__VI                     0xF81A
#define mmCP_MEC_ME1_UCODE_DATA__VI                     0xF81B
#define mmCP_MEC_ME2_UCODE_ADDR__VI                     0xF81C
#define mmCP_MEC_ME2_UCODE_DATA__VI                     0xF81D
#define mmCP_ME_RAM_DATA__SI__CI                        0x3058
#define mmCP_ME_RAM_DATA__VI                            0xF817
#define mmCP_ME_RAM_RADDR__SI__CI                       0x3056
#define mmCP_ME_RAM_RADDR__VI                           0xF816
#define mmCP_ME_RAM_WADDR__SI__CI                       0x3057
#define mmCP_ME_RAM_WADDR__VI                           0xF816
#define mmCP_PFP_COMPLETION_STATUS__VI                  0xC0EC
#define mmCP_PFP_METADATA_BASE_ADDR__VI                 0xC0F0
#define mmCP_PFP_METADATA_BASE_ADDR_HI__VI              0xC0F1
#define mmCP_PFP_UCODE_ADDR__SI__CI                     0x3054
#define mmCP_PFP_UCODE_ADDR__VI                         0xF814
#define mmCP_PFP_UCODE_DATA__SI__CI                     0x3055
#define mmCP_PFP_UCODE_DATA__VI                         0xF815
#define mmCP_PIPE_STATS_CONTROL__VI                     0xC03D
#define mmCP_PQ_STATUS__VI                              0x30B8
#define mmCP_PRED_NOT_VISIBLE__VI                       0xC0EE
#define mmCP_RB_DOORBELL_CONTROL__VI                    0x3059
#define mmCP_RB_DOORBELL_RANGE_LOWER__VI                0x305A
#define mmCP_RB_DOORBELL_RANGE_UPPER__VI                0x305B
#define mmCP_SAMPLE_STATUS__VI                          0xC0FD
#define mmCP_STREAM_OUT_CONTROL__VI                     0xC03E
#define mmCP_VIRT_STATUS__VI                            0x3038
#define mmCP_VMID_STATUS__VI                            0x30BF
#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL__VI           0x1B78
#define mmCRTC0_CRTC_AVSYNC_COUNTER__VI                 0x1B9B
#define mmCRTC0_CRTC_BLACK_COLOR__VI                    0x1BCC
#define mmCRTC0_CRTC_BLACK_COLOR_EXT__VI                0x1BCD
#define mmCRTC0_CRTC_BLANK_DATA_COLOR__VI               0x1BCA
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT__VI           0x1BCB
#define mmCRTC0_CRTC_CRC0_DATA_B__VI                    0x1BDA
#define mmCRTC0_CRTC_CRC0_DATA_RG__VI                   0x1BD9
#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x1BD5
#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x1BD6
#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x1BD7
#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x1BD8
#define mmCRTC0_CRTC_CRC1_DATA_B__VI                    0x1BE0
#define mmCRTC0_CRTC_CRC1_DATA_RG__VI                   0x1BDF
#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x1BDB
#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x1BDC
#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x1BDD
#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x1BDE
#define mmCRTC0_CRTC_CRC_CNTL__VI                       0x1BD4
#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL__VI             0x1B7C
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x1BE1
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x1BE5
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x1BE4
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x1BE6
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x1BE3
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x1BE2
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL__VI       0x1BA0
#define mmCRTC0_CRTC_GSL_CONTROL__VI                    0x1B7B
#define mmCRTC0_CRTC_GSL_VSYNC_GAP__VI                  0x1B79
#define mmCRTC0_CRTC_GSL_WINDOW__VI                     0x1B7A
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM__VI              0x1B7D
#define mmCRTC0_CRTC_OVERSCAN_COLOR__VI                 0x1BC8
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT__VI             0x1BC9
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0__VI           0x1BA1
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1__VI           0x1BA2
#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL__VI          0x1BE7
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x1B9A
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x1BCF
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x1BCE
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x1BD1
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x1BD0
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x1BD3
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x1BD2
#define mmCRTC0_DCFE_DBG_SEL__VI                        0x1B7E
#define mmCRTC0_DCFE_MEM_PWR_CTRL__VI                   0x1B7F
#define mmCRTC0_DCFE_MEM_PWR_CTRL2__VI                  0x1BB8
#define mmCRTC0_DCFE_MEM_PWR_STATUS__VI                 0x1BB9
#define mmCRTC0_PIXEL_RATE_CNTL__VI                     0x0140
#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL__VI           0x1D78
#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__VI           0x1DC3
#define mmCRTC1_CRTC_AVSYNC_COUNTER__VI                 0x1D9B
#define mmCRTC1_CRTC_BLACK_COLOR__VI                    0x1DCC
#define mmCRTC1_CRTC_BLACK_COLOR_EXT__VI                0x1DCD
#define mmCRTC1_CRTC_BLANK_CONTROL__SI__CI              0x1E9D
#define mmCRTC1_CRTC_BLANK_CONTROL__VI                  0x1D9D
#define mmCRTC1_CRTC_BLANK_DATA_COLOR__VI               0x1DCA
#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT__VI           0x1DCB
#define mmCRTC1_CRTC_CONTROL__VI                        0x1D9C
#define mmCRTC1_CRTC_COUNT_CONTROL__VI                  0x1DA9
#define mmCRTC1_CRTC_COUNT_RESET__VI                    0x1DAA
#define mmCRTC1_CRTC_CRC0_DATA_B__VI                    0x1DDA
#define mmCRTC1_CRTC_CRC0_DATA_RG__VI                   0x1DD9
#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x1DD5
#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x1DD6
#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x1DD7
#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x1DD8
#define mmCRTC1_CRTC_CRC1_DATA_B__VI                    0x1DE0
#define mmCRTC1_CRTC_CRC1_DATA_RG__VI                   0x1DDF
#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x1DDB
#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x1DDC
#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x1DDD
#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x1DDE
#define mmCRTC1_CRTC_CRC_CNTL__VI                       0x1DD4
#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL__VI             0x1D7C
#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL__VI          0x1DB6
#define mmCRTC1_CRTC_DTMTEST_CNTL__VI                   0x1D92
#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION__VI        0x1D93
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x1DE1
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x1DE5
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x1DE4
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x1DE6
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x1DE3
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x1DE2
#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL__VI       0x1DA0
#define mmCRTC1_CRTC_FLOW_CONTROL__VI                   0x1D99
#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL__VI           0x1D98
#define mmCRTC1_CRTC_GSL_CONTROL__VI                    0x1D7B
#define mmCRTC1_CRTC_GSL_VSYNC_GAP__VI                  0x1D79
#define mmCRTC1_CRTC_GSL_WINDOW__VI                     0x1D7A
#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM__VI              0x1D7D
#define mmCRTC1_CRTC_H_BLANK_START_END__VI              0x1D81
#define mmCRTC1_CRTC_H_SYNC_A__VI                       0x1D82
#define mmCRTC1_CRTC_H_SYNC_A_CNTL__VI                  0x1D83
#define mmCRTC1_CRTC_H_SYNC_B__VI                       0x1D84
#define mmCRTC1_CRTC_H_SYNC_B_CNTL__VI                  0x1D85
#define mmCRTC1_CRTC_H_TOTAL__VI                        0x1D80
#define mmCRTC1_CRTC_INTERLACE_CONTROL__VI              0x1D9E
#define mmCRTC1_CRTC_INTERLACE_STATUS__VI               0x1D9F
#define mmCRTC1_CRTC_INTERRUPT_CONTROL__VI              0x1DB4
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI   0x1DAB
#define mmCRTC1_CRTC_MASTER_EN__VI                      0x1DC2
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT__VI         0x1DBF
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI   0x1DC0
#define mmCRTC1_CRTC_MVP_STATUS__VI                     0x1DC1
#define mmCRTC1_CRTC_NOM_VERT_POSITION__VI              0x1DA5
#define mmCRTC1_CRTC_OVERSCAN_COLOR__VI                 0x1DC8
#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT__VI             0x1DC9
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0__VI           0x1DA1
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1__VI           0x1DA2
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL__VI               0x1DB0
#define mmCRTC1_CRTC_SNAPSHOT_FRAME__VI                 0x1DB2
#define mmCRTC1_CRTC_SNAPSHOT_POSITION__VI              0x1DB1
#define mmCRTC1_CRTC_SNAPSHOT_STATUS__VI                0x1DAF
#define mmCRTC1_CRTC_START_LINE_CONTROL__VI             0x1DB3
#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL__VI          0x1DE7
#define mmCRTC1_CRTC_STATUS__SI__CI                     0x1EA3
#define mmCRTC1_CRTC_STATUS__VI                         0x1DA3
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT__VI             0x1DA6
#define mmCRTC1_CRTC_STATUS_HV_COUNT__VI                0x1DA8
#define mmCRTC1_CRTC_STATUS_POSITION__SI__CI            0x1EA4
#define mmCRTC1_CRTC_STATUS_POSITION__VI                0x1DA4
#define mmCRTC1_CRTC_STATUS_VF_COUNT__VI                0x1DA7
#define mmCRTC1_CRTC_STEREO_CONTROL__VI                 0x1DAE
#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x1D9A
#define mmCRTC1_CRTC_STEREO_STATUS__VI                  0x1DAD
#define mmCRTC1_CRTC_TEST_DEBUG_DATA__VI                0x1DC7
#define mmCRTC1_CRTC_TEST_DEBUG_INDEX__VI               0x1DC6
#define mmCRTC1_CRTC_TEST_PATTERN_COLOR__VI             0x1DBC
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL__VI           0x1DBA
#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS__VI        0x1DBB
#define mmCRTC1_CRTC_TRIGA_CNTL__VI                     0x1D94
#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG__VI              0x1D95
#define mmCRTC1_CRTC_TRIGB_CNTL__VI                     0x1D96
#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG__VI              0x1D97
#define mmCRTC1_CRTC_UPDATE_LOCK__VI                    0x1DB5
#define mmCRTC1_CRTC_VBI_END__VI                        0x1D86
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x1DCF
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x1DCE
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x1DD1
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x1DD0
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x1DD3
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x1DD2
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL__VI              0x1DAC
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI     0x1DB7
#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS__VI           0x1D8C
#define mmCRTC1_CRTC_V_BLANK_START_END__VI              0x1D8D
#define mmCRTC1_CRTC_V_SYNC_A__VI                       0x1D8E
#define mmCRTC1_CRTC_V_SYNC_A_CNTL__VI                  0x1D8F
#define mmCRTC1_CRTC_V_SYNC_B__VI                       0x1D90
#define mmCRTC1_CRTC_V_SYNC_B_CNTL__VI                  0x1D91
#define mmCRTC1_CRTC_V_TOTAL__VI                        0x1D87
#define mmCRTC1_CRTC_V_TOTAL_CONTROL__VI                0x1D8A
#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS__VI             0x1D8B
#define mmCRTC1_CRTC_V_TOTAL_MAX__VI                    0x1D89
#define mmCRTC1_CRTC_V_TOTAL_MIN__VI                    0x1D88
#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS__VI            0x1DC4
#define mmCRTC1_DCFE_DBG_SEL__VI                        0x1D7E
#define mmCRTC1_DCFE_MEM_PWR_CTRL__VI                   0x1D7F
#define mmCRTC1_DCFE_MEM_PWR_CTRL2__VI                  0x1DB8
#define mmCRTC1_DCFE_MEM_PWR_STATUS__VI                 0x1DB9
#define mmCRTC1_MASTER_UPDATE_LOCK__VI                  0x1DBD
#define mmCRTC1_MASTER_UPDATE_MODE__SI__CI              0x1EBE
#define mmCRTC1_MASTER_UPDATE_MODE__VI                  0x1DBE
#define mmCRTC1_PIXEL_RATE_CNTL__VI                     0x0144
#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL__VI           0x1F78
#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__VI           0x1FC3
#define mmCRTC2_CRTC_AVSYNC_COUNTER__VI                 0x1F9B
#define mmCRTC2_CRTC_BLACK_COLOR__VI                    0x1FCC
#define mmCRTC2_CRTC_BLACK_COLOR_EXT__VI                0x1FCD
#define mmCRTC2_CRTC_BLANK_CONTROL__SI__CI              0x419D
#define mmCRTC2_CRTC_BLANK_CONTROL__VI                  0x1F9D
#define mmCRTC2_CRTC_BLANK_DATA_COLOR__VI               0x1FCA
#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT__VI           0x1FCB
#define mmCRTC2_CRTC_CONTROL__VI                        0x1F9C
#define mmCRTC2_CRTC_COUNT_CONTROL__VI                  0x1FA9
#define mmCRTC2_CRTC_COUNT_RESET__VI                    0x1FAA
#define mmCRTC2_CRTC_CRC0_DATA_B__VI                    0x1FDA
#define mmCRTC2_CRTC_CRC0_DATA_RG__VI                   0x1FD9
#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x1FD5
#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x1FD6
#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x1FD7
#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x1FD8
#define mmCRTC2_CRTC_CRC1_DATA_B__VI                    0x1FE0
#define mmCRTC2_CRTC_CRC1_DATA_RG__VI                   0x1FDF
#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x1FDB
#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x1FDC
#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x1FDD
#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x1FDE
#define mmCRTC2_CRTC_CRC_CNTL__VI                       0x1FD4
#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL__VI             0x1F7C
#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL__VI          0x1FB6
#define mmCRTC2_CRTC_DTMTEST_CNTL__VI                   0x1F92
#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION__VI        0x1F93
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x1FE1
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x1FE5
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x1FE4
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x1FE6
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x1FE3
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x1FE2
#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL__VI       0x1FA0
#define mmCRTC2_CRTC_FLOW_CONTROL__VI                   0x1F99
#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL__VI           0x1F98
#define mmCRTC2_CRTC_GSL_CONTROL__VI                    0x1F7B
#define mmCRTC2_CRTC_GSL_VSYNC_GAP__VI                  0x1F79
#define mmCRTC2_CRTC_GSL_WINDOW__VI                     0x1F7A
#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM__VI              0x1F7D
#define mmCRTC2_CRTC_H_BLANK_START_END__VI              0x1F81
#define mmCRTC2_CRTC_H_SYNC_A__VI                       0x1F82
#define mmCRTC2_CRTC_H_SYNC_A_CNTL__VI                  0x1F83
#define mmCRTC2_CRTC_H_SYNC_B__VI                       0x1F84
#define mmCRTC2_CRTC_H_SYNC_B_CNTL__VI                  0x1F85
#define mmCRTC2_CRTC_H_TOTAL__VI                        0x1F80
#define mmCRTC2_CRTC_INTERLACE_CONTROL__VI              0x1F9E
#define mmCRTC2_CRTC_INTERLACE_STATUS__VI               0x1F9F
#define mmCRTC2_CRTC_INTERRUPT_CONTROL__VI              0x1FB4
#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI   0x1FAB
#define mmCRTC2_CRTC_MASTER_EN__VI                      0x1FC2
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT__VI         0x1FBF
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI   0x1FC0
#define mmCRTC2_CRTC_MVP_STATUS__VI                     0x1FC1
#define mmCRTC2_CRTC_NOM_VERT_POSITION__VI              0x1FA5
#define mmCRTC2_CRTC_OVERSCAN_COLOR__VI                 0x1FC8
#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT__VI             0x1FC9
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0__VI           0x1FA1
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1__VI           0x1FA2
#define mmCRTC2_CRTC_SNAPSHOT_CONTROL__VI               0x1FB0
#define mmCRTC2_CRTC_SNAPSHOT_FRAME__VI                 0x1FB2
#define mmCRTC2_CRTC_SNAPSHOT_POSITION__VI              0x1FB1
#define mmCRTC2_CRTC_SNAPSHOT_STATUS__VI                0x1FAF
#define mmCRTC2_CRTC_START_LINE_CONTROL__VI             0x1FB3
#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL__VI          0x1FE7
#define mmCRTC2_CRTC_STATUS__SI__CI                     0x41A3
#define mmCRTC2_CRTC_STATUS__VI                         0x1FA3
#define mmCRTC2_CRTC_STATUS_FRAME_COUNT__VI             0x1FA6
#define mmCRTC2_CRTC_STATUS_HV_COUNT__VI                0x1FA8
#define mmCRTC2_CRTC_STATUS_POSITION__SI__CI            0x41A4
#define mmCRTC2_CRTC_STATUS_POSITION__VI                0x1FA4
#define mmCRTC2_CRTC_STATUS_VF_COUNT__VI                0x1FA7
#define mmCRTC2_CRTC_STEREO_CONTROL__VI                 0x1FAE
#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x1F9A
#define mmCRTC2_CRTC_STEREO_STATUS__VI                  0x1FAD
#define mmCRTC2_CRTC_TEST_DEBUG_DATA__VI                0x1FC7
#define mmCRTC2_CRTC_TEST_DEBUG_INDEX__VI               0x1FC6
#define mmCRTC2_CRTC_TEST_PATTERN_COLOR__VI             0x1FBC
#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL__VI           0x1FBA
#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS__VI        0x1FBB
#define mmCRTC2_CRTC_TRIGA_CNTL__VI                     0x1F94
#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG__VI              0x1F95
#define mmCRTC2_CRTC_TRIGB_CNTL__VI                     0x1F96
#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG__VI              0x1F97
#define mmCRTC2_CRTC_UPDATE_LOCK__VI                    0x1FB5
#define mmCRTC2_CRTC_VBI_END__VI                        0x1F86
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x1FCF
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x1FCE
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x1FD1
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x1FD0
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x1FD3
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x1FD2
#define mmCRTC2_CRTC_VERT_SYNC_CONTROL__VI              0x1FAC
#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI     0x1FB7
#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS__VI           0x1F8C
#define mmCRTC2_CRTC_V_BLANK_START_END__VI              0x1F8D
#define mmCRTC2_CRTC_V_SYNC_A__VI                       0x1F8E
#define mmCRTC2_CRTC_V_SYNC_A_CNTL__VI                  0x1F8F
#define mmCRTC2_CRTC_V_SYNC_B__VI                       0x1F90
#define mmCRTC2_CRTC_V_SYNC_B_CNTL__VI                  0x1F91
#define mmCRTC2_CRTC_V_TOTAL__VI                        0x1F87
#define mmCRTC2_CRTC_V_TOTAL_CONTROL__VI                0x1F8A
#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS__VI             0x1F8B
#define mmCRTC2_CRTC_V_TOTAL_MAX__VI                    0x1F89
#define mmCRTC2_CRTC_V_TOTAL_MIN__VI                    0x1F88
#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS__VI            0x1FC4
#define mmCRTC2_DCFE_DBG_SEL__VI                        0x1F7E
#define mmCRTC2_DCFE_MEM_PWR_CTRL__VI                   0x1F7F
#define mmCRTC2_DCFE_MEM_PWR_CTRL2__VI                  0x1FB8
#define mmCRTC2_DCFE_MEM_PWR_STATUS__VI                 0x1FB9
#define mmCRTC2_MASTER_UPDATE_LOCK__VI                  0x1FBD
#define mmCRTC2_MASTER_UPDATE_MODE__SI__CI              0x41BE
#define mmCRTC2_MASTER_UPDATE_MODE__VI                  0x1FBE
#define mmCRTC2_PIXEL_RATE_CNTL__VI                     0x0148
#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL__VI           0x4178
#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__VI           0x41C3
#define mmCRTC3_CRTC_AVSYNC_COUNTER__VI                 0x419B
#define mmCRTC3_CRTC_BLACK_COLOR__VI                    0x41CC
#define mmCRTC3_CRTC_BLACK_COLOR_EXT__VI                0x41CD
#define mmCRTC3_CRTC_BLANK_CONTROL__SI__CI              0x449D
#define mmCRTC3_CRTC_BLANK_CONTROL__VI                  0x419D
#define mmCRTC3_CRTC_BLANK_DATA_COLOR__VI               0x41CA
#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT__VI           0x41CB
#define mmCRTC3_CRTC_CONTROL__VI                        0x419C
#define mmCRTC3_CRTC_COUNT_CONTROL__VI                  0x41A9
#define mmCRTC3_CRTC_COUNT_RESET__VI                    0x41AA
#define mmCRTC3_CRTC_CRC0_DATA_B__VI                    0x41DA
#define mmCRTC3_CRTC_CRC0_DATA_RG__VI                   0x41D9
#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x41D5
#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x41D6
#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x41D7
#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x41D8
#define mmCRTC3_CRTC_CRC1_DATA_B__VI                    0x41E0
#define mmCRTC3_CRTC_CRC1_DATA_RG__VI                   0x41DF
#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x41DB
#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x41DC
#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x41DD
#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x41DE
#define mmCRTC3_CRTC_CRC_CNTL__VI                       0x41D4
#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL__VI             0x417C
#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL__VI          0x41B6
#define mmCRTC3_CRTC_DTMTEST_CNTL__VI                   0x4192
#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION__VI        0x4193
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x41E1
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x41E5
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x41E4
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x41E6
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x41E3
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x41E2
#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL__VI       0x41A0
#define mmCRTC3_CRTC_FLOW_CONTROL__VI                   0x4199
#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL__VI           0x4198
#define mmCRTC3_CRTC_GSL_CONTROL__VI                    0x417B
#define mmCRTC3_CRTC_GSL_VSYNC_GAP__VI                  0x4179
#define mmCRTC3_CRTC_GSL_WINDOW__VI                     0x417A
#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM__VI              0x417D
#define mmCRTC3_CRTC_H_BLANK_START_END__VI              0x4181
#define mmCRTC3_CRTC_H_SYNC_A__VI                       0x4182
#define mmCRTC3_CRTC_H_SYNC_A_CNTL__VI                  0x4183
#define mmCRTC3_CRTC_H_SYNC_B__VI                       0x4184
#define mmCRTC3_CRTC_H_SYNC_B_CNTL__VI                  0x4185
#define mmCRTC3_CRTC_H_TOTAL__VI                        0x4180
#define mmCRTC3_CRTC_INTERLACE_CONTROL__VI              0x419E
#define mmCRTC3_CRTC_INTERLACE_STATUS__VI               0x419F
#define mmCRTC3_CRTC_INTERRUPT_CONTROL__VI              0x41B4
#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI   0x41AB
#define mmCRTC3_CRTC_MASTER_EN__VI                      0x41C2
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT__VI         0x41BF
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI   0x41C0
#define mmCRTC3_CRTC_MVP_STATUS__VI                     0x41C1
#define mmCRTC3_CRTC_NOM_VERT_POSITION__VI              0x41A5
#define mmCRTC3_CRTC_OVERSCAN_COLOR__VI                 0x41C8
#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT__VI             0x41C9
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0__VI           0x41A1
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1__VI           0x41A2
#define mmCRTC3_CRTC_SNAPSHOT_CONTROL__VI               0x41B0
#define mmCRTC3_CRTC_SNAPSHOT_FRAME__VI                 0x41B2
#define mmCRTC3_CRTC_SNAPSHOT_POSITION__VI              0x41B1
#define mmCRTC3_CRTC_SNAPSHOT_STATUS__VI                0x41AF
#define mmCRTC3_CRTC_START_LINE_CONTROL__VI             0x41B3
#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL__VI          0x41E7
#define mmCRTC3_CRTC_STATUS__SI__CI                     0x44A3
#define mmCRTC3_CRTC_STATUS__VI                         0x41A3
#define mmCRTC3_CRTC_STATUS_FRAME_COUNT__VI             0x41A6
#define mmCRTC3_CRTC_STATUS_HV_COUNT__VI                0x41A8
#define mmCRTC3_CRTC_STATUS_POSITION__SI__CI            0x44A4
#define mmCRTC3_CRTC_STATUS_POSITION__VI                0x41A4
#define mmCRTC3_CRTC_STATUS_VF_COUNT__VI                0x41A7
#define mmCRTC3_CRTC_STEREO_CONTROL__VI                 0x41AE
#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x419A
#define mmCRTC3_CRTC_STEREO_STATUS__VI                  0x41AD
#define mmCRTC3_CRTC_TEST_DEBUG_DATA__VI                0x41C7
#define mmCRTC3_CRTC_TEST_DEBUG_INDEX__VI               0x41C6
#define mmCRTC3_CRTC_TEST_PATTERN_COLOR__VI             0x41BC
#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL__VI           0x41BA
#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS__VI        0x41BB
#define mmCRTC3_CRTC_TRIGA_CNTL__VI                     0x4194
#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG__VI              0x4195
#define mmCRTC3_CRTC_TRIGB_CNTL__VI                     0x4196
#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG__VI              0x4197
#define mmCRTC3_CRTC_UPDATE_LOCK__VI                    0x41B5
#define mmCRTC3_CRTC_VBI_END__VI                        0x4186
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x41CF
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x41CE
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x41D1
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x41D0
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x41D3
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x41D2
#define mmCRTC3_CRTC_VERT_SYNC_CONTROL__VI              0x41AC
#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI     0x41B7
#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS__VI           0x418C
#define mmCRTC3_CRTC_V_BLANK_START_END__VI              0x418D
#define mmCRTC3_CRTC_V_SYNC_A__VI                       0x418E
#define mmCRTC3_CRTC_V_SYNC_A_CNTL__VI                  0x418F
#define mmCRTC3_CRTC_V_SYNC_B__VI                       0x4190
#define mmCRTC3_CRTC_V_SYNC_B_CNTL__VI                  0x4191
#define mmCRTC3_CRTC_V_TOTAL__VI                        0x4187
#define mmCRTC3_CRTC_V_TOTAL_CONTROL__VI                0x418A
#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS__VI             0x418B
#define mmCRTC3_CRTC_V_TOTAL_MAX__VI                    0x4189
#define mmCRTC3_CRTC_V_TOTAL_MIN__VI                    0x4188
#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS__VI            0x41C4
#define mmCRTC3_DCFE_DBG_SEL__VI                        0x417E
#define mmCRTC3_DCFE_MEM_PWR_CTRL__VI                   0x417F
#define mmCRTC3_DCFE_MEM_PWR_CTRL2__VI                  0x41B8
#define mmCRTC3_DCFE_MEM_PWR_STATUS__VI                 0x41B9
#define mmCRTC3_MASTER_UPDATE_LOCK__VI                  0x41BD
#define mmCRTC3_MASTER_UPDATE_MODE__SI__CI              0x44BE
#define mmCRTC3_MASTER_UPDATE_MODE__VI                  0x41BE
#define mmCRTC3_PIXEL_RATE_CNTL__VI                     0x014C
#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL__VI           0x4378
#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__VI           0x43C3
#define mmCRTC4_CRTC_AVSYNC_COUNTER__VI                 0x439B
#define mmCRTC4_CRTC_BLACK_COLOR__VI                    0x43CC
#define mmCRTC4_CRTC_BLACK_COLOR_EXT__VI                0x43CD
#define mmCRTC4_CRTC_BLANK_CONTROL__SI__CI              0x479D
#define mmCRTC4_CRTC_BLANK_CONTROL__VI                  0x439D
#define mmCRTC4_CRTC_BLANK_DATA_COLOR__VI               0x43CA
#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT__VI           0x43CB
#define mmCRTC4_CRTC_CONTROL__VI                        0x439C
#define mmCRTC4_CRTC_COUNT_CONTROL__VI                  0x43A9
#define mmCRTC4_CRTC_COUNT_RESET__VI                    0x43AA
#define mmCRTC4_CRTC_CRC0_DATA_B__VI                    0x43DA
#define mmCRTC4_CRTC_CRC0_DATA_RG__VI                   0x43D9
#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x43D5
#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x43D6
#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x43D7
#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x43D8
#define mmCRTC4_CRTC_CRC1_DATA_B__VI                    0x43E0
#define mmCRTC4_CRTC_CRC1_DATA_RG__VI                   0x43DF
#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x43DB
#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x43DC
#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x43DD
#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x43DE
#define mmCRTC4_CRTC_CRC_CNTL__VI                       0x43D4
#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL__VI             0x437C
#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL__VI          0x43B6
#define mmCRTC4_CRTC_DTMTEST_CNTL__VI                   0x4392
#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION__VI        0x4393
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x43E1
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x43E5
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x43E4
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x43E6
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x43E3
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x43E2
#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL__VI       0x43A0
#define mmCRTC4_CRTC_FLOW_CONTROL__VI                   0x4399
#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL__VI           0x4398
#define mmCRTC4_CRTC_GSL_CONTROL__VI                    0x437B
#define mmCRTC4_CRTC_GSL_VSYNC_GAP__VI                  0x4379
#define mmCRTC4_CRTC_GSL_WINDOW__VI                     0x437A
#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM__VI              0x437D
#define mmCRTC4_CRTC_H_BLANK_START_END__VI              0x4381
#define mmCRTC4_CRTC_H_SYNC_A__VI                       0x4382
#define mmCRTC4_CRTC_H_SYNC_A_CNTL__VI                  0x4383
#define mmCRTC4_CRTC_H_SYNC_B__VI                       0x4384
#define mmCRTC4_CRTC_H_SYNC_B_CNTL__VI                  0x4385
#define mmCRTC4_CRTC_H_TOTAL__VI                        0x4380
#define mmCRTC4_CRTC_INTERLACE_CONTROL__VI              0x439E
#define mmCRTC4_CRTC_INTERLACE_STATUS__VI               0x439F
#define mmCRTC4_CRTC_INTERRUPT_CONTROL__VI              0x43B4
#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI   0x43AB
#define mmCRTC4_CRTC_MASTER_EN__VI                      0x43C2
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT__VI         0x43BF
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI   0x43C0
#define mmCRTC4_CRTC_MVP_STATUS__VI                     0x43C1
#define mmCRTC4_CRTC_NOM_VERT_POSITION__VI              0x43A5
#define mmCRTC4_CRTC_OVERSCAN_COLOR__VI                 0x43C8
#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT__VI             0x43C9
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0__VI           0x43A1
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1__VI           0x43A2
#define mmCRTC4_CRTC_SNAPSHOT_CONTROL__VI               0x43B0
#define mmCRTC4_CRTC_SNAPSHOT_FRAME__VI                 0x43B2
#define mmCRTC4_CRTC_SNAPSHOT_POSITION__VI              0x43B1
#define mmCRTC4_CRTC_SNAPSHOT_STATUS__VI                0x43AF
#define mmCRTC4_CRTC_START_LINE_CONTROL__VI             0x43B3
#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL__VI          0x43E7
#define mmCRTC4_CRTC_STATUS__SI__CI                     0x47A3
#define mmCRTC4_CRTC_STATUS__VI                         0x43A3
#define mmCRTC4_CRTC_STATUS_FRAME_COUNT__VI             0x43A6
#define mmCRTC4_CRTC_STATUS_HV_COUNT__VI                0x43A8
#define mmCRTC4_CRTC_STATUS_POSITION__SI__CI            0x47A4
#define mmCRTC4_CRTC_STATUS_POSITION__VI                0x43A4
#define mmCRTC4_CRTC_STATUS_VF_COUNT__VI                0x43A7
#define mmCRTC4_CRTC_STEREO_CONTROL__VI                 0x43AE
#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x439A
#define mmCRTC4_CRTC_STEREO_STATUS__VI                  0x43AD
#define mmCRTC4_CRTC_TEST_DEBUG_DATA__VI                0x43C7
#define mmCRTC4_CRTC_TEST_DEBUG_INDEX__VI               0x43C6
#define mmCRTC4_CRTC_TEST_PATTERN_COLOR__VI             0x43BC
#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL__VI           0x43BA
#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS__VI        0x43BB
#define mmCRTC4_CRTC_TRIGA_CNTL__VI                     0x4394
#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG__VI              0x4395
#define mmCRTC4_CRTC_TRIGB_CNTL__VI                     0x4396
#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG__VI              0x4397
#define mmCRTC4_CRTC_UPDATE_LOCK__VI                    0x43B5
#define mmCRTC4_CRTC_VBI_END__VI                        0x4386
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x43CF
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x43CE
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x43D1
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x43D0
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x43D3
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x43D2
#define mmCRTC4_CRTC_VERT_SYNC_CONTROL__VI              0x43AC
#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI     0x43B7
#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS__VI           0x438C
#define mmCRTC4_CRTC_V_BLANK_START_END__VI              0x438D
#define mmCRTC4_CRTC_V_SYNC_A__VI                       0x438E
#define mmCRTC4_CRTC_V_SYNC_A_CNTL__VI                  0x438F
#define mmCRTC4_CRTC_V_SYNC_B__VI                       0x4390
#define mmCRTC4_CRTC_V_SYNC_B_CNTL__VI                  0x4391
#define mmCRTC4_CRTC_V_TOTAL__VI                        0x4387
#define mmCRTC4_CRTC_V_TOTAL_CONTROL__VI                0x438A
#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS__VI             0x438B
#define mmCRTC4_CRTC_V_TOTAL_MAX__VI                    0x4389
#define mmCRTC4_CRTC_V_TOTAL_MIN__VI                    0x4388
#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS__VI            0x43C4
#define mmCRTC4_DCFE_DBG_SEL__VI                        0x437E
#define mmCRTC4_DCFE_MEM_PWR_CTRL__VI                   0x437F
#define mmCRTC4_DCFE_MEM_PWR_CTRL2__VI                  0x43B8
#define mmCRTC4_DCFE_MEM_PWR_STATUS__VI                 0x43B9
#define mmCRTC4_MASTER_UPDATE_LOCK__VI                  0x43BD
#define mmCRTC4_MASTER_UPDATE_MODE__SI__CI              0x47BE
#define mmCRTC4_MASTER_UPDATE_MODE__VI                  0x43BE
#define mmCRTC4_PIXEL_RATE_CNTL__VI                     0x0150
#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL__VI           0x4578
#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__VI           0x45C3
#define mmCRTC5_CRTC_AVSYNC_COUNTER__VI                 0x459B
#define mmCRTC5_CRTC_BLACK_COLOR__VI                    0x45CC
#define mmCRTC5_CRTC_BLACK_COLOR_EXT__VI                0x45CD
#define mmCRTC5_CRTC_BLANK_CONTROL__SI__CI              0x4A9D
#define mmCRTC5_CRTC_BLANK_CONTROL__VI                  0x459D
#define mmCRTC5_CRTC_BLANK_DATA_COLOR__VI               0x45CA
#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT__VI           0x45CB
#define mmCRTC5_CRTC_CONTROL__VI                        0x459C
#define mmCRTC5_CRTC_COUNT_CONTROL__VI                  0x45A9
#define mmCRTC5_CRTC_COUNT_RESET__VI                    0x45AA
#define mmCRTC5_CRTC_CRC0_DATA_B__VI                    0x45DA
#define mmCRTC5_CRTC_CRC0_DATA_RG__VI                   0x45D9
#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x45D5
#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x45D6
#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x45D7
#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x45D8
#define mmCRTC5_CRTC_CRC1_DATA_B__VI                    0x45E0
#define mmCRTC5_CRTC_CRC1_DATA_RG__VI                   0x45DF
#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x45DB
#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x45DC
#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x45DD
#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x45DE
#define mmCRTC5_CRTC_CRC_CNTL__VI                       0x45D4
#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL__VI             0x457C
#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL__VI          0x45B6
#define mmCRTC5_CRTC_DTMTEST_CNTL__VI                   0x4592
#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION__VI        0x4593
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x45E1
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x45E5
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x45E4
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x45E6
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x45E3
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x45E2
#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL__VI       0x45A0
#define mmCRTC5_CRTC_FLOW_CONTROL__VI                   0x4599
#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL__VI           0x4598
#define mmCRTC5_CRTC_GSL_CONTROL__VI                    0x457B
#define mmCRTC5_CRTC_GSL_VSYNC_GAP__VI                  0x4579
#define mmCRTC5_CRTC_GSL_WINDOW__VI                     0x457A
#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM__VI              0x457D
#define mmCRTC5_CRTC_H_BLANK_START_END__VI              0x4581
#define mmCRTC5_CRTC_H_SYNC_A__VI                       0x4582
#define mmCRTC5_CRTC_H_SYNC_A_CNTL__VI                  0x4583
#define mmCRTC5_CRTC_H_SYNC_B__VI                       0x4584
#define mmCRTC5_CRTC_H_SYNC_B_CNTL__VI                  0x4585
#define mmCRTC5_CRTC_H_TOTAL__VI                        0x4580
#define mmCRTC5_CRTC_INTERLACE_CONTROL__VI              0x459E
#define mmCRTC5_CRTC_INTERLACE_STATUS__VI               0x459F
#define mmCRTC5_CRTC_INTERRUPT_CONTROL__VI              0x45B4
#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI   0x45AB
#define mmCRTC5_CRTC_MASTER_EN__VI                      0x45C2
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT__VI         0x45BF
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI   0x45C0
#define mmCRTC5_CRTC_MVP_STATUS__VI                     0x45C1
#define mmCRTC5_CRTC_NOM_VERT_POSITION__VI              0x45A5
#define mmCRTC5_CRTC_OVERSCAN_COLOR__VI                 0x45C8
#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT__VI             0x45C9
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0__VI           0x45A1
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1__VI           0x45A2
#define mmCRTC5_CRTC_SNAPSHOT_CONTROL__VI               0x45B0
#define mmCRTC5_CRTC_SNAPSHOT_FRAME__VI                 0x45B2
#define mmCRTC5_CRTC_SNAPSHOT_POSITION__VI              0x45B1
#define mmCRTC5_CRTC_SNAPSHOT_STATUS__VI                0x45AF
#define mmCRTC5_CRTC_START_LINE_CONTROL__VI             0x45B3
#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL__VI          0x45E7
#define mmCRTC5_CRTC_STATUS__SI__CI                     0x4AA3
#define mmCRTC5_CRTC_STATUS__VI                         0x45A3
#define mmCRTC5_CRTC_STATUS_FRAME_COUNT__VI             0x45A6
#define mmCRTC5_CRTC_STATUS_HV_COUNT__VI                0x45A8
#define mmCRTC5_CRTC_STATUS_POSITION__SI__CI            0x4AA4
#define mmCRTC5_CRTC_STATUS_POSITION__VI                0x45A4
#define mmCRTC5_CRTC_STATUS_VF_COUNT__VI                0x45A7
#define mmCRTC5_CRTC_STEREO_CONTROL__VI                 0x45AE
#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x459A
#define mmCRTC5_CRTC_STEREO_STATUS__VI                  0x45AD
#define mmCRTC5_CRTC_TEST_DEBUG_DATA__VI                0x45C7
#define mmCRTC5_CRTC_TEST_DEBUG_INDEX__VI               0x45C6
#define mmCRTC5_CRTC_TEST_PATTERN_COLOR__VI             0x45BC
#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL__VI           0x45BA
#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS__VI        0x45BB
#define mmCRTC5_CRTC_TRIGA_CNTL__VI                     0x4594
#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG__VI              0x4595
#define mmCRTC5_CRTC_TRIGB_CNTL__VI                     0x4596
#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG__VI              0x4597
#define mmCRTC5_CRTC_UPDATE_LOCK__VI                    0x45B5
#define mmCRTC5_CRTC_VBI_END__VI                        0x4586
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x45CF
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x45CE
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x45D1
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x45D0
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x45D3
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x45D2
#define mmCRTC5_CRTC_VERT_SYNC_CONTROL__VI              0x45AC
#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI     0x45B7
#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS__VI           0x458C
#define mmCRTC5_CRTC_V_BLANK_START_END__VI              0x458D
#define mmCRTC5_CRTC_V_SYNC_A__VI                       0x458E
#define mmCRTC5_CRTC_V_SYNC_A_CNTL__VI                  0x458F
#define mmCRTC5_CRTC_V_SYNC_B__VI                       0x4590
#define mmCRTC5_CRTC_V_SYNC_B_CNTL__VI                  0x4591
#define mmCRTC5_CRTC_V_TOTAL__VI                        0x4587
#define mmCRTC5_CRTC_V_TOTAL_CONTROL__VI                0x458A
#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS__VI             0x458B
#define mmCRTC5_CRTC_V_TOTAL_MAX__VI                    0x4589
#define mmCRTC5_CRTC_V_TOTAL_MIN__VI                    0x4588
#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS__VI            0x45C4
#define mmCRTC5_DCFE_DBG_SEL__VI                        0x457E
#define mmCRTC5_DCFE_MEM_PWR_CTRL__VI                   0x457F
#define mmCRTC5_DCFE_MEM_PWR_CTRL2__VI                  0x45B8
#define mmCRTC5_DCFE_MEM_PWR_STATUS__VI                 0x45B9
#define mmCRTC5_MASTER_UPDATE_LOCK__VI                  0x45BD
#define mmCRTC5_MASTER_UPDATE_MODE__SI__CI              0x4ABE
#define mmCRTC5_MASTER_UPDATE_MODE__VI                  0x45BE
#define mmCRTC5_PIXEL_RATE_CNTL__VI                     0x0154
#define mmCRTC6_CRTC_3D_STRUCTURE_CONTROL__VI           0x4778
#define mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT__VI           0x47C3
#define mmCRTC6_CRTC_AVSYNC_COUNTER__VI                 0x479B
#define mmCRTC6_CRTC_BLACK_COLOR__VI                    0x47CC
#define mmCRTC6_CRTC_BLACK_COLOR_EXT__VI                0x47CD
#define mmCRTC6_CRTC_BLANK_CONTROL__VI                  0x479D
#define mmCRTC6_CRTC_BLANK_DATA_COLOR__VI               0x47CA
#define mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT__VI           0x47CB
#define mmCRTC6_CRTC_CONTROL__VI                        0x479C
#define mmCRTC6_CRTC_COUNT_CONTROL__VI                  0x47A9
#define mmCRTC6_CRTC_COUNT_RESET__VI                    0x47AA
#define mmCRTC6_CRTC_CRC0_DATA_B__VI                    0x47DA
#define mmCRTC6_CRTC_CRC0_DATA_RG__VI                   0x47D9
#define mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL__VI         0x47D5
#define mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL__VI         0x47D6
#define mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL__VI         0x47D7
#define mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL__VI         0x47D8
#define mmCRTC6_CRTC_CRC1_DATA_B__VI                    0x47E0
#define mmCRTC6_CRTC_CRC1_DATA_RG__VI                   0x47DF
#define mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL__VI         0x47DB
#define mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL__VI         0x47DC
#define mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL__VI         0x47DD
#define mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL__VI         0x47DE
#define mmCRTC6_CRTC_CRC_CNTL__VI                       0x47D4
#define mmCRTC6_CRTC_DCFE_CLOCK_CONTROL__VI             0x477C
#define mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL__VI          0x47B6
#define mmCRTC6_CRTC_DTMTEST_CNTL__VI                   0x4792
#define mmCRTC6_CRTC_DTMTEST_STATUS_POSITION__VI        0x4793
#define mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL__VI        0x47E1
#define mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI 0x47E5
#define mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x47E4
#define mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x47E6
#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI     0x47E3
#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI   0x47E2
#define mmCRTC6_CRTC_FIELD_INDICATION_CONTROL__VI       0x47A0
#define mmCRTC6_CRTC_FLOW_CONTROL__VI                   0x4799
#define mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL__VI           0x4798
#define mmCRTC6_CRTC_GSL_CONTROL__VI                    0x477B
#define mmCRTC6_CRTC_GSL_VSYNC_GAP__VI                  0x4779
#define mmCRTC6_CRTC_GSL_WINDOW__VI                     0x477A
#define mmCRTC6_CRTC_H_BLANK_EARLY_NUM__VI              0x477D
#define mmCRTC6_CRTC_H_BLANK_START_END__VI              0x4781
#define mmCRTC6_CRTC_H_SYNC_A__VI                       0x4782
#define mmCRTC6_CRTC_H_SYNC_A_CNTL__VI                  0x4783
#define mmCRTC6_CRTC_H_SYNC_B__VI                       0x4784
#define mmCRTC6_CRTC_H_SYNC_B_CNTL__VI                  0x4785
#define mmCRTC6_CRTC_H_TOTAL__VI                        0x4780
#define mmCRTC6_CRTC_INTERLACE_CONTROL__VI              0x479E
#define mmCRTC6_CRTC_INTERLACE_STATUS__VI               0x479F
#define mmCRTC6_CRTC_INTERRUPT_CONTROL__VI              0x47B4
#define mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI   0x47AB
#define mmCRTC6_CRTC_MASTER_EN__VI                      0x47C2
#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT__VI         0x47BF
#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI   0x47C0
#define mmCRTC6_CRTC_MVP_STATUS__VI                     0x47C1
#define mmCRTC6_CRTC_NOM_VERT_POSITION__VI              0x47A5
#define mmCRTC6_CRTC_OVERSCAN_COLOR__VI                 0x47C8
#define mmCRTC6_CRTC_OVERSCAN_COLOR_EXT__VI             0x47C9
#define mmCRTC6_CRTC_PIXEL_DATA_READBACK0__VI           0x47A1
#define mmCRTC6_CRTC_PIXEL_DATA_READBACK1__VI           0x47A2
#define mmCRTC6_CRTC_SNAPSHOT_CONTROL__VI               0x47B0
#define mmCRTC6_CRTC_SNAPSHOT_FRAME__VI                 0x47B2
#define mmCRTC6_CRTC_SNAPSHOT_POSITION__VI              0x47B1
#define mmCRTC6_CRTC_SNAPSHOT_STATUS__VI                0x47AF
#define mmCRTC6_CRTC_START_LINE_CONTROL__VI             0x47B3
#define mmCRTC6_CRTC_STATIC_SCREEN_CONTROL__VI          0x47E7
#define mmCRTC6_CRTC_STATUS__VI                         0x47A3
#define mmCRTC6_CRTC_STATUS_FRAME_COUNT__VI             0x47A6
#define mmCRTC6_CRTC_STATUS_HV_COUNT__VI                0x47A8
#define mmCRTC6_CRTC_STATUS_POSITION__VI                0x47A4
#define mmCRTC6_CRTC_STATUS_VF_COUNT__VI                0x47A7
#define mmCRTC6_CRTC_STEREO_CONTROL__VI                 0x47AE
#define mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE__VI          0x479A
#define mmCRTC6_CRTC_STEREO_STATUS__VI                  0x47AD
#define mmCRTC6_CRTC_TEST_DEBUG_DATA__VI                0x47C7
#define mmCRTC6_CRTC_TEST_DEBUG_INDEX__VI               0x47C6
#define mmCRTC6_CRTC_TEST_PATTERN_COLOR__VI             0x47BC
#define mmCRTC6_CRTC_TEST_PATTERN_CONTROL__VI           0x47BA
#define mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS__VI        0x47BB
#define mmCRTC6_CRTC_TRIGA_CNTL__VI                     0x4794
#define mmCRTC6_CRTC_TRIGA_MANUAL_TRIG__VI              0x4795
#define mmCRTC6_CRTC_TRIGB_CNTL__VI                     0x4796
#define mmCRTC6_CRTC_TRIGB_MANUAL_TRIG__VI              0x4797
#define mmCRTC6_CRTC_UPDATE_LOCK__VI                    0x47B5
#define mmCRTC6_CRTC_VBI_END__VI                        0x4786
#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI    0x47CF
#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION__VI   0x47CE
#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI    0x47D1
#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION__VI   0x47D0
#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI    0x47D3
#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION__VI   0x47D2
#define mmCRTC6_CRTC_VERT_SYNC_CONTROL__VI              0x47AC
#define mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI     0x47B7
#define mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS__VI           0x478C
#define mmCRTC6_CRTC_V_BLANK_START_END__VI              0x478D
#define mmCRTC6_CRTC_V_SYNC_A__VI                       0x478E
#define mmCRTC6_CRTC_V_SYNC_A_CNTL__VI                  0x478F
#define mmCRTC6_CRTC_V_SYNC_B__VI                       0x4790
#define mmCRTC6_CRTC_V_SYNC_B_CNTL__VI                  0x4791
#define mmCRTC6_CRTC_V_TOTAL__VI                        0x4787
#define mmCRTC6_CRTC_V_TOTAL_CONTROL__VI                0x478A
#define mmCRTC6_CRTC_V_TOTAL_INT_STATUS__VI             0x478B
#define mmCRTC6_CRTC_V_TOTAL_MAX__VI                    0x4789
#define mmCRTC6_CRTC_V_TOTAL_MIN__VI                    0x4788
#define mmCRTC6_CRTC_V_UPDATE_INT_STATUS__VI            0x47C4
#define mmCRTC6_DCFE_DBG_SEL__VI                        0x477E
#define mmCRTC6_DCFE_MEM_PWR_CTRL__VI                   0x477F
#define mmCRTC6_DCFE_MEM_PWR_CTRL2__VI                  0x47B8
#define mmCRTC6_DCFE_MEM_PWR_STATUS__VI                 0x47B9
#define mmCRTC6_MASTER_UPDATE_LOCK__VI                  0x47BD
#define mmCRTC6_MASTER_UPDATE_MODE__VI                  0x47BE
#define mmCRTC_3D_STRUCTURE_CONTROL__VI                 0x1B78
#define mmCRTC_AVSYNC_COUNTER__VI                       0x1B9B
#define mmCRTC_BLACK_COLOR__VI                          0x1BCC
#define mmCRTC_BLACK_COLOR_EXT__VI                      0x1BCD
#define mmCRTC_BLANK_DATA_COLOR__VI                     0x1BCA
#define mmCRTC_BLANK_DATA_COLOR_EXT__VI                 0x1BCB
#define mmCRTC_CRC0_DATA_B__VI                          0x1BDA
#define mmCRTC_CRC0_DATA_RG__VI                         0x1BD9
#define mmCRTC_CRC0_WINDOWA_X_CONTROL__VI               0x1BD5
#define mmCRTC_CRC0_WINDOWA_Y_CONTROL__VI               0x1BD6
#define mmCRTC_CRC0_WINDOWB_X_CONTROL__VI               0x1BD7
#define mmCRTC_CRC0_WINDOWB_Y_CONTROL__VI               0x1BD8
#define mmCRTC_CRC1_DATA_B__VI                          0x1BE0
#define mmCRTC_CRC1_DATA_RG__VI                         0x1BDF
#define mmCRTC_CRC1_WINDOWA_X_CONTROL__VI               0x1BDB
#define mmCRTC_CRC1_WINDOWA_Y_CONTROL__VI               0x1BDC
#define mmCRTC_CRC1_WINDOWB_X_CONTROL__VI               0x1BDD
#define mmCRTC_CRC1_WINDOWB_Y_CONTROL__VI               0x1BDE
#define mmCRTC_CRC_CNTL__VI                             0x1BD4
#define mmCRTC_DCFE_CLOCK_CONTROL__VI                   0x1B7C
#define mmCRTC_EXT_TIMING_SYNC_CONTROL__VI              0x1BE1
#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI    0x1BE5
#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI 0x1BE4
#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI 0x1BE6
#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END__VI           0x1BE3
#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START__VI         0x1BE2
#define mmCRTC_FIELD_INDICATION_CONTROL__VI             0x1BA0
#define mmCRTC_GSL_CONTROL__VI                          0x1B7B
#define mmCRTC_GSL_VSYNC_GAP__VI                        0x1B79
#define mmCRTC_GSL_WINDOW__VI                           0x1B7A
#define mmCRTC_H_BLANK_EARLY_NUM__VI                    0x1B7D
#define mmCRTC_OVERSCAN_COLOR__VI                       0x1BC8
#define mmCRTC_OVERSCAN_COLOR_EXT__VI                   0x1BC9
#define mmCRTC_PIXEL_DATA_READBACK0__VI                 0x1BA1
#define mmCRTC_PIXEL_DATA_READBACK1__VI                 0x1BA2
#define mmCRTC_STATIC_SCREEN_CONTROL__VI                0x1BE7
#define mmCRTC_STEREO_FORCE_NEXT_EYE__VI                0x1B9A
#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL__VI          0x1BCF
#define mmCRTC_VERTICAL_INTERRUPT0_POSITION__VI         0x1BCE
#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL__VI          0x1BD1
#define mmCRTC_VERTICAL_INTERRUPT1_POSITION__VI         0x1BD0
#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL__VI          0x1BD3
#define mmCRTC_VERTICAL_INTERRUPT2_POSITION__VI         0x1BD2
#define mmCUR2_COLOR1__VI                               0x1A75
#define mmCUR2_COLOR2__VI                               0x1A76
#define mmCUR2_CONTROL__VI                              0x1A6F
#define mmCUR2_HOT_SPOT__VI                             0x1A74
#define mmCUR2_POSITION__VI                             0x1A73
#define mmCUR2_SIZE__VI                                 0x1A71
#define mmCUR2_STEREO_CONTROL__VI                       0x1A9B
#define mmCUR2_SURFACE_ADDRESS__VI                      0x1A70
#define mmCUR2_SURFACE_ADDRESS_HIGH__VI                 0x1A72
#define mmCUR2_UPDATE__VI                               0x1A77
#define mmCUR_REQUEST_FILTER_CNTL__VI                   0x1A99
#define mmCUR_STEREO_CONTROL__VI                        0x1A9A
#define mmDAC_AUTODETECT_CONTROL__VI                    0x16B4
#define mmDAC_AUTODETECT_CONTROL2__VI                   0x16B5
#define mmDAC_AUTODETECT_CONTROL3__VI                   0x16B6
#define mmDAC_AUTODETECT_INT_CONTROL__VI                0x16B8
#define mmDAC_AUTODETECT_STATUS__VI                     0x16B7
#define mmDAC_CLK_ENABLE__VI                            0x0128
#define mmDAC_COMPARATOR_ENABLE__VI                     0x16BD
#define mmDAC_COMPARATOR_OUTPUT__VI                     0x16BE
#define mmDAC_CONTROL__VI                               0x16BC
#define mmDAC_CRC_CONTROL__VI                           0x16AD
#define mmDAC_CRC_EN__VI                                0x16AC
#define mmDAC_CRC_SIG_CONTROL__VI                       0x16B1
#define mmDAC_CRC_SIG_CONTROL_MASK__VI                  0x16AF
#define mmDAC_CRC_SIG_RGB__VI                           0x16B0
#define mmDAC_CRC_SIG_RGB_MASK__VI                      0x16AE
#define mmDAC_DFT_CONFIG__VI                            0x16C0
#define mmDAC_ENABLE__VI                                0x16AA
#define mmDAC_FIFO_STATUS__VI                           0x16C1
#define mmDAC_FORCE_DATA__VI                            0x16BA
#define mmDAC_FORCE_OUTPUT_CNTL__VI                     0x16B9
#define mmDAC_MACRO_CNTL_RESERVED0__VI                  0x48B8
#define mmDAC_MACRO_CNTL_RESERVED1__VI                  0x48B9
#define mmDAC_MACRO_CNTL_RESERVED2__VI                  0x48BA
#define mmDAC_MACRO_CNTL_RESERVED3__VI                  0x48BB
#define mmDAC_POWERDOWN__VI                             0x16BB
#define mmDAC_PWR_CNTL__VI                              0x16BF
#define mmDAC_SOURCE_SELECT__VI                         0x16AB
#define mmDAC_STEREOSYNC_SELECT__VI                     0x16B3
#define mmDAC_SYNC_TRISTATE_CONTROL__VI                 0x16B2
#define mmDAC_TEST_DEBUG_DATA__VI                       0x16C3
#define mmDAC_TEST_DEBUG_INDEX__VI                      0x16C2
#define mmDBG_OUT_CNTL__VI                              0x4834
#define mmDBG_SMB_BYPASS_SRBM_ACCESS__VI                0x14EB
#define mmDCCG_AUDIO_DTO0_MODULE__VI                    0x016D
#define mmDCCG_AUDIO_DTO0_PHASE__VI                     0x016C
#define mmDCCG_AUDIO_DTO1_MODULE__VI                    0x016F
#define mmDCCG_AUDIO_DTO1_PHASE__VI                     0x016E
#define mmDCCG_AUDIO_DTO_SOURCE__VI                     0x016B
#define mmDCCG_CAC_STATUS__VI                           0x0137
#define mmDCCG_CBUS_WRCMD_DELAY__VI                     0x0110
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0__VI      0x5FD0
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1__VI      0x5FD1
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10__VI     0x5FDA
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11__VI     0x5FDB
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2__VI      0x5FD2
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3__VI      0x5FD3
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4__VI      0x5FD4
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5__VI      0x5FD5
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6__VI      0x5FD6
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7__VI      0x5FD7
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8__VI      0x5FD8
#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9__VI      0x5FD9
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0__VI      0x5FDC
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1__VI      0x5FDD
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10__VI     0x5FE6
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11__VI     0x5FE7
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2__VI      0x5FDE
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3__VI      0x5FDF
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4__VI      0x5FE0
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5__VI      0x5FE1
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6__VI      0x5FE2
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7__VI      0x5FE3
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8__VI      0x5FE4
#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9__VI      0x5FE5
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0__VI      0x5FE8
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1__VI      0x5FE9
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10__VI     0x5FF2
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11__VI     0x5FF3
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2__VI      0x5FEA
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3__VI      0x5FEB
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4__VI      0x5FEC
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5__VI      0x5FED
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6__VI      0x5FEE
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7__VI      0x5FEF
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8__VI      0x5FF0
#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9__VI      0x5FF1
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0__VI      0x5FF4
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1__VI      0x5FF5
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10__VI     0x5FFE
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11__VI     0x5FFF
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2__VI      0x5FF6
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3__VI      0x5FF7
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4__VI      0x5FF8
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5__VI      0x5FF9
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6__VI      0x5FFA
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7__VI      0x5FFB
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8__VI      0x5FFC
#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9__VI      0x5FFD
#define mmDCCG_DISP_CNTL_REG__VI                        0x013F
#define mmDCCG_DS_CNTL__VI                              0x0115
#define mmDCCG_DS_DEBUG_CNTL__VI                        0x0112
#define mmDCCG_DS_DTO_INCR__VI                          0x0113
#define mmDCCG_DS_DTO_MODULO__VI                        0x0114
#define mmDCCG_DS_HW_CAL_INTERVAL__VI                   0x0116
#define mmDCCG_GATE_DISABLE_CNTL__VI                    0x0134
#define mmDCCG_GTC_CNTL__VI                             0x0120
#define mmDCCG_GTC_CURRENT__VI                          0x0123
#define mmDCCG_GTC_DTO_INCR__VI                         0x0121
#define mmDCCG_GTC_DTO_MODULO__VI                       0x0122
#define mmDCCG_PERFMON_CNTL__VI                         0x0133
#define mmDCCG_PERFMON_CNTL2__VI                        0x010E
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0__VI        0x1700
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1__VI        0x1701
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10__VI       0x170A
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11__VI       0x170B
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12__VI       0x170C
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13__VI       0x170D
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14__VI       0x170E
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15__VI       0x170F
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16__VI       0x1710
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17__VI       0x1711
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18__VI       0x1712
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19__VI       0x1713
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2__VI        0x1702
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20__VI       0x1714
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21__VI       0x1715
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22__VI       0x1716
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23__VI       0x1717
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24__VI       0x1718
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25__VI       0x1719
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26__VI       0x171A
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27__VI       0x171B
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28__VI       0x171C
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29__VI       0x171D
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3__VI        0x1703
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30__VI       0x171E
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31__VI       0x171F
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32__VI       0x1720
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33__VI       0x1721
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34__VI       0x1722
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35__VI       0x1723
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36__VI       0x1724
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37__VI       0x1725
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38__VI       0x1726
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39__VI       0x1727
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4__VI        0x1704
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40__VI       0x1728
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41__VI       0x1729
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5__VI        0x1705
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6__VI        0x1706
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7__VI        0x1707
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8__VI        0x1708
#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9__VI        0x1709
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0__VI        0x172A
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1__VI        0x172B
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10__VI       0x1734
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11__VI       0x1735
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12__VI       0x1736
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13__VI       0x1737
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14__VI       0x1738
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15__VI       0x1739
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16__VI       0x173A
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17__VI       0x173B
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18__VI       0x173C
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19__VI       0x173D
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2__VI        0x172C
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20__VI       0x173E
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21__VI       0x173F
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22__VI       0x1740
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23__VI       0x1741
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24__VI       0x1742
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25__VI       0x1743
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26__VI       0x1744
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27__VI       0x1745
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28__VI       0x1746
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29__VI       0x1747
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3__VI        0x172D
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30__VI       0x1748
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31__VI       0x1749
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32__VI       0x174A
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33__VI       0x174B
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34__VI       0x174C
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35__VI       0x174D
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36__VI       0x174E
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37__VI       0x174F
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38__VI       0x1750
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39__VI       0x1751
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4__VI        0x172E
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40__VI       0x1752
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41__VI       0x1753
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5__VI        0x172F
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6__VI        0x1730
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7__VI        0x1731
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8__VI        0x1732
#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9__VI        0x1733
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0__VI        0x1754
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1__VI        0x1755
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10__VI       0x175E
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11__VI       0x175F
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12__VI       0x1760
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13__VI       0x1761
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14__VI       0x1762
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15__VI       0x1763
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16__VI       0x1764
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17__VI       0x1765
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18__VI       0x1766
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19__VI       0x1767
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2__VI        0x1756
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20__VI       0x1768
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21__VI       0x1769
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22__VI       0x176A
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23__VI       0x176B
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24__VI       0x176C
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25__VI       0x176D
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26__VI       0x176E
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27__VI       0x176F
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28__VI       0x1770
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29__VI       0x1771
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3__VI        0x1757
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30__VI       0x1772
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31__VI       0x1773
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32__VI       0x1774
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33__VI       0x1775
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34__VI       0x1776
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35__VI       0x1777
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36__VI       0x1778
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37__VI       0x1779
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38__VI       0x177A
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39__VI       0x177B
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4__VI        0x1758
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40__VI       0x177C
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41__VI       0x177D
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5__VI        0x1759
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6__VI        0x175A
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7__VI        0x175B
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8__VI        0x175C
#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9__VI        0x175D
#define mmDCCG_SOFT_RESET__VI                           0x015F
#define mmDCCG_TEST_CLK_SEL__VI                         0x017E
#define mmDCCG_TEST_DEBUG_DATA__VI                      0x017D
#define mmDCCG_TEST_DEBUG_INDEX__VI                     0x017C
#define mmDCDEBUG_BUS_CLK1_SEL__VI                      0x16C4
#define mmDCDEBUG_BUS_CLK2_SEL__VI                      0x16C5
#define mmDCDEBUG_BUS_CLK3_SEL__VI                      0x16C6
#define mmDCDEBUG_BUS_CLK4_SEL__VI                      0x16C7
#define mmDCDEBUG_BUS_CLK5_SEL__VI                      0x16C8
#define mmDCDEBUG_OUT_CNTL__VI                          0x16CA
#define mmDCDEBUG_OUT_DATA__VI                          0x16CB
#define mmDCDEBUG_OUT_PIN_OVERRIDE__VI                  0x16C9
#define mmDCE_VCE_CONTROL__VI                           0x1856
#define mmDCFE0_DCFE_CLOCK_CONTROL__VI                  0x1B00
#define mmDCFE0_DCFE_DBG_CONFIG__VI                     0x1B02
#define mmDCFE0_DCFE_SOFT_RESET__VI                     0x1B01
#define mmDCFE1_DCFE_CLOCK_CONTROL__VI                  0x1D00
#define mmDCFE1_DCFE_DBG_CONFIG__VI                     0x1D02
#define mmDCFE1_DCFE_SOFT_RESET__VI                     0x1D01
#define mmDCFE2_DCFE_CLOCK_CONTROL__VI                  0x1F00
#define mmDCFE2_DCFE_DBG_CONFIG__VI                     0x1F02
#define mmDCFE2_DCFE_SOFT_RESET__VI                     0x1F01
#define mmDCFE3_DCFE_CLOCK_CONTROL__VI                  0x4100
#define mmDCFE3_DCFE_DBG_CONFIG__VI                     0x4102
#define mmDCFE3_DCFE_SOFT_RESET__VI                     0x4101
#define mmDCFE4_DCFE_CLOCK_CONTROL__VI                  0x4300
#define mmDCFE4_DCFE_DBG_CONFIG__VI                     0x4302
#define mmDCFE4_DCFE_SOFT_RESET__VI                     0x4301
#define mmDCFE5_DCFE_CLOCK_CONTROL__VI                  0x4500
#define mmDCFE5_DCFE_DBG_CONFIG__VI                     0x4502
#define mmDCFE5_DCFE_SOFT_RESET__VI                     0x4501
#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL__VI               0x0104
#define mmDCFEV0_PG_CONFIG__VI                          0x02DB
#define mmDCFEV0_PG_ENABLE__VI                          0x02DC
#define mmDCFEV0_PG_STATUS__VI                          0x02DD
#define mmDCFEV_CLOCK_CONTROL__VI                       0x46F4
#define mmDCFEV_DBG_CONFIG__VI                          0x46F7
#define mmDCFEV_DMIFV_CLOCK_CONTROL__VI                 0x46F6
#define mmDCFEV_DMIFV_MEM_PWR_CTRL__VI                  0x46F8
#define mmDCFEV_DMIFV_MEM_PWR_STATUS__VI                0x46F9
#define mmDCFEV_SOFT_RESET__VI                          0x46F5
#define mmDCFE_CLOCK_CONTROL__VI                        0x1B00
#define mmDCFE_DBG_CONFIG__VI                           0x1B02
#define mmDCFE_DBG_SEL__VI                              0x1B7E
#define mmDCFE_MEM_PWR_CTRL__VI                         0x1B7F
#define mmDCFE_MEM_PWR_CTRL2__VI                        0x1BB8
#define mmDCFE_MEM_PWR_STATUS__VI                       0x1BB9
#define mmDCFE_SOFT_RESET__VI                           0x1B01
#define mmDCIO_CLOCK_CNTL__VI                           0x482D
#define mmDCIO_DEBUG__VI                                0x482F
#define mmDCIO_DEBUG_CONFIG__VI                         0x4835
#define mmDCIO_DPHY_SEL__VI                             0x4837
#define mmDCIO_GSL0_CNTL__VI                            0x4826
#define mmDCIO_GSL1_CNTL__VI                            0x4827
#define mmDCIO_GSL2_CNTL__VI                            0x4828
#define mmDCIO_GSL_GENLK_PAD_CNTL__VI                   0x4824
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL__VI                0x4825
#define mmDCIO_IMPCAL_CNTL__VI                          0x483D
#define mmDCIO_IMPCAL_CNTL_CD__VI                       0x4841
#define mmDCIO_IMPCAL_CNTL_EF__VI                       0x4845
#define mmDCIO_SOFT_RESET__VI                           0x4836
#define mmDCIO_TEST_DEBUG_DATA__VI                      0x4832
#define mmDCIO_TEST_DEBUG_INDEX__VI                     0x4831
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x48C0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x48C1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x48CA
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x48CB
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x48CC
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x48CD
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x48CE
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x48CF
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x48D0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x48D1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x48D2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x48D3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x48C2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x48D4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x48D5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x48D6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x48D7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x48D8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x48D9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x48DA
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x48DB
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x48DC
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x48DD
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x48C3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x48DE
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x48DF
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x48C4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x48C5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x48C6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x48C7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x48C8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x48C9
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x48E0
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x48E1
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x48EA
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x48EB
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x48EC
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x48ED
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x48EE
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x48EF
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x48F0
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x48F1
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x48F2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x48F3
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x48E2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x48F4
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x48F5
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x48F6
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x48F7
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x48F8
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x48F9
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x48FA
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x48FB
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x48FC
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x48FD
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x48E3
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x48FE
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x48FF
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x48E4
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x48E5
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x48E6
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x48E7
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x48E8
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x48E9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x4900
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x4901
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x490A
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x490B
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x490C
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x490D
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x490E
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x490F
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x4910
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x4911
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x4912
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x4913
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x4902
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x4914
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x4915
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x4916
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x4917
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x4918
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x4919
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x491A
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x491B
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x491C
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x491D
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x4903
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x491E
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x491F
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x4904
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x4905
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x4906
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x4907
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x4908
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x4909
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x4920
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x4921
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x492A
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x492B
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x492C
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x492D
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x492E
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x492F
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x4930
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x4931
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x4932
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x4933
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x4922
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x4934
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x4935
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x4936
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x4937
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x4938
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x4939
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x493A
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x493B
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x493C
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x493D
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x4923
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x493E
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x493F
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x4924
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x4925
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x4926
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x4927
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x4928
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x4929
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x4940
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x4941
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x494A
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x494B
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x494C
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x494D
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x494E
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x494F
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x4950
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x4951
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x4952
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x4953
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x4942
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x4954
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x4955
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x4956
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x4957
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x4958
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x4959
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x495A
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x495B
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x495C
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x495D
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x4943
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x495E
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x495F
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x4944
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x4945
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x4946
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x4947
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x4948
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x4949
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x4960
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x4961
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x496A
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x496B
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x496C
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x496D
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x496E
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x496F
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x4970
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x4971
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x4972
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x4973
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x4962
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x4974
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x4975
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x4976
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x4977
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x4978
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x4979
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x497A
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x497B
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x497C
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x497D
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x4963
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x497E
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x497F
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x4964
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x4965
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x4966
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x4967
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x4968
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x4969
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__VI  0x4980
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__VI  0x4981
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__VI 0x498A
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__VI 0x498B
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__VI 0x498C
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__VI 0x498D
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__VI 0x498E
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__VI 0x498F
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__VI 0x4990
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__VI 0x4991
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__VI 0x4992
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__VI 0x4993
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__VI  0x4982
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__VI 0x4994
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__VI 0x4995
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__VI 0x4996
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__VI 0x4997
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__VI 0x4998
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__VI 0x4999
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__VI 0x499A
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__VI 0x499B
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__VI 0x499C
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__VI 0x499D
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__VI  0x4983
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__VI 0x499E
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__VI 0x499F
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__VI  0x4984
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__VI  0x4985
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__VI  0x4986
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__VI  0x4987
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__VI  0x4988
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__VI  0x4989
#define mmDCIO_WRCMD_DELAY__VI                          0x4816
#define mmDCI_CLK_CNTL__VI                              0x0319
#define mmDCI_CLK_RAMP_CNTL__VI                         0x031A
#define mmDCI_DEBUG_CONFIG__VI                          0x0320
#define mmDCI_MEM_PWR_CNTL__VI                          0x031B
#define mmDCI_MEM_PWR_CNTL2__VI                         0x031C
#define mmDCI_MEM_PWR_CNTL3__VI                         0x031D
#define mmDCI_MEM_PWR_STATUS__VI                        0x0317
#define mmDCI_MEM_PWR_STATUS2__VI                       0x0318
#define mmDCI_PG_DEBUG_CONFIG__VI                       0x1812
#define mmDCI_SOFT_RESET__VI                            0x0328
#define mmDCI_TEST_DEBUG_DATA__VI                       0x031F
#define mmDCI_TEST_DEBUG_INDEX__VI                      0x031E
#define mmDCO_CLK_CNTL__VI                              0x1864
#define mmDCO_CLK_RAMP_CNTL__VI                         0x1865
#define mmDCO_DCFE_EXT_VSYNC_CNTL__VI                   0x4830
#define mmDCO_MEM_PWR_CTRL__VI                          0x1862
#define mmDCO_MEM_PWR_CTRL2__VI                         0x1863
#define mmDCO_MEM_PWR_STATUS__VI                        0x1861
#define mmDCO_POWER_MANAGEMENT_CNTL__VI                 0x1868
#define mmDCO_SCRATCH0__VI                              0x184E
#define mmDCO_SCRATCH1__VI                              0x184F
#define mmDCO_SCRATCH2__VI                              0x1850
#define mmDCO_SCRATCH3__VI                              0x1851
#define mmDCO_SCRATCH4__VI                              0x1852
#define mmDCO_SCRATCH5__VI                              0x1853
#define mmDCO_SCRATCH6__VI                              0x1854
#define mmDCO_SCRATCH7__VI                              0x1855
#define mmDCO_SOFT_RESET__VI                            0x1871
#define mmDCO_STEREOSYNC_SEL__VI                        0x186E
#define mmDCO_TEST_DEBUG_DATA__VI                       0x1870
#define mmDCO_TEST_DEBUG_INDEX__VI                      0x186F
#define mmDCP0_ALPHA_CONTROL__VI                        0x1ABC
#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12__VI           0x1A43
#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14__VI           0x1A44
#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22__VI           0x1A45
#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24__VI           0x1A46
#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32__VI           0x1A47
#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34__VI           0x1A48
#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12__VI           0x1A49
#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14__VI           0x1A4A
#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22__VI           0x1A4B
#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24__VI           0x1A4C
#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32__VI           0x1A4D
#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34__VI           0x1A4E
#define mmDCP0_CUR2_COLOR1__VI                          0x1A75
#define mmDCP0_CUR2_COLOR2__VI                          0x1A76
#define mmDCP0_CUR2_CONTROL__VI                         0x1A6F
#define mmDCP0_CUR2_HOT_SPOT__VI                        0x1A74
#define mmDCP0_CUR2_POSITION__VI                        0x1A73
#define mmDCP0_CUR2_SIZE__VI                            0x1A71
#define mmDCP0_CUR2_STEREO_CONTROL__VI                  0x1A9B
#define mmDCP0_CUR2_SURFACE_ADDRESS__VI                 0x1A70
#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH__VI            0x1A72
#define mmDCP0_CUR2_UPDATE__VI                          0x1A77
#define mmDCP0_CUR_REQUEST_FILTER_CNTL__VI              0x1A99
#define mmDCP0_CUR_STEREO_CONTROL__VI                   0x1A9A
#define mmDCP0_DCP_DEBUG2__VI                           0x1A98
#define mmDCP0_DCP_FP_CONVERTED_FIELD__VI               0x1A65
#define mmDCP0_DCP_GSL_CONTROL__VI                      0x1A90
#define mmDCP0_DCP_RANDOM_SEEDS__VI                     0x1A61
#define mmDCP0_DCP_SPATIAL_DITHER_CNTL__VI              0x1A60
#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE__VI             0x1A7D
#define mmDCP0_DEGAMMA_CONTROL__VI                      0x1A58
#define mmDCP0_DENORM_CONTROL__VI                       0x1A50
#define mmDCP0_GAMUT_REMAP_C11_C12__VI                  0x1A5A
#define mmDCP0_GAMUT_REMAP_C13_C14__VI                  0x1A5B
#define mmDCP0_GAMUT_REMAP_C21_C22__VI                  0x1A5C
#define mmDCP0_GAMUT_REMAP_C23_C24__VI                  0x1A5D
#define mmDCP0_GAMUT_REMAP_C31_C32__VI                  0x1A5E
#define mmDCP0_GAMUT_REMAP_C33_C34__VI                  0x1A5F
#define mmDCP0_GAMUT_REMAP_CONTROL__VI                  0x1A59
#define mmDCP0_GRPH_FLIP_RATE_CNTL__VI                  0x1A8E
#define mmDCP0_GRPH_STEREOSYNC_FLIP__VI                 0x1A97
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI   0x1A9F
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI 0x1ABF
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI   0x1ABD
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI 0x1ABE
#define mmDCP0_HW_ROTATION__VI                          0x1A9E
#define mmDCP0_INPUT_CSC_C11_C12__VI                    0x1A36
#define mmDCP0_INPUT_CSC_C13_C14__VI                    0x1A37
#define mmDCP0_INPUT_CSC_C21_C22__VI                    0x1A38
#define mmDCP0_INPUT_CSC_C23_C24__VI                    0x1A39
#define mmDCP0_INPUT_CSC_C31_C32__VI                    0x1A3A
#define mmDCP0_INPUT_CSC_C33_C34__VI                    0x1A3B
#define mmDCP0_INPUT_CSC_CONTROL__VI                    0x1A35
#define mmDCP0_INPUT_GAMMA_CONTROL__VI                  0x1A10
#define mmDCP0_KEY_CONTROL__VI                          0x1A53
#define mmDCP0_KEY_RANGE_ALPHA__VI                      0x1A54
#define mmDCP0_KEY_RANGE_BLUE__VI                       0x1A57
#define mmDCP0_KEY_RANGE_GREEN__VI                      0x1A56
#define mmDCP0_KEY_RANGE_RED__VI                        0x1A55
#define mmDCP0_OUTPUT_CSC_C11_C12__VI                   0x1A3D
#define mmDCP0_OUTPUT_CSC_C13_C14__VI                   0x1A3E
#define mmDCP0_OUTPUT_CSC_C21_C22__VI                   0x1A3F
#define mmDCP0_OUTPUT_CSC_C23_C24__VI                   0x1A40
#define mmDCP0_OUTPUT_CSC_C31_C32__VI                   0x1A41
#define mmDCP0_OUTPUT_CSC_C33_C34__VI                   0x1A42
#define mmDCP0_OUTPUT_CSC_CONTROL__VI                   0x1A3C
#define mmDCP0_OUT_CLAMP_CONTROL_B_CB__VI               0x1A9D
#define mmDCP0_OUT_CLAMP_CONTROL_G_Y__VI                0x1A9C
#define mmDCP0_OUT_CLAMP_CONTROL_R_CR__VI               0x1A52
#define mmDCP0_OUT_ROUND_CONTROL__VI                    0x1A51
#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS__VI        0x1A92
#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI   0x1A94
#define mmDCP0_OVL_STEREOSYNC_FLIP__VI                  0x1A93
#define mmDCP0_PRESCALE_GRPH_CONTROL__VI                0x1A2D
#define mmDCP0_PRESCALE_OVL_CONTROL__VI                 0x1A31
#define mmDCP0_PRESCALE_VALUES_GRPH_B__VI               0x1A30
#define mmDCP0_PRESCALE_VALUES_GRPH_G__VI               0x1A2F
#define mmDCP0_PRESCALE_VALUES_GRPH_R__VI               0x1A2E
#define mmDCP0_PRESCALE_VALUES_OVL_CB__VI               0x1A32
#define mmDCP0_PRESCALE_VALUES_OVL_CR__VI               0x1A34
#define mmDCP0_PRESCALE_VALUES_OVL_Y__VI                0x1A33
#define mmDCP0_REGAMMA_CNTLA_END_CNTL1__VI              0x1AA6
#define mmDCP0_REGAMMA_CNTLA_END_CNTL2__VI              0x1AA7
#define mmDCP0_REGAMMA_CNTLA_REGION_0_1__VI             0x1AA8
#define mmDCP0_REGAMMA_CNTLA_REGION_10_11__VI           0x1AAD
#define mmDCP0_REGAMMA_CNTLA_REGION_12_13__VI           0x1AAE
#define mmDCP0_REGAMMA_CNTLA_REGION_14_15__VI           0x1AAF
#define mmDCP0_REGAMMA_CNTLA_REGION_2_3__VI             0x1AA9
#define mmDCP0_REGAMMA_CNTLA_REGION_4_5__VI             0x1AAA
#define mmDCP0_REGAMMA_CNTLA_REGION_6_7__VI             0x1AAB
#define mmDCP0_REGAMMA_CNTLA_REGION_8_9__VI             0x1AAC
#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL__VI             0x1AA5
#define mmDCP0_REGAMMA_CNTLA_START_CNTL__VI             0x1AA4
#define mmDCP0_REGAMMA_CNTLB_END_CNTL1__VI              0x1AB2
#define mmDCP0_REGAMMA_CNTLB_END_CNTL2__VI              0x1AB3
#define mmDCP0_REGAMMA_CNTLB_REGION_0_1__VI             0x1AB4
#define mmDCP0_REGAMMA_CNTLB_REGION_10_11__VI           0x1AB9
#define mmDCP0_REGAMMA_CNTLB_REGION_12_13__VI           0x1ABA
#define mmDCP0_REGAMMA_CNTLB_REGION_14_15__VI           0x1ABB
#define mmDCP0_REGAMMA_CNTLB_REGION_2_3__VI             0x1AB5
#define mmDCP0_REGAMMA_CNTLB_REGION_4_5__VI             0x1AB6
#define mmDCP0_REGAMMA_CNTLB_REGION_6_7__VI             0x1AB7
#define mmDCP0_REGAMMA_CNTLB_REGION_8_9__VI             0x1AB8
#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL__VI             0x1AB1
#define mmDCP0_REGAMMA_CNTLB_START_CNTL__VI             0x1AB0
#define mmDCP0_REGAMMA_CONTROL__VI                      0x1AA0
#define mmDCP0_REGAMMA_LUT_DATA__VI                     0x1AA2
#define mmDCP0_REGAMMA_LUT_INDEX__VI                    0x1AA1
#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK__VI            0x1AA3
#define mmDCP1_ALPHA_CONTROL__VI                        0x1CBC
#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12__VI           0x1C43
#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14__VI           0x1C44
#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22__VI           0x1C45
#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24__VI           0x1C46
#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32__VI           0x1C47
#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34__VI           0x1C48
#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12__VI           0x1C49
#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14__VI           0x1C4A
#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22__VI           0x1C4B
#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24__VI           0x1C4C
#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32__VI           0x1C4D
#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34__VI           0x1C4E
#define mmDCP1_CUR2_COLOR1__VI                          0x1C75
#define mmDCP1_CUR2_COLOR2__VI                          0x1C76
#define mmDCP1_CUR2_CONTROL__VI                         0x1C6F
#define mmDCP1_CUR2_HOT_SPOT__VI                        0x1C74
#define mmDCP1_CUR2_POSITION__VI                        0x1C73
#define mmDCP1_CUR2_SIZE__VI                            0x1C71
#define mmDCP1_CUR2_STEREO_CONTROL__VI                  0x1C9B
#define mmDCP1_CUR2_SURFACE_ADDRESS__VI                 0x1C70
#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH__VI            0x1C72
#define mmDCP1_CUR2_UPDATE__VI                          0x1C77
#define mmDCP1_CUR_COLOR1__VI                           0x1C6C
#define mmDCP1_CUR_COLOR2__VI                           0x1C6D
#define mmDCP1_CUR_CONTROL__VI                          0x1C66
#define mmDCP1_CUR_HOT_SPOT__VI                         0x1C6B
#define mmDCP1_CUR_POSITION__VI                         0x1C6A
#define mmDCP1_CUR_REQUEST_FILTER_CNTL__VI              0x1C99
#define mmDCP1_CUR_SIZE__VI                             0x1C68
#define mmDCP1_CUR_STEREO_CONTROL__VI                   0x1C9A
#define mmDCP1_CUR_SURFACE_ADDRESS__VI                  0x1C67
#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH__VI             0x1C69
#define mmDCP1_CUR_UPDATE__VI                           0x1C6E
#define mmDCP1_DCP_CRC_CONTROL__VI                      0x1C87
#define mmDCP1_DCP_CRC_CURRENT__VI                      0x1C89
#define mmDCP1_DCP_CRC_LAST__VI                         0x1C8B
#define mmDCP1_DCP_CRC_MASK__VI                         0x1C88
#define mmDCP1_DCP_DEBUG__VI                            0x1C8D
#define mmDCP1_DCP_DEBUG2__VI                           0x1C98
#define mmDCP1_DCP_FP_CONVERTED_FIELD__VI               0x1C65
#define mmDCP1_DCP_GSL_CONTROL__VI                      0x1C90
#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI        0x1C91
#define mmDCP1_DCP_RANDOM_SEEDS__VI                     0x1C61
#define mmDCP1_DCP_SPATIAL_DITHER_CNTL__VI              0x1C60
#define mmDCP1_DCP_TEST_DEBUG_DATA__VI                  0x1C96
#define mmDCP1_DCP_TEST_DEBUG_INDEX__VI                 0x1C95
#define mmDCP1_DC_LUT_30_COLOR__VI                      0x1C7C
#define mmDCP1_DC_LUT_AUTOFILL__VI                      0x1C7F
#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE__VI             0x1C81
#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN__VI            0x1C82
#define mmDCP1_DC_LUT_BLACK_OFFSET_RED__VI              0x1C83
#define mmDCP1_DC_LUT_CONTROL__VI                       0x1C80
#define mmDCP1_DC_LUT_PWL_DATA__VI                      0x1C7B
#define mmDCP1_DC_LUT_RW_INDEX__VI                      0x1C79
#define mmDCP1_DC_LUT_RW_MODE__VI                       0x1C78
#define mmDCP1_DC_LUT_SEQ_COLOR__VI                     0x1C7A
#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE__VI             0x1C7D
#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE__VI             0x1C84
#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN__VI            0x1C85
#define mmDCP1_DC_LUT_WHITE_OFFSET_RED__VI              0x1C86
#define mmDCP1_DC_LUT_WRITE_EN_MASK__VI                 0x1C7E
#define mmDCP1_DEGAMMA_CONTROL__VI                      0x1C58
#define mmDCP1_DENORM_CONTROL__VI                       0x1C50
#define mmDCP1_GAMUT_REMAP_C11_C12__VI                  0x1C5A
#define mmDCP1_GAMUT_REMAP_C13_C14__VI                  0x1C5B
#define mmDCP1_GAMUT_REMAP_C21_C22__VI                  0x1C5C
#define mmDCP1_GAMUT_REMAP_C23_C24__VI                  0x1C5D
#define mmDCP1_GAMUT_REMAP_C31_C32__VI                  0x1C5E
#define mmDCP1_GAMUT_REMAP_C33_C34__VI                  0x1C5F
#define mmDCP1_GAMUT_REMAP_CONTROL__VI                  0x1C59
#define mmDCP1_GRPH_COMPRESS_PITCH__VI                  0x1C1A
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS__VI        0x1C19
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI   0x1C1B
#define mmDCP1_GRPH_CONTROL__SI__CI                     0x1D01
#define mmDCP1_GRPH_CONTROL__VI                         0x1C01
#define mmDCP1_GRPH_DFQ_CONTROL__VI                     0x1C14
#define mmDCP1_GRPH_DFQ_STATUS__VI                      0x1C15
#define mmDCP1_GRPH_ENABLE__VI                          0x1C00
#define mmDCP1_GRPH_FLIP_CONTROL__SI__CI                0x1D12
#define mmDCP1_GRPH_FLIP_CONTROL__VI                    0x1C12
#define mmDCP1_GRPH_FLIP_RATE_CNTL__VI                  0x1C8E
#define mmDCP1_GRPH_INTERRUPT_CONTROL__VI               0x1C17
#define mmDCP1_GRPH_INTERRUPT_STATUS__VI                0x1C16
#define mmDCP1_GRPH_LUT_10BIT_BYPASS__VI                0x1C02
#define mmDCP1_GRPH_PITCH__SI__CI                       0x1D06
#define mmDCP1_GRPH_PITCH__VI                           0x1C06
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI     0x1D04
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS__VI         0x1C04
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI    0x1C07
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS__VI       0x1C05
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI  0x1C08
#define mmDCP1_GRPH_STEREOSYNC_FLIP__VI                 0x1C97
#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI      0x1C18
#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE__VI           0x1C13
#define mmDCP1_GRPH_SURFACE_OFFSET_X__VI                0x1C09
#define mmDCP1_GRPH_SURFACE_OFFSET_Y__VI                0x1C0A
#define mmDCP1_GRPH_SWAP_CNTL__VI                       0x1C03
#define mmDCP1_GRPH_UPDATE__SI__CI                      0x1D11
#define mmDCP1_GRPH_UPDATE__VI                          0x1C11
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI   0x1C9F
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI 0x1CBF
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI   0x1CBD
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI 0x1CBE
#define mmDCP1_GRPH_X_END__VI                           0x1C0D
#define mmDCP1_GRPH_X_START__VI                         0x1C0B
#define mmDCP1_GRPH_Y_END__VI                           0x1C0E
#define mmDCP1_GRPH_Y_START__VI                         0x1C0C
#define mmDCP1_HW_ROTATION__VI                          0x1C9E
#define mmDCP1_INPUT_CSC_C11_C12__VI                    0x1C36
#define mmDCP1_INPUT_CSC_C13_C14__VI                    0x1C37
#define mmDCP1_INPUT_CSC_C21_C22__VI                    0x1C38
#define mmDCP1_INPUT_CSC_C23_C24__VI                    0x1C39
#define mmDCP1_INPUT_CSC_C31_C32__VI                    0x1C3A
#define mmDCP1_INPUT_CSC_C33_C34__VI                    0x1C3B
#define mmDCP1_INPUT_CSC_CONTROL__VI                    0x1C35
#define mmDCP1_INPUT_GAMMA_CONTROL__VI                  0x1C10
#define mmDCP1_KEY_CONTROL__VI                          0x1C53
#define mmDCP1_KEY_RANGE_ALPHA__VI                      0x1C54
#define mmDCP1_KEY_RANGE_BLUE__VI                       0x1C57
#define mmDCP1_KEY_RANGE_GREEN__VI                      0x1C56
#define mmDCP1_KEY_RANGE_RED__VI                        0x1C55
#define mmDCP1_OUTPUT_CSC_C11_C12__VI                   0x1C3D
#define mmDCP1_OUTPUT_CSC_C13_C14__VI                   0x1C3E
#define mmDCP1_OUTPUT_CSC_C21_C22__VI                   0x1C3F
#define mmDCP1_OUTPUT_CSC_C23_C24__VI                   0x1C40
#define mmDCP1_OUTPUT_CSC_C31_C32__VI                   0x1C41
#define mmDCP1_OUTPUT_CSC_C33_C34__VI                   0x1C42
#define mmDCP1_OUTPUT_CSC_CONTROL__VI                   0x1C3C
#define mmDCP1_OUT_CLAMP_CONTROL_B_CB__VI               0x1C9D
#define mmDCP1_OUT_CLAMP_CONTROL_G_Y__VI                0x1C9C
#define mmDCP1_OUT_CLAMP_CONTROL_R_CR__VI               0x1C52
#define mmDCP1_OUT_ROUND_CONTROL__VI                    0x1C51
#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL__VI               0x1C2C
#define mmDCP1_OVL_CONTROL1__VI                         0x1C1D
#define mmDCP1_OVL_CONTROL2__VI                         0x1C1E
#define mmDCP1_OVL_DFQ_CONTROL__VI                      0x1C29
#define mmDCP1_OVL_DFQ_STATUS__VI                       0x1C2A
#define mmDCP1_OVL_ENABLE__VI                           0x1C1C
#define mmDCP1_OVL_END__VI                              0x1C26
#define mmDCP1_OVL_PITCH__VI                            0x1C21
#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS__VI        0x1C92
#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI   0x1C94
#define mmDCP1_OVL_START__VI                            0x1C25
#define mmDCP1_OVL_STEREOSYNC_FLIP__VI                  0x1C93
#define mmDCP1_OVL_SURFACE_ADDRESS__SI__CI              0x1D20
#define mmDCP1_OVL_SURFACE_ADDRESS__VI                  0x1C20
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH__VI             0x1C22
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI       0x1C2B
#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE__VI            0x1C28
#define mmDCP1_OVL_SURFACE_OFFSET_X__VI                 0x1C23
#define mmDCP1_OVL_SURFACE_OFFSET_Y__VI                 0x1C24
#define mmDCP1_OVL_SWAP_CNTL__VI                        0x1C1F
#define mmDCP1_OVL_UPDATE__VI                           0x1C27
#define mmDCP1_PRESCALE_GRPH_CONTROL__VI                0x1C2D
#define mmDCP1_PRESCALE_OVL_CONTROL__VI                 0x1C31
#define mmDCP1_PRESCALE_VALUES_GRPH_B__VI               0x1C30
#define mmDCP1_PRESCALE_VALUES_GRPH_G__VI               0x1C2F
#define mmDCP1_PRESCALE_VALUES_GRPH_R__VI               0x1C2E
#define mmDCP1_PRESCALE_VALUES_OVL_CB__VI               0x1C32
#define mmDCP1_PRESCALE_VALUES_OVL_CR__VI               0x1C34
#define mmDCP1_PRESCALE_VALUES_OVL_Y__VI                0x1C33
#define mmDCP1_REGAMMA_CNTLA_END_CNTL1__VI              0x1CA6
#define mmDCP1_REGAMMA_CNTLA_END_CNTL2__VI              0x1CA7
#define mmDCP1_REGAMMA_CNTLA_REGION_0_1__VI             0x1CA8
#define mmDCP1_REGAMMA_CNTLA_REGION_10_11__VI           0x1CAD
#define mmDCP1_REGAMMA_CNTLA_REGION_12_13__VI           0x1CAE
#define mmDCP1_REGAMMA_CNTLA_REGION_14_15__VI           0x1CAF
#define mmDCP1_REGAMMA_CNTLA_REGION_2_3__VI             0x1CA9
#define mmDCP1_REGAMMA_CNTLA_REGION_4_5__VI             0x1CAA
#define mmDCP1_REGAMMA_CNTLA_REGION_6_7__VI             0x1CAB
#define mmDCP1_REGAMMA_CNTLA_REGION_8_9__VI             0x1CAC
#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL__VI             0x1CA5
#define mmDCP1_REGAMMA_CNTLA_START_CNTL__VI             0x1CA4
#define mmDCP1_REGAMMA_CNTLB_END_CNTL1__VI              0x1CB2
#define mmDCP1_REGAMMA_CNTLB_END_CNTL2__VI              0x1CB3
#define mmDCP1_REGAMMA_CNTLB_REGION_0_1__VI             0x1CB4
#define mmDCP1_REGAMMA_CNTLB_REGION_10_11__VI           0x1CB9
#define mmDCP1_REGAMMA_CNTLB_REGION_12_13__VI           0x1CBA
#define mmDCP1_REGAMMA_CNTLB_REGION_14_15__VI           0x1CBB
#define mmDCP1_REGAMMA_CNTLB_REGION_2_3__VI             0x1CB5
#define mmDCP1_REGAMMA_CNTLB_REGION_4_5__VI             0x1CB6
#define mmDCP1_REGAMMA_CNTLB_REGION_6_7__VI             0x1CB7
#define mmDCP1_REGAMMA_CNTLB_REGION_8_9__VI             0x1CB8
#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL__VI             0x1CB1
#define mmDCP1_REGAMMA_CNTLB_START_CNTL__VI             0x1CB0
#define mmDCP1_REGAMMA_CONTROL__VI                      0x1CA0
#define mmDCP1_REGAMMA_LUT_DATA__VI                     0x1CA2
#define mmDCP1_REGAMMA_LUT_INDEX__VI                    0x1CA1
#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK__VI            0x1CA3
#define mmDCP2_ALPHA_CONTROL__VI                        0x1EBC
#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12__VI           0x1E43
#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14__VI           0x1E44
#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22__VI           0x1E45
#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24__VI           0x1E46
#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32__VI           0x1E47
#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34__VI           0x1E48
#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12__VI           0x1E49
#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14__VI           0x1E4A
#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22__VI           0x1E4B
#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24__VI           0x1E4C
#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32__VI           0x1E4D
#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34__VI           0x1E4E
#define mmDCP2_CUR2_COLOR1__VI                          0x1E75
#define mmDCP2_CUR2_COLOR2__VI                          0x1E76
#define mmDCP2_CUR2_CONTROL__VI                         0x1E6F
#define mmDCP2_CUR2_HOT_SPOT__VI                        0x1E74
#define mmDCP2_CUR2_POSITION__VI                        0x1E73
#define mmDCP2_CUR2_SIZE__VI                            0x1E71
#define mmDCP2_CUR2_STEREO_CONTROL__VI                  0x1E9B
#define mmDCP2_CUR2_SURFACE_ADDRESS__VI                 0x1E70
#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH__VI            0x1E72
#define mmDCP2_CUR2_UPDATE__VI                          0x1E77
#define mmDCP2_CUR_COLOR1__VI                           0x1E6C
#define mmDCP2_CUR_COLOR2__VI                           0x1E6D
#define mmDCP2_CUR_CONTROL__VI                          0x1E66
#define mmDCP2_CUR_HOT_SPOT__VI                         0x1E6B
#define mmDCP2_CUR_POSITION__VI                         0x1E6A
#define mmDCP2_CUR_REQUEST_FILTER_CNTL__VI              0x1E99
#define mmDCP2_CUR_SIZE__VI                             0x1E68
#define mmDCP2_CUR_STEREO_CONTROL__VI                   0x1E9A
#define mmDCP2_CUR_SURFACE_ADDRESS__VI                  0x1E67
#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH__VI             0x1E69
#define mmDCP2_CUR_UPDATE__VI                           0x1E6E
#define mmDCP2_DCP_CRC_CONTROL__VI                      0x1E87
#define mmDCP2_DCP_CRC_CURRENT__VI                      0x1E89
#define mmDCP2_DCP_CRC_LAST__VI                         0x1E8B
#define mmDCP2_DCP_CRC_MASK__VI                         0x1E88
#define mmDCP2_DCP_DEBUG__VI                            0x1E8D
#define mmDCP2_DCP_DEBUG2__VI                           0x1E98
#define mmDCP2_DCP_FP_CONVERTED_FIELD__VI               0x1E65
#define mmDCP2_DCP_GSL_CONTROL__VI                      0x1E90
#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI        0x1E91
#define mmDCP2_DCP_RANDOM_SEEDS__VI                     0x1E61
#define mmDCP2_DCP_SPATIAL_DITHER_CNTL__VI              0x1E60
#define mmDCP2_DCP_TEST_DEBUG_DATA__VI                  0x1E96
#define mmDCP2_DCP_TEST_DEBUG_INDEX__VI                 0x1E95
#define mmDCP2_DC_LUT_30_COLOR__VI                      0x1E7C
#define mmDCP2_DC_LUT_AUTOFILL__VI                      0x1E7F
#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE__VI             0x1E81
#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN__VI            0x1E82
#define mmDCP2_DC_LUT_BLACK_OFFSET_RED__VI              0x1E83
#define mmDCP2_DC_LUT_CONTROL__VI                       0x1E80
#define mmDCP2_DC_LUT_PWL_DATA__VI                      0x1E7B
#define mmDCP2_DC_LUT_RW_INDEX__VI                      0x1E79
#define mmDCP2_DC_LUT_RW_MODE__VI                       0x1E78
#define mmDCP2_DC_LUT_SEQ_COLOR__VI                     0x1E7A
#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE__VI             0x1E7D
#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE__VI             0x1E84
#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN__VI            0x1E85
#define mmDCP2_DC_LUT_WHITE_OFFSET_RED__VI              0x1E86
#define mmDCP2_DC_LUT_WRITE_EN_MASK__VI                 0x1E7E
#define mmDCP2_DEGAMMA_CONTROL__VI                      0x1E58
#define mmDCP2_DENORM_CONTROL__VI                       0x1E50
#define mmDCP2_GAMUT_REMAP_C11_C12__VI                  0x1E5A
#define mmDCP2_GAMUT_REMAP_C13_C14__VI                  0x1E5B
#define mmDCP2_GAMUT_REMAP_C21_C22__VI                  0x1E5C
#define mmDCP2_GAMUT_REMAP_C23_C24__VI                  0x1E5D
#define mmDCP2_GAMUT_REMAP_C31_C32__VI                  0x1E5E
#define mmDCP2_GAMUT_REMAP_C33_C34__VI                  0x1E5F
#define mmDCP2_GAMUT_REMAP_CONTROL__VI                  0x1E59
#define mmDCP2_GRPH_COMPRESS_PITCH__VI                  0x1E1A
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS__VI        0x1E19
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI   0x1E1B
#define mmDCP2_GRPH_CONTROL__SI__CI                     0x4001
#define mmDCP2_GRPH_CONTROL__VI                         0x1E01
#define mmDCP2_GRPH_DFQ_CONTROL__VI                     0x1E14
#define mmDCP2_GRPH_DFQ_STATUS__VI                      0x1E15
#define mmDCP2_GRPH_ENABLE__VI                          0x1E00
#define mmDCP2_GRPH_FLIP_CONTROL__SI__CI                0x4012
#define mmDCP2_GRPH_FLIP_CONTROL__VI                    0x1E12
#define mmDCP2_GRPH_FLIP_RATE_CNTL__VI                  0x1E8E
#define mmDCP2_GRPH_INTERRUPT_CONTROL__VI               0x1E17
#define mmDCP2_GRPH_INTERRUPT_STATUS__VI                0x1E16
#define mmDCP2_GRPH_LUT_10BIT_BYPASS__VI                0x1E02
#define mmDCP2_GRPH_PITCH__SI__CI                       0x4006
#define mmDCP2_GRPH_PITCH__VI                           0x1E06
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI     0x4004
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS__VI         0x1E04
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI    0x1E07
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS__VI       0x1E05
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI  0x1E08
#define mmDCP2_GRPH_STEREOSYNC_FLIP__VI                 0x1E97
#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI      0x1E18
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE__VI           0x1E13
#define mmDCP2_GRPH_SURFACE_OFFSET_X__VI                0x1E09
#define mmDCP2_GRPH_SURFACE_OFFSET_Y__VI                0x1E0A
#define mmDCP2_GRPH_SWAP_CNTL__VI                       0x1E03
#define mmDCP2_GRPH_UPDATE__SI__CI                      0x4011
#define mmDCP2_GRPH_UPDATE__VI                          0x1E11
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI   0x1E9F
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI 0x1EBF
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI   0x1EBD
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI 0x1EBE
#define mmDCP2_GRPH_X_END__VI                           0x1E0D
#define mmDCP2_GRPH_X_START__VI                         0x1E0B
#define mmDCP2_GRPH_Y_END__VI                           0x1E0E
#define mmDCP2_GRPH_Y_START__VI                         0x1E0C
#define mmDCP2_HW_ROTATION__VI                          0x1E9E
#define mmDCP2_INPUT_CSC_C11_C12__VI                    0x1E36
#define mmDCP2_INPUT_CSC_C13_C14__VI                    0x1E37
#define mmDCP2_INPUT_CSC_C21_C22__VI                    0x1E38
#define mmDCP2_INPUT_CSC_C23_C24__VI                    0x1E39
#define mmDCP2_INPUT_CSC_C31_C32__VI                    0x1E3A
#define mmDCP2_INPUT_CSC_C33_C34__VI                    0x1E3B
#define mmDCP2_INPUT_CSC_CONTROL__VI                    0x1E35
#define mmDCP2_INPUT_GAMMA_CONTROL__VI                  0x1E10
#define mmDCP2_KEY_CONTROL__VI                          0x1E53
#define mmDCP2_KEY_RANGE_ALPHA__VI                      0x1E54
#define mmDCP2_KEY_RANGE_BLUE__VI                       0x1E57
#define mmDCP2_KEY_RANGE_GREEN__VI                      0x1E56
#define mmDCP2_KEY_RANGE_RED__VI                        0x1E55
#define mmDCP2_OUTPUT_CSC_C11_C12__VI                   0x1E3D
#define mmDCP2_OUTPUT_CSC_C13_C14__VI                   0x1E3E
#define mmDCP2_OUTPUT_CSC_C21_C22__VI                   0x1E3F
#define mmDCP2_OUTPUT_CSC_C23_C24__VI                   0x1E40
#define mmDCP2_OUTPUT_CSC_C31_C32__VI                   0x1E41
#define mmDCP2_OUTPUT_CSC_C33_C34__VI                   0x1E42
#define mmDCP2_OUTPUT_CSC_CONTROL__VI                   0x1E3C
#define mmDCP2_OUT_CLAMP_CONTROL_B_CB__VI               0x1E9D
#define mmDCP2_OUT_CLAMP_CONTROL_G_Y__VI                0x1E9C
#define mmDCP2_OUT_CLAMP_CONTROL_R_CR__VI               0x1E52
#define mmDCP2_OUT_ROUND_CONTROL__VI                    0x1E51
#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL__VI               0x1E2C
#define mmDCP2_OVL_CONTROL1__VI                         0x1E1D
#define mmDCP2_OVL_CONTROL2__VI                         0x1E1E
#define mmDCP2_OVL_DFQ_CONTROL__VI                      0x1E29
#define mmDCP2_OVL_DFQ_STATUS__VI                       0x1E2A
#define mmDCP2_OVL_ENABLE__VI                           0x1E1C
#define mmDCP2_OVL_END__VI                              0x1E26
#define mmDCP2_OVL_PITCH__VI                            0x1E21
#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS__VI        0x1E92
#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI   0x1E94
#define mmDCP2_OVL_START__VI                            0x1E25
#define mmDCP2_OVL_STEREOSYNC_FLIP__VI                  0x1E93
#define mmDCP2_OVL_SURFACE_ADDRESS__SI__CI              0x4020
#define mmDCP2_OVL_SURFACE_ADDRESS__VI                  0x1E20
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH__VI             0x1E22
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI       0x1E2B
#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE__VI            0x1E28
#define mmDCP2_OVL_SURFACE_OFFSET_X__VI                 0x1E23
#define mmDCP2_OVL_SURFACE_OFFSET_Y__VI                 0x1E24
#define mmDCP2_OVL_SWAP_CNTL__VI                        0x1E1F
#define mmDCP2_OVL_UPDATE__VI                           0x1E27
#define mmDCP2_PRESCALE_GRPH_CONTROL__VI                0x1E2D
#define mmDCP2_PRESCALE_OVL_CONTROL__VI                 0x1E31
#define mmDCP2_PRESCALE_VALUES_GRPH_B__VI               0x1E30
#define mmDCP2_PRESCALE_VALUES_GRPH_G__VI               0x1E2F
#define mmDCP2_PRESCALE_VALUES_GRPH_R__VI               0x1E2E
#define mmDCP2_PRESCALE_VALUES_OVL_CB__VI               0x1E32
#define mmDCP2_PRESCALE_VALUES_OVL_CR__VI               0x1E34
#define mmDCP2_PRESCALE_VALUES_OVL_Y__VI                0x1E33
#define mmDCP2_REGAMMA_CNTLA_END_CNTL1__VI              0x1EA6
#define mmDCP2_REGAMMA_CNTLA_END_CNTL2__VI              0x1EA7
#define mmDCP2_REGAMMA_CNTLA_REGION_0_1__VI             0x1EA8
#define mmDCP2_REGAMMA_CNTLA_REGION_10_11__VI           0x1EAD
#define mmDCP2_REGAMMA_CNTLA_REGION_12_13__VI           0x1EAE
#define mmDCP2_REGAMMA_CNTLA_REGION_14_15__VI           0x1EAF
#define mmDCP2_REGAMMA_CNTLA_REGION_2_3__VI             0x1EA9
#define mmDCP2_REGAMMA_CNTLA_REGION_4_5__VI             0x1EAA
#define mmDCP2_REGAMMA_CNTLA_REGION_6_7__VI             0x1EAB
#define mmDCP2_REGAMMA_CNTLA_REGION_8_9__VI             0x1EAC
#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL__VI             0x1EA5
#define mmDCP2_REGAMMA_CNTLA_START_CNTL__VI             0x1EA4
#define mmDCP2_REGAMMA_CNTLB_END_CNTL1__VI              0x1EB2
#define mmDCP2_REGAMMA_CNTLB_END_CNTL2__VI              0x1EB3
#define mmDCP2_REGAMMA_CNTLB_REGION_0_1__VI             0x1EB4
#define mmDCP2_REGAMMA_CNTLB_REGION_10_11__VI           0x1EB9
#define mmDCP2_REGAMMA_CNTLB_REGION_12_13__VI           0x1EBA
#define mmDCP2_REGAMMA_CNTLB_REGION_14_15__VI           0x1EBB
#define mmDCP2_REGAMMA_CNTLB_REGION_2_3__VI             0x1EB5
#define mmDCP2_REGAMMA_CNTLB_REGION_4_5__VI             0x1EB6
#define mmDCP2_REGAMMA_CNTLB_REGION_6_7__VI             0x1EB7
#define mmDCP2_REGAMMA_CNTLB_REGION_8_9__VI             0x1EB8
#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL__VI             0x1EB1
#define mmDCP2_REGAMMA_CNTLB_START_CNTL__VI             0x1EB0
#define mmDCP2_REGAMMA_CONTROL__VI                      0x1EA0
#define mmDCP2_REGAMMA_LUT_DATA__VI                     0x1EA2
#define mmDCP2_REGAMMA_LUT_INDEX__VI                    0x1EA1
#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK__VI            0x1EA3
#define mmDCP3_ALPHA_CONTROL__VI                        0x40BC
#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12__VI           0x4043
#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14__VI           0x4044
#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22__VI           0x4045
#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24__VI           0x4046
#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32__VI           0x4047
#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34__VI           0x4048
#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12__VI           0x4049
#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14__VI           0x404A
#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22__VI           0x404B
#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24__VI           0x404C
#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32__VI           0x404D
#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34__VI           0x404E
#define mmDCP3_CUR2_COLOR1__VI                          0x4075
#define mmDCP3_CUR2_COLOR2__VI                          0x4076
#define mmDCP3_CUR2_CONTROL__VI                         0x406F
#define mmDCP3_CUR2_HOT_SPOT__VI                        0x4074
#define mmDCP3_CUR2_POSITION__VI                        0x4073
#define mmDCP3_CUR2_SIZE__VI                            0x4071
#define mmDCP3_CUR2_STEREO_CONTROL__VI                  0x409B
#define mmDCP3_CUR2_SURFACE_ADDRESS__VI                 0x4070
#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH__VI            0x4072
#define mmDCP3_CUR2_UPDATE__VI                          0x4077
#define mmDCP3_CUR_COLOR1__VI                           0x406C
#define mmDCP3_CUR_COLOR2__VI                           0x406D
#define mmDCP3_CUR_CONTROL__VI                          0x4066
#define mmDCP3_CUR_HOT_SPOT__VI                         0x406B
#define mmDCP3_CUR_POSITION__VI                         0x406A
#define mmDCP3_CUR_REQUEST_FILTER_CNTL__VI              0x4099
#define mmDCP3_CUR_SIZE__VI                             0x4068
#define mmDCP3_CUR_STEREO_CONTROL__VI                   0x409A
#define mmDCP3_CUR_SURFACE_ADDRESS__VI                  0x4067
#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH__VI             0x4069
#define mmDCP3_CUR_UPDATE__VI                           0x406E
#define mmDCP3_DCP_CRC_CONTROL__VI                      0x4087
#define mmDCP3_DCP_CRC_CURRENT__VI                      0x4089
#define mmDCP3_DCP_CRC_LAST__VI                         0x408B
#define mmDCP3_DCP_CRC_MASK__VI                         0x4088
#define mmDCP3_DCP_DEBUG__VI                            0x408D
#define mmDCP3_DCP_DEBUG2__VI                           0x4098
#define mmDCP3_DCP_FP_CONVERTED_FIELD__VI               0x4065
#define mmDCP3_DCP_GSL_CONTROL__VI                      0x4090
#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI        0x4091
#define mmDCP3_DCP_RANDOM_SEEDS__VI                     0x4061
#define mmDCP3_DCP_SPATIAL_DITHER_CNTL__VI              0x4060
#define mmDCP3_DCP_TEST_DEBUG_DATA__VI                  0x4096
#define mmDCP3_DCP_TEST_DEBUG_INDEX__VI                 0x4095
#define mmDCP3_DC_LUT_30_COLOR__VI                      0x407C
#define mmDCP3_DC_LUT_AUTOFILL__VI                      0x407F
#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE__VI             0x4081
#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN__VI            0x4082
#define mmDCP3_DC_LUT_BLACK_OFFSET_RED__VI              0x4083
#define mmDCP3_DC_LUT_CONTROL__VI                       0x4080
#define mmDCP3_DC_LUT_PWL_DATA__VI                      0x407B
#define mmDCP3_DC_LUT_RW_INDEX__VI                      0x4079
#define mmDCP3_DC_LUT_RW_MODE__VI                       0x4078
#define mmDCP3_DC_LUT_SEQ_COLOR__VI                     0x407A
#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE__VI             0x407D
#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE__VI             0x4084
#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN__VI            0x4085
#define mmDCP3_DC_LUT_WHITE_OFFSET_RED__VI              0x4086
#define mmDCP3_DC_LUT_WRITE_EN_MASK__VI                 0x407E
#define mmDCP3_DEGAMMA_CONTROL__VI                      0x4058
#define mmDCP3_DENORM_CONTROL__VI                       0x4050
#define mmDCP3_GAMUT_REMAP_C11_C12__VI                  0x405A
#define mmDCP3_GAMUT_REMAP_C13_C14__VI                  0x405B
#define mmDCP3_GAMUT_REMAP_C21_C22__VI                  0x405C
#define mmDCP3_GAMUT_REMAP_C23_C24__VI                  0x405D
#define mmDCP3_GAMUT_REMAP_C31_C32__VI                  0x405E
#define mmDCP3_GAMUT_REMAP_C33_C34__VI                  0x405F
#define mmDCP3_GAMUT_REMAP_CONTROL__VI                  0x4059
#define mmDCP3_GRPH_COMPRESS_PITCH__VI                  0x401A
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS__VI        0x4019
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI   0x401B
#define mmDCP3_GRPH_CONTROL__SI__CI                     0x4301
#define mmDCP3_GRPH_CONTROL__VI                         0x4001
#define mmDCP3_GRPH_DFQ_CONTROL__VI                     0x4014
#define mmDCP3_GRPH_DFQ_STATUS__VI                      0x4015
#define mmDCP3_GRPH_ENABLE__VI                          0x4000
#define mmDCP3_GRPH_FLIP_CONTROL__SI__CI                0x4312
#define mmDCP3_GRPH_FLIP_CONTROL__VI                    0x4012
#define mmDCP3_GRPH_FLIP_RATE_CNTL__VI                  0x408E
#define mmDCP3_GRPH_INTERRUPT_CONTROL__VI               0x4017
#define mmDCP3_GRPH_INTERRUPT_STATUS__VI                0x4016
#define mmDCP3_GRPH_LUT_10BIT_BYPASS__VI                0x4002
#define mmDCP3_GRPH_PITCH__SI__CI                       0x4306
#define mmDCP3_GRPH_PITCH__VI                           0x4006
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI     0x4304
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS__VI         0x4004
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI    0x4007
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS__VI       0x4005
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI  0x4008
#define mmDCP3_GRPH_STEREOSYNC_FLIP__VI                 0x4097
#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI      0x4018
#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE__VI           0x4013
#define mmDCP3_GRPH_SURFACE_OFFSET_X__VI                0x4009
#define mmDCP3_GRPH_SURFACE_OFFSET_Y__VI                0x400A
#define mmDCP3_GRPH_SWAP_CNTL__VI                       0x4003
#define mmDCP3_GRPH_UPDATE__SI__CI                      0x4311
#define mmDCP3_GRPH_UPDATE__VI                          0x4011
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI   0x409F
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI 0x40BF
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI   0x40BD
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI 0x40BE
#define mmDCP3_GRPH_X_END__VI                           0x400D
#define mmDCP3_GRPH_X_START__VI                         0x400B
#define mmDCP3_GRPH_Y_END__VI                           0x400E
#define mmDCP3_GRPH_Y_START__VI                         0x400C
#define mmDCP3_HW_ROTATION__VI                          0x409E
#define mmDCP3_INPUT_CSC_C11_C12__VI                    0x4036
#define mmDCP3_INPUT_CSC_C13_C14__VI                    0x4037
#define mmDCP3_INPUT_CSC_C21_C22__VI                    0x4038
#define mmDCP3_INPUT_CSC_C23_C24__VI                    0x4039
#define mmDCP3_INPUT_CSC_C31_C32__VI                    0x403A
#define mmDCP3_INPUT_CSC_C33_C34__VI                    0x403B
#define mmDCP3_INPUT_CSC_CONTROL__VI                    0x4035
#define mmDCP3_INPUT_GAMMA_CONTROL__VI                  0x4010
#define mmDCP3_KEY_CONTROL__VI                          0x4053
#define mmDCP3_KEY_RANGE_ALPHA__VI                      0x4054
#define mmDCP3_KEY_RANGE_BLUE__VI                       0x4057
#define mmDCP3_KEY_RANGE_GREEN__VI                      0x4056
#define mmDCP3_KEY_RANGE_RED__VI                        0x4055
#define mmDCP3_OUTPUT_CSC_C11_C12__VI                   0x403D
#define mmDCP3_OUTPUT_CSC_C13_C14__VI                   0x403E
#define mmDCP3_OUTPUT_CSC_C21_C22__VI                   0x403F
#define mmDCP3_OUTPUT_CSC_C23_C24__VI                   0x4040
#define mmDCP3_OUTPUT_CSC_C31_C32__VI                   0x4041
#define mmDCP3_OUTPUT_CSC_C33_C34__VI                   0x4042
#define mmDCP3_OUTPUT_CSC_CONTROL__VI                   0x403C
#define mmDCP3_OUT_CLAMP_CONTROL_B_CB__VI               0x409D
#define mmDCP3_OUT_CLAMP_CONTROL_G_Y__VI                0x409C
#define mmDCP3_OUT_CLAMP_CONTROL_R_CR__VI               0x4052
#define mmDCP3_OUT_ROUND_CONTROL__VI                    0x4051
#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL__VI               0x402C
#define mmDCP3_OVL_CONTROL1__VI                         0x401D
#define mmDCP3_OVL_CONTROL2__VI                         0x401E
#define mmDCP3_OVL_DFQ_CONTROL__VI                      0x4029
#define mmDCP3_OVL_DFQ_STATUS__VI                       0x402A
#define mmDCP3_OVL_ENABLE__VI                           0x401C
#define mmDCP3_OVL_END__VI                              0x4026
#define mmDCP3_OVL_PITCH__VI                            0x4021
#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS__VI        0x4092
#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI   0x4094
#define mmDCP3_OVL_START__VI                            0x4025
#define mmDCP3_OVL_STEREOSYNC_FLIP__VI                  0x4093
#define mmDCP3_OVL_SURFACE_ADDRESS__SI__CI              0x4320
#define mmDCP3_OVL_SURFACE_ADDRESS__VI                  0x4020
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH__VI             0x4022
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI       0x402B
#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE__VI            0x4028
#define mmDCP3_OVL_SURFACE_OFFSET_X__VI                 0x4023
#define mmDCP3_OVL_SURFACE_OFFSET_Y__VI                 0x4024
#define mmDCP3_OVL_SWAP_CNTL__VI                        0x401F
#define mmDCP3_OVL_UPDATE__VI                           0x4027
#define mmDCP3_PRESCALE_GRPH_CONTROL__VI                0x402D
#define mmDCP3_PRESCALE_OVL_CONTROL__VI                 0x4031
#define mmDCP3_PRESCALE_VALUES_GRPH_B__VI               0x4030
#define mmDCP3_PRESCALE_VALUES_GRPH_G__VI               0x402F
#define mmDCP3_PRESCALE_VALUES_GRPH_R__VI               0x402E
#define mmDCP3_PRESCALE_VALUES_OVL_CB__VI               0x4032
#define mmDCP3_PRESCALE_VALUES_OVL_CR__VI               0x4034
#define mmDCP3_PRESCALE_VALUES_OVL_Y__VI                0x4033
#define mmDCP3_REGAMMA_CNTLA_END_CNTL1__VI              0x40A6
#define mmDCP3_REGAMMA_CNTLA_END_CNTL2__VI              0x40A7
#define mmDCP3_REGAMMA_CNTLA_REGION_0_1__VI             0x40A8
#define mmDCP3_REGAMMA_CNTLA_REGION_10_11__VI           0x40AD
#define mmDCP3_REGAMMA_CNTLA_REGION_12_13__VI           0x40AE
#define mmDCP3_REGAMMA_CNTLA_REGION_14_15__VI           0x40AF
#define mmDCP3_REGAMMA_CNTLA_REGION_2_3__VI             0x40A9
#define mmDCP3_REGAMMA_CNTLA_REGION_4_5__VI             0x40AA
#define mmDCP3_REGAMMA_CNTLA_REGION_6_7__VI             0x40AB
#define mmDCP3_REGAMMA_CNTLA_REGION_8_9__VI             0x40AC
#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL__VI             0x40A5
#define mmDCP3_REGAMMA_CNTLA_START_CNTL__VI             0x40A4
#define mmDCP3_REGAMMA_CNTLB_END_CNTL1__VI              0x40B2
#define mmDCP3_REGAMMA_CNTLB_END_CNTL2__VI              0x40B3
#define mmDCP3_REGAMMA_CNTLB_REGION_0_1__VI             0x40B4
#define mmDCP3_REGAMMA_CNTLB_REGION_10_11__VI           0x40B9
#define mmDCP3_REGAMMA_CNTLB_REGION_12_13__VI           0x40BA
#define mmDCP3_REGAMMA_CNTLB_REGION_14_15__VI           0x40BB
#define mmDCP3_REGAMMA_CNTLB_REGION_2_3__VI             0x40B5
#define mmDCP3_REGAMMA_CNTLB_REGION_4_5__VI             0x40B6
#define mmDCP3_REGAMMA_CNTLB_REGION_6_7__VI             0x40B7
#define mmDCP3_REGAMMA_CNTLB_REGION_8_9__VI             0x40B8
#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL__VI             0x40B1
#define mmDCP3_REGAMMA_CNTLB_START_CNTL__VI             0x40B0
#define mmDCP3_REGAMMA_CONTROL__VI                      0x40A0
#define mmDCP3_REGAMMA_LUT_DATA__VI                     0x40A2
#define mmDCP3_REGAMMA_LUT_INDEX__VI                    0x40A1
#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK__VI            0x40A3
#define mmDCP4_ALPHA_CONTROL__VI                        0x42BC
#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12__VI           0x4243
#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14__VI           0x4244
#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22__VI           0x4245
#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24__VI           0x4246
#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32__VI           0x4247
#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34__VI           0x4248
#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12__VI           0x4249
#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14__VI           0x424A
#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22__VI           0x424B
#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24__VI           0x424C
#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32__VI           0x424D
#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34__VI           0x424E
#define mmDCP4_CUR2_COLOR1__VI                          0x4275
#define mmDCP4_CUR2_COLOR2__VI                          0x4276
#define mmDCP4_CUR2_CONTROL__VI                         0x426F
#define mmDCP4_CUR2_HOT_SPOT__VI                        0x4274
#define mmDCP4_CUR2_POSITION__VI                        0x4273
#define mmDCP4_CUR2_SIZE__VI                            0x4271
#define mmDCP4_CUR2_STEREO_CONTROL__VI                  0x429B
#define mmDCP4_CUR2_SURFACE_ADDRESS__VI                 0x4270
#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH__VI            0x4272
#define mmDCP4_CUR2_UPDATE__VI                          0x4277
#define mmDCP4_CUR_COLOR1__VI                           0x426C
#define mmDCP4_CUR_COLOR2__VI                           0x426D
#define mmDCP4_CUR_CONTROL__VI                          0x4266
#define mmDCP4_CUR_HOT_SPOT__VI                         0x426B
#define mmDCP4_CUR_POSITION__VI                         0x426A
#define mmDCP4_CUR_REQUEST_FILTER_CNTL__VI              0x4299
#define mmDCP4_CUR_SIZE__VI                             0x4268
#define mmDCP4_CUR_STEREO_CONTROL__VI                   0x429A
#define mmDCP4_CUR_SURFACE_ADDRESS__VI                  0x4267
#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH__VI             0x4269
#define mmDCP4_CUR_UPDATE__VI                           0x426E
#define mmDCP4_DCP_CRC_CONTROL__VI                      0x4287
#define mmDCP4_DCP_CRC_CURRENT__VI                      0x4289
#define mmDCP4_DCP_CRC_LAST__VI                         0x428B
#define mmDCP4_DCP_CRC_MASK__VI                         0x4288
#define mmDCP4_DCP_DEBUG__VI                            0x428D
#define mmDCP4_DCP_DEBUG2__VI                           0x4298
#define mmDCP4_DCP_FP_CONVERTED_FIELD__VI               0x4265
#define mmDCP4_DCP_GSL_CONTROL__VI                      0x4290
#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI        0x4291
#define mmDCP4_DCP_RANDOM_SEEDS__VI                     0x4261
#define mmDCP4_DCP_SPATIAL_DITHER_CNTL__VI              0x4260
#define mmDCP4_DCP_TEST_DEBUG_DATA__VI                  0x4296
#define mmDCP4_DCP_TEST_DEBUG_INDEX__VI                 0x4295
#define mmDCP4_DC_LUT_30_COLOR__VI                      0x427C
#define mmDCP4_DC_LUT_AUTOFILL__VI                      0x427F
#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE__VI             0x4281
#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN__VI            0x4282
#define mmDCP4_DC_LUT_BLACK_OFFSET_RED__VI              0x4283
#define mmDCP4_DC_LUT_CONTROL__VI                       0x4280
#define mmDCP4_DC_LUT_PWL_DATA__VI                      0x427B
#define mmDCP4_DC_LUT_RW_INDEX__VI                      0x4279
#define mmDCP4_DC_LUT_RW_MODE__VI                       0x4278
#define mmDCP4_DC_LUT_SEQ_COLOR__VI                     0x427A
#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE__VI             0x427D
#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE__VI             0x4284
#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN__VI            0x4285
#define mmDCP4_DC_LUT_WHITE_OFFSET_RED__VI              0x4286
#define mmDCP4_DC_LUT_WRITE_EN_MASK__VI                 0x427E
#define mmDCP4_DEGAMMA_CONTROL__VI                      0x4258
#define mmDCP4_DENORM_CONTROL__VI                       0x4250
#define mmDCP4_GAMUT_REMAP_C11_C12__VI                  0x425A
#define mmDCP4_GAMUT_REMAP_C13_C14__VI                  0x425B
#define mmDCP4_GAMUT_REMAP_C21_C22__VI                  0x425C
#define mmDCP4_GAMUT_REMAP_C23_C24__VI                  0x425D
#define mmDCP4_GAMUT_REMAP_C31_C32__VI                  0x425E
#define mmDCP4_GAMUT_REMAP_C33_C34__VI                  0x425F
#define mmDCP4_GAMUT_REMAP_CONTROL__VI                  0x4259
#define mmDCP4_GRPH_COMPRESS_PITCH__VI                  0x421A
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS__VI        0x4219
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI   0x421B
#define mmDCP4_GRPH_CONTROL__SI__CI                     0x4601
#define mmDCP4_GRPH_CONTROL__VI                         0x4201
#define mmDCP4_GRPH_DFQ_CONTROL__VI                     0x4214
#define mmDCP4_GRPH_DFQ_STATUS__VI                      0x4215
#define mmDCP4_GRPH_ENABLE__VI                          0x4200
#define mmDCP4_GRPH_FLIP_CONTROL__SI__CI                0x4612
#define mmDCP4_GRPH_FLIP_CONTROL__VI                    0x4212
#define mmDCP4_GRPH_FLIP_RATE_CNTL__VI                  0x428E
#define mmDCP4_GRPH_INTERRUPT_CONTROL__VI               0x4217
#define mmDCP4_GRPH_INTERRUPT_STATUS__VI                0x4216
#define mmDCP4_GRPH_LUT_10BIT_BYPASS__VI                0x4202
#define mmDCP4_GRPH_PITCH__SI__CI                       0x4606
#define mmDCP4_GRPH_PITCH__VI                           0x4206
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI     0x4604
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS__VI         0x4204
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI    0x4207
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS__VI       0x4205
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI  0x4208
#define mmDCP4_GRPH_STEREOSYNC_FLIP__VI                 0x4297
#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI      0x4218
#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE__VI           0x4213
#define mmDCP4_GRPH_SURFACE_OFFSET_X__VI                0x4209
#define mmDCP4_GRPH_SURFACE_OFFSET_Y__VI                0x420A
#define mmDCP4_GRPH_SWAP_CNTL__VI                       0x4203
#define mmDCP4_GRPH_UPDATE__SI__CI                      0x4611
#define mmDCP4_GRPH_UPDATE__VI                          0x4211
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI   0x429F
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI 0x42BF
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI   0x42BD
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI 0x42BE
#define mmDCP4_GRPH_X_END__VI                           0x420D
#define mmDCP4_GRPH_X_START__VI                         0x420B
#define mmDCP4_GRPH_Y_END__VI                           0x420E
#define mmDCP4_GRPH_Y_START__VI                         0x420C
#define mmDCP4_HW_ROTATION__VI                          0x429E
#define mmDCP4_INPUT_CSC_C11_C12__VI                    0x4236
#define mmDCP4_INPUT_CSC_C13_C14__VI                    0x4237
#define mmDCP4_INPUT_CSC_C21_C22__VI                    0x4238
#define mmDCP4_INPUT_CSC_C23_C24__VI                    0x4239
#define mmDCP4_INPUT_CSC_C31_C32__VI                    0x423A
#define mmDCP4_INPUT_CSC_C33_C34__VI                    0x423B
#define mmDCP4_INPUT_CSC_CONTROL__VI                    0x4235
#define mmDCP4_INPUT_GAMMA_CONTROL__VI                  0x4210
#define mmDCP4_KEY_CONTROL__VI                          0x4253
#define mmDCP4_KEY_RANGE_ALPHA__VI                      0x4254
#define mmDCP4_KEY_RANGE_BLUE__VI                       0x4257
#define mmDCP4_KEY_RANGE_GREEN__VI                      0x4256
#define mmDCP4_KEY_RANGE_RED__VI                        0x4255
#define mmDCP4_OUTPUT_CSC_C11_C12__VI                   0x423D
#define mmDCP4_OUTPUT_CSC_C13_C14__VI                   0x423E
#define mmDCP4_OUTPUT_CSC_C21_C22__VI                   0x423F
#define mmDCP4_OUTPUT_CSC_C23_C24__VI                   0x4240
#define mmDCP4_OUTPUT_CSC_C31_C32__VI                   0x4241
#define mmDCP4_OUTPUT_CSC_C33_C34__VI                   0x4242
#define mmDCP4_OUTPUT_CSC_CONTROL__VI                   0x423C
#define mmDCP4_OUT_CLAMP_CONTROL_B_CB__VI               0x429D
#define mmDCP4_OUT_CLAMP_CONTROL_G_Y__VI                0x429C
#define mmDCP4_OUT_CLAMP_CONTROL_R_CR__VI               0x4252
#define mmDCP4_OUT_ROUND_CONTROL__VI                    0x4251
#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL__VI               0x422C
#define mmDCP4_OVL_CONTROL1__VI                         0x421D
#define mmDCP4_OVL_CONTROL2__VI                         0x421E
#define mmDCP4_OVL_DFQ_CONTROL__VI                      0x4229
#define mmDCP4_OVL_DFQ_STATUS__VI                       0x422A
#define mmDCP4_OVL_ENABLE__VI                           0x421C
#define mmDCP4_OVL_END__VI                              0x4226
#define mmDCP4_OVL_PITCH__VI                            0x4221
#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS__VI        0x4292
#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI   0x4294
#define mmDCP4_OVL_START__VI                            0x4225
#define mmDCP4_OVL_STEREOSYNC_FLIP__VI                  0x4293
#define mmDCP4_OVL_SURFACE_ADDRESS__SI__CI              0x4620
#define mmDCP4_OVL_SURFACE_ADDRESS__VI                  0x4220
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH__VI             0x4222
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI       0x422B
#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE__VI            0x4228
#define mmDCP4_OVL_SURFACE_OFFSET_X__VI                 0x4223
#define mmDCP4_OVL_SURFACE_OFFSET_Y__VI                 0x4224
#define mmDCP4_OVL_SWAP_CNTL__VI                        0x421F
#define mmDCP4_OVL_UPDATE__VI                           0x4227
#define mmDCP4_PRESCALE_GRPH_CONTROL__VI                0x422D
#define mmDCP4_PRESCALE_OVL_CONTROL__VI                 0x4231
#define mmDCP4_PRESCALE_VALUES_GRPH_B__VI               0x4230
#define mmDCP4_PRESCALE_VALUES_GRPH_G__VI               0x422F
#define mmDCP4_PRESCALE_VALUES_GRPH_R__VI               0x422E
#define mmDCP4_PRESCALE_VALUES_OVL_CB__VI               0x4232
#define mmDCP4_PRESCALE_VALUES_OVL_CR__VI               0x4234
#define mmDCP4_PRESCALE_VALUES_OVL_Y__VI                0x4233
#define mmDCP4_REGAMMA_CNTLA_END_CNTL1__VI              0x42A6
#define mmDCP4_REGAMMA_CNTLA_END_CNTL2__VI              0x42A7
#define mmDCP4_REGAMMA_CNTLA_REGION_0_1__VI             0x42A8
#define mmDCP4_REGAMMA_CNTLA_REGION_10_11__VI           0x42AD
#define mmDCP4_REGAMMA_CNTLA_REGION_12_13__VI           0x42AE
#define mmDCP4_REGAMMA_CNTLA_REGION_14_15__VI           0x42AF
#define mmDCP4_REGAMMA_CNTLA_REGION_2_3__VI             0x42A9
#define mmDCP4_REGAMMA_CNTLA_REGION_4_5__VI             0x42AA
#define mmDCP4_REGAMMA_CNTLA_REGION_6_7__VI             0x42AB
#define mmDCP4_REGAMMA_CNTLA_REGION_8_9__VI             0x42AC
#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL__VI             0x42A5
#define mmDCP4_REGAMMA_CNTLA_START_CNTL__VI             0x42A4
#define mmDCP4_REGAMMA_CNTLB_END_CNTL1__VI              0x42B2
#define mmDCP4_REGAMMA_CNTLB_END_CNTL2__VI              0x42B3
#define mmDCP4_REGAMMA_CNTLB_REGION_0_1__VI             0x42B4
#define mmDCP4_REGAMMA_CNTLB_REGION_10_11__VI           0x42B9
#define mmDCP4_REGAMMA_CNTLB_REGION_12_13__VI           0x42BA
#define mmDCP4_REGAMMA_CNTLB_REGION_14_15__VI           0x42BB
#define mmDCP4_REGAMMA_CNTLB_REGION_2_3__VI             0x42B5
#define mmDCP4_REGAMMA_CNTLB_REGION_4_5__VI             0x42B6
#define mmDCP4_REGAMMA_CNTLB_REGION_6_7__VI             0x42B7
#define mmDCP4_REGAMMA_CNTLB_REGION_8_9__VI             0x42B8
#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL__VI             0x42B1
#define mmDCP4_REGAMMA_CNTLB_START_CNTL__VI             0x42B0
#define mmDCP4_REGAMMA_CONTROL__VI                      0x42A0
#define mmDCP4_REGAMMA_LUT_DATA__VI                     0x42A2
#define mmDCP4_REGAMMA_LUT_INDEX__VI                    0x42A1
#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK__VI            0x42A3
#define mmDCP5_ALPHA_CONTROL__VI                        0x44BC
#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12__VI           0x4443
#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14__VI           0x4444
#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22__VI           0x4445
#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24__VI           0x4446
#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32__VI           0x4447
#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34__VI           0x4448
#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12__VI           0x4449
#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14__VI           0x444A
#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22__VI           0x444B
#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24__VI           0x444C
#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32__VI           0x444D
#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34__VI           0x444E
#define mmDCP5_CUR2_COLOR1__VI                          0x4475
#define mmDCP5_CUR2_COLOR2__VI                          0x4476
#define mmDCP5_CUR2_CONTROL__VI                         0x446F
#define mmDCP5_CUR2_HOT_SPOT__VI                        0x4474
#define mmDCP5_CUR2_POSITION__VI                        0x4473
#define mmDCP5_CUR2_SIZE__VI                            0x4471
#define mmDCP5_CUR2_STEREO_CONTROL__VI                  0x449B
#define mmDCP5_CUR2_SURFACE_ADDRESS__VI                 0x4470
#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH__VI            0x4472
#define mmDCP5_CUR2_UPDATE__VI                          0x4477
#define mmDCP5_CUR_COLOR1__VI                           0x446C
#define mmDCP5_CUR_COLOR2__VI                           0x446D
#define mmDCP5_CUR_CONTROL__VI                          0x4466
#define mmDCP5_CUR_HOT_SPOT__VI                         0x446B
#define mmDCP5_CUR_POSITION__VI                         0x446A
#define mmDCP5_CUR_REQUEST_FILTER_CNTL__VI              0x4499
#define mmDCP5_CUR_SIZE__VI                             0x4468
#define mmDCP5_CUR_STEREO_CONTROL__VI                   0x449A
#define mmDCP5_CUR_SURFACE_ADDRESS__VI                  0x4467
#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH__VI             0x4469
#define mmDCP5_CUR_UPDATE__VI                           0x446E
#define mmDCP5_DCP_CRC_CONTROL__VI                      0x4487
#define mmDCP5_DCP_CRC_CURRENT__VI                      0x4489
#define mmDCP5_DCP_CRC_LAST__VI                         0x448B
#define mmDCP5_DCP_CRC_MASK__VI                         0x4488
#define mmDCP5_DCP_DEBUG__VI                            0x448D
#define mmDCP5_DCP_DEBUG2__VI                           0x4498
#define mmDCP5_DCP_FP_CONVERTED_FIELD__VI               0x4465
#define mmDCP5_DCP_GSL_CONTROL__VI                      0x4490
#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI        0x4491
#define mmDCP5_DCP_RANDOM_SEEDS__VI                     0x4461
#define mmDCP5_DCP_SPATIAL_DITHER_CNTL__VI              0x4460
#define mmDCP5_DCP_TEST_DEBUG_DATA__VI                  0x4496
#define mmDCP5_DCP_TEST_DEBUG_INDEX__VI                 0x4495
#define mmDCP5_DC_LUT_30_COLOR__VI                      0x447C
#define mmDCP5_DC_LUT_AUTOFILL__VI                      0x447F
#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE__VI             0x4481
#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN__VI            0x4482
#define mmDCP5_DC_LUT_BLACK_OFFSET_RED__VI              0x4483
#define mmDCP5_DC_LUT_CONTROL__VI                       0x4480
#define mmDCP5_DC_LUT_PWL_DATA__VI                      0x447B
#define mmDCP5_DC_LUT_RW_INDEX__VI                      0x4479
#define mmDCP5_DC_LUT_RW_MODE__VI                       0x4478
#define mmDCP5_DC_LUT_SEQ_COLOR__VI                     0x447A
#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE__VI             0x447D
#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE__VI             0x4484
#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN__VI            0x4485
#define mmDCP5_DC_LUT_WHITE_OFFSET_RED__VI              0x4486
#define mmDCP5_DC_LUT_WRITE_EN_MASK__VI                 0x447E
#define mmDCP5_DEGAMMA_CONTROL__VI                      0x4458
#define mmDCP5_DENORM_CONTROL__VI                       0x4450
#define mmDCP5_GAMUT_REMAP_C11_C12__VI                  0x445A
#define mmDCP5_GAMUT_REMAP_C13_C14__VI                  0x445B
#define mmDCP5_GAMUT_REMAP_C21_C22__VI                  0x445C
#define mmDCP5_GAMUT_REMAP_C23_C24__VI                  0x445D
#define mmDCP5_GAMUT_REMAP_C31_C32__VI                  0x445E
#define mmDCP5_GAMUT_REMAP_C33_C34__VI                  0x445F
#define mmDCP5_GAMUT_REMAP_CONTROL__VI                  0x4459
#define mmDCP5_GRPH_COMPRESS_PITCH__VI                  0x441A
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS__VI        0x4419
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI   0x441B
#define mmDCP5_GRPH_CONTROL__SI__CI                     0x4901
#define mmDCP5_GRPH_CONTROL__VI                         0x4401
#define mmDCP5_GRPH_DFQ_CONTROL__VI                     0x4414
#define mmDCP5_GRPH_DFQ_STATUS__VI                      0x4415
#define mmDCP5_GRPH_ENABLE__VI                          0x4400
#define mmDCP5_GRPH_FLIP_CONTROL__SI__CI                0x4912
#define mmDCP5_GRPH_FLIP_CONTROL__VI                    0x4412
#define mmDCP5_GRPH_FLIP_RATE_CNTL__VI                  0x448E
#define mmDCP5_GRPH_INTERRUPT_CONTROL__VI               0x4417
#define mmDCP5_GRPH_INTERRUPT_STATUS__VI                0x4416
#define mmDCP5_GRPH_LUT_10BIT_BYPASS__VI                0x4402
#define mmDCP5_GRPH_PITCH__SI__CI                       0x4906
#define mmDCP5_GRPH_PITCH__VI                           0x4406
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI     0x4904
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS__VI         0x4404
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI    0x4407
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS__VI       0x4405
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI  0x4408
#define mmDCP5_GRPH_STEREOSYNC_FLIP__VI                 0x4497
#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI      0x4418
#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE__VI           0x4413
#define mmDCP5_GRPH_SURFACE_OFFSET_X__VI                0x4409
#define mmDCP5_GRPH_SURFACE_OFFSET_Y__VI                0x440A
#define mmDCP5_GRPH_SWAP_CNTL__VI                       0x4403
#define mmDCP5_GRPH_UPDATE__SI__CI                      0x4911
#define mmDCP5_GRPH_UPDATE__VI                          0x4411
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI   0x449F
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI 0x44BF
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI   0x44BD
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI 0x44BE
#define mmDCP5_GRPH_X_END__VI                           0x440D
#define mmDCP5_GRPH_X_START__VI                         0x440B
#define mmDCP5_GRPH_Y_END__VI                           0x440E
#define mmDCP5_GRPH_Y_START__VI                         0x440C
#define mmDCP5_HW_ROTATION__VI                          0x449E
#define mmDCP5_INPUT_CSC_C11_C12__VI                    0x4436
#define mmDCP5_INPUT_CSC_C13_C14__VI                    0x4437
#define mmDCP5_INPUT_CSC_C21_C22__VI                    0x4438
#define mmDCP5_INPUT_CSC_C23_C24__VI                    0x4439
#define mmDCP5_INPUT_CSC_C31_C32__VI                    0x443A
#define mmDCP5_INPUT_CSC_C33_C34__VI                    0x443B
#define mmDCP5_INPUT_CSC_CONTROL__VI                    0x4435
#define mmDCP5_INPUT_GAMMA_CONTROL__VI                  0x4410
#define mmDCP5_KEY_CONTROL__VI                          0x4453
#define mmDCP5_KEY_RANGE_ALPHA__VI                      0x4454
#define mmDCP5_KEY_RANGE_BLUE__VI                       0x4457
#define mmDCP5_KEY_RANGE_GREEN__VI                      0x4456
#define mmDCP5_KEY_RANGE_RED__VI                        0x4455
#define mmDCP5_OUTPUT_CSC_C11_C12__VI                   0x443D
#define mmDCP5_OUTPUT_CSC_C13_C14__VI                   0x443E
#define mmDCP5_OUTPUT_CSC_C21_C22__VI                   0x443F
#define mmDCP5_OUTPUT_CSC_C23_C24__VI                   0x4440
#define mmDCP5_OUTPUT_CSC_C31_C32__VI                   0x4441
#define mmDCP5_OUTPUT_CSC_C33_C34__VI                   0x4442
#define mmDCP5_OUTPUT_CSC_CONTROL__VI                   0x443C
#define mmDCP5_OUT_CLAMP_CONTROL_B_CB__VI               0x449D
#define mmDCP5_OUT_CLAMP_CONTROL_G_Y__VI                0x449C
#define mmDCP5_OUT_CLAMP_CONTROL_R_CR__VI               0x4452
#define mmDCP5_OUT_ROUND_CONTROL__VI                    0x4451
#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL__VI               0x442C
#define mmDCP5_OVL_CONTROL1__VI                         0x441D
#define mmDCP5_OVL_CONTROL2__VI                         0x441E
#define mmDCP5_OVL_DFQ_CONTROL__VI                      0x4429
#define mmDCP5_OVL_DFQ_STATUS__VI                       0x442A
#define mmDCP5_OVL_ENABLE__VI                           0x441C
#define mmDCP5_OVL_END__VI                              0x4426
#define mmDCP5_OVL_PITCH__VI                            0x4421
#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS__VI        0x4492
#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI   0x4494
#define mmDCP5_OVL_START__VI                            0x4425
#define mmDCP5_OVL_STEREOSYNC_FLIP__VI                  0x4493
#define mmDCP5_OVL_SURFACE_ADDRESS__SI__CI              0x4920
#define mmDCP5_OVL_SURFACE_ADDRESS__VI                  0x4420
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH__VI             0x4422
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI       0x442B
#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE__VI            0x4428
#define mmDCP5_OVL_SURFACE_OFFSET_X__VI                 0x4423
#define mmDCP5_OVL_SURFACE_OFFSET_Y__VI                 0x4424
#define mmDCP5_OVL_SWAP_CNTL__VI                        0x441F
#define mmDCP5_OVL_UPDATE__VI                           0x4427
#define mmDCP5_PRESCALE_GRPH_CONTROL__VI                0x442D
#define mmDCP5_PRESCALE_OVL_CONTROL__VI                 0x4431
#define mmDCP5_PRESCALE_VALUES_GRPH_B__VI               0x4430
#define mmDCP5_PRESCALE_VALUES_GRPH_G__VI               0x442F
#define mmDCP5_PRESCALE_VALUES_GRPH_R__VI               0x442E
#define mmDCP5_PRESCALE_VALUES_OVL_CB__VI               0x4432
#define mmDCP5_PRESCALE_VALUES_OVL_CR__VI               0x4434
#define mmDCP5_PRESCALE_VALUES_OVL_Y__VI                0x4433
#define mmDCP5_REGAMMA_CNTLA_END_CNTL1__VI              0x44A6
#define mmDCP5_REGAMMA_CNTLA_END_CNTL2__VI              0x44A7
#define mmDCP5_REGAMMA_CNTLA_REGION_0_1__VI             0x44A8
#define mmDCP5_REGAMMA_CNTLA_REGION_10_11__VI           0x44AD
#define mmDCP5_REGAMMA_CNTLA_REGION_12_13__VI           0x44AE
#define mmDCP5_REGAMMA_CNTLA_REGION_14_15__VI           0x44AF
#define mmDCP5_REGAMMA_CNTLA_REGION_2_3__VI             0x44A9
#define mmDCP5_REGAMMA_CNTLA_REGION_4_5__VI             0x44AA
#define mmDCP5_REGAMMA_CNTLA_REGION_6_7__VI             0x44AB
#define mmDCP5_REGAMMA_CNTLA_REGION_8_9__VI             0x44AC
#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL__VI             0x44A5
#define mmDCP5_REGAMMA_CNTLA_START_CNTL__VI             0x44A4
#define mmDCP5_REGAMMA_CNTLB_END_CNTL1__VI              0x44B2
#define mmDCP5_REGAMMA_CNTLB_END_CNTL2__VI              0x44B3
#define mmDCP5_REGAMMA_CNTLB_REGION_0_1__VI             0x44B4
#define mmDCP5_REGAMMA_CNTLB_REGION_10_11__VI           0x44B9
#define mmDCP5_REGAMMA_CNTLB_REGION_12_13__VI           0x44BA
#define mmDCP5_REGAMMA_CNTLB_REGION_14_15__VI           0x44BB
#define mmDCP5_REGAMMA_CNTLB_REGION_2_3__VI             0x44B5
#define mmDCP5_REGAMMA_CNTLB_REGION_4_5__VI             0x44B6
#define mmDCP5_REGAMMA_CNTLB_REGION_6_7__VI             0x44B7
#define mmDCP5_REGAMMA_CNTLB_REGION_8_9__VI             0x44B8
#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL__VI             0x44B1
#define mmDCP5_REGAMMA_CNTLB_START_CNTL__VI             0x44B0
#define mmDCP5_REGAMMA_CONTROL__VI                      0x44A0
#define mmDCP5_REGAMMA_LUT_DATA__VI                     0x44A2
#define mmDCP5_REGAMMA_LUT_INDEX__VI                    0x44A1
#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK__VI            0x44A3
#define mmDCPG_TEST_DEBUG_DATA__VI                      0x02D7
#define mmDCPG_TEST_DEBUG_INDEX__VI                     0x02D6
#define mmDCP_DEBUG2__VI                                0x1A98
#define mmDCP_FP_CONVERTED_FIELD__VI                    0x1A65
#define mmDCP_GSL_CONTROL__VI                           0x1A90
#define mmDCP_RANDOM_SEEDS__VI                          0x1A61
#define mmDCP_SPATIAL_DITHER_CNTL__VI                   0x1A60
#define mmDCRX_PHY_MACRO_CNTL_RESERVED0__VI             0x5A84
#define mmDCRX_PHY_MACRO_CNTL_RESERVED1__VI             0x5A85
#define mmDCRX_PHY_MACRO_CNTL_RESERVED10__VI            0x5A8E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED100__VI           0x5AE8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED101__VI           0x5AE9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED102__VI           0x5AEA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED103__VI           0x5AEB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED104__VI           0x5AEC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED105__VI           0x5AED
#define mmDCRX_PHY_MACRO_CNTL_RESERVED106__VI           0x5AEE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED107__VI           0x5AEF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED108__VI           0x5AF0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED109__VI           0x5AF1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED11__VI            0x5A8F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED110__VI           0x5AF2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED111__VI           0x5AF3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED112__VI           0x5AF4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED113__VI           0x5AF5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED114__VI           0x5AF6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED115__VI           0x5AF7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED116__VI           0x5AF8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED117__VI           0x5AF9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED118__VI           0x5AFA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED119__VI           0x5AFB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED12__VI            0x5A90
#define mmDCRX_PHY_MACRO_CNTL_RESERVED120__VI           0x5AFC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED121__VI           0x5AFD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED122__VI           0x5AFE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED123__VI           0x5AFF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED124__VI           0x5B00
#define mmDCRX_PHY_MACRO_CNTL_RESERVED125__VI           0x5B01
#define mmDCRX_PHY_MACRO_CNTL_RESERVED126__VI           0x5B02
#define mmDCRX_PHY_MACRO_CNTL_RESERVED127__VI           0x5B03
#define mmDCRX_PHY_MACRO_CNTL_RESERVED128__VI           0x5B04
#define mmDCRX_PHY_MACRO_CNTL_RESERVED129__VI           0x5B05
#define mmDCRX_PHY_MACRO_CNTL_RESERVED13__VI            0x5A91
#define mmDCRX_PHY_MACRO_CNTL_RESERVED130__VI           0x5B06
#define mmDCRX_PHY_MACRO_CNTL_RESERVED131__VI           0x5B07
#define mmDCRX_PHY_MACRO_CNTL_RESERVED132__VI           0x5B08
#define mmDCRX_PHY_MACRO_CNTL_RESERVED133__VI           0x5B09
#define mmDCRX_PHY_MACRO_CNTL_RESERVED134__VI           0x5B0A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED135__VI           0x5B0B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED136__VI           0x5B0C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED137__VI           0x5B0D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED138__VI           0x5B0E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED139__VI           0x5B0F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED14__VI            0x5A92
#define mmDCRX_PHY_MACRO_CNTL_RESERVED140__VI           0x5B10
#define mmDCRX_PHY_MACRO_CNTL_RESERVED141__VI           0x5B11
#define mmDCRX_PHY_MACRO_CNTL_RESERVED142__VI           0x5B12
#define mmDCRX_PHY_MACRO_CNTL_RESERVED143__VI           0x5B13
#define mmDCRX_PHY_MACRO_CNTL_RESERVED144__VI           0x5B14
#define mmDCRX_PHY_MACRO_CNTL_RESERVED145__VI           0x5B15
#define mmDCRX_PHY_MACRO_CNTL_RESERVED146__VI           0x5B16
#define mmDCRX_PHY_MACRO_CNTL_RESERVED147__VI           0x5B17
#define mmDCRX_PHY_MACRO_CNTL_RESERVED148__VI           0x5B18
#define mmDCRX_PHY_MACRO_CNTL_RESERVED149__VI           0x5B19
#define mmDCRX_PHY_MACRO_CNTL_RESERVED15__VI            0x5A93
#define mmDCRX_PHY_MACRO_CNTL_RESERVED150__VI           0x5B1A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED151__VI           0x5B1B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED152__VI           0x5B1C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED153__VI           0x5B1D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED154__VI           0x5B1E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED155__VI           0x5B1F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED156__VI           0x5B20
#define mmDCRX_PHY_MACRO_CNTL_RESERVED157__VI           0x5B21
#define mmDCRX_PHY_MACRO_CNTL_RESERVED158__VI           0x5B22
#define mmDCRX_PHY_MACRO_CNTL_RESERVED159__VI           0x5B23
#define mmDCRX_PHY_MACRO_CNTL_RESERVED16__VI            0x5A94
#define mmDCRX_PHY_MACRO_CNTL_RESERVED160__VI           0x5B24
#define mmDCRX_PHY_MACRO_CNTL_RESERVED161__VI           0x5B25
#define mmDCRX_PHY_MACRO_CNTL_RESERVED162__VI           0x5B26
#define mmDCRX_PHY_MACRO_CNTL_RESERVED163__VI           0x5B27
#define mmDCRX_PHY_MACRO_CNTL_RESERVED164__VI           0x5B28
#define mmDCRX_PHY_MACRO_CNTL_RESERVED165__VI           0x5B29
#define mmDCRX_PHY_MACRO_CNTL_RESERVED166__VI           0x5B2A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED167__VI           0x5B2B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED168__VI           0x5B2C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED169__VI           0x5B2D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED17__VI            0x5A95
#define mmDCRX_PHY_MACRO_CNTL_RESERVED170__VI           0x5B2E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED171__VI           0x5B2F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED172__VI           0x5B30
#define mmDCRX_PHY_MACRO_CNTL_RESERVED173__VI           0x5B31
#define mmDCRX_PHY_MACRO_CNTL_RESERVED174__VI           0x5B32
#define mmDCRX_PHY_MACRO_CNTL_RESERVED175__VI           0x5B33
#define mmDCRX_PHY_MACRO_CNTL_RESERVED176__VI           0x5B34
#define mmDCRX_PHY_MACRO_CNTL_RESERVED177__VI           0x5B35
#define mmDCRX_PHY_MACRO_CNTL_RESERVED178__VI           0x5B36
#define mmDCRX_PHY_MACRO_CNTL_RESERVED179__VI           0x5B37
#define mmDCRX_PHY_MACRO_CNTL_RESERVED18__VI            0x5A96
#define mmDCRX_PHY_MACRO_CNTL_RESERVED180__VI           0x5B38
#define mmDCRX_PHY_MACRO_CNTL_RESERVED181__VI           0x5B39
#define mmDCRX_PHY_MACRO_CNTL_RESERVED182__VI           0x5B3A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED183__VI           0x5B3B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED184__VI           0x5B3C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED185__VI           0x5B3D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED186__VI           0x5B3E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED187__VI           0x5B3F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED188__VI           0x5B40
#define mmDCRX_PHY_MACRO_CNTL_RESERVED189__VI           0x5B41
#define mmDCRX_PHY_MACRO_CNTL_RESERVED19__VI            0x5A97
#define mmDCRX_PHY_MACRO_CNTL_RESERVED190__VI           0x5B42
#define mmDCRX_PHY_MACRO_CNTL_RESERVED191__VI           0x5B43
#define mmDCRX_PHY_MACRO_CNTL_RESERVED192__VI           0x5B44
#define mmDCRX_PHY_MACRO_CNTL_RESERVED193__VI           0x5B45
#define mmDCRX_PHY_MACRO_CNTL_RESERVED194__VI           0x5B46
#define mmDCRX_PHY_MACRO_CNTL_RESERVED195__VI           0x5B47
#define mmDCRX_PHY_MACRO_CNTL_RESERVED196__VI           0x5B48
#define mmDCRX_PHY_MACRO_CNTL_RESERVED197__VI           0x5B49
#define mmDCRX_PHY_MACRO_CNTL_RESERVED198__VI           0x5B4A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED199__VI           0x5B4B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED2__VI             0x5A86
#define mmDCRX_PHY_MACRO_CNTL_RESERVED20__VI            0x5A98
#define mmDCRX_PHY_MACRO_CNTL_RESERVED200__VI           0x5B4C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED201__VI           0x5B4D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED202__VI           0x5B4E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED203__VI           0x5B4F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED204__VI           0x5B50
#define mmDCRX_PHY_MACRO_CNTL_RESERVED205__VI           0x5B51
#define mmDCRX_PHY_MACRO_CNTL_RESERVED206__VI           0x5B52
#define mmDCRX_PHY_MACRO_CNTL_RESERVED207__VI           0x5B53
#define mmDCRX_PHY_MACRO_CNTL_RESERVED208__VI           0x5B54
#define mmDCRX_PHY_MACRO_CNTL_RESERVED209__VI           0x5B55
#define mmDCRX_PHY_MACRO_CNTL_RESERVED21__VI            0x5A99
#define mmDCRX_PHY_MACRO_CNTL_RESERVED210__VI           0x5B56
#define mmDCRX_PHY_MACRO_CNTL_RESERVED211__VI           0x5B57
#define mmDCRX_PHY_MACRO_CNTL_RESERVED212__VI           0x5B58
#define mmDCRX_PHY_MACRO_CNTL_RESERVED213__VI           0x5B59
#define mmDCRX_PHY_MACRO_CNTL_RESERVED214__VI           0x5B5A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED215__VI           0x5B5B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED216__VI           0x5B5C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED217__VI           0x5B5D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED218__VI           0x5B5E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED219__VI           0x5B5F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED22__VI            0x5A9A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED220__VI           0x5B60
#define mmDCRX_PHY_MACRO_CNTL_RESERVED221__VI           0x5B61
#define mmDCRX_PHY_MACRO_CNTL_RESERVED222__VI           0x5B62
#define mmDCRX_PHY_MACRO_CNTL_RESERVED223__VI           0x5B63
#define mmDCRX_PHY_MACRO_CNTL_RESERVED224__VI           0x5B64
#define mmDCRX_PHY_MACRO_CNTL_RESERVED225__VI           0x5B65
#define mmDCRX_PHY_MACRO_CNTL_RESERVED226__VI           0x5B66
#define mmDCRX_PHY_MACRO_CNTL_RESERVED227__VI           0x5B67
#define mmDCRX_PHY_MACRO_CNTL_RESERVED228__VI           0x5B68
#define mmDCRX_PHY_MACRO_CNTL_RESERVED229__VI           0x5B69
#define mmDCRX_PHY_MACRO_CNTL_RESERVED23__VI            0x5A9B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED230__VI           0x5B6A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED231__VI           0x5B6B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED232__VI           0x5B6C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED233__VI           0x5B6D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED234__VI           0x5B6E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED235__VI           0x5B6F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED236__VI           0x5B70
#define mmDCRX_PHY_MACRO_CNTL_RESERVED237__VI           0x5B71
#define mmDCRX_PHY_MACRO_CNTL_RESERVED238__VI           0x5B72
#define mmDCRX_PHY_MACRO_CNTL_RESERVED239__VI           0x5B73
#define mmDCRX_PHY_MACRO_CNTL_RESERVED24__VI            0x5A9C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED240__VI           0x5B74
#define mmDCRX_PHY_MACRO_CNTL_RESERVED241__VI           0x5B75
#define mmDCRX_PHY_MACRO_CNTL_RESERVED242__VI           0x5B76
#define mmDCRX_PHY_MACRO_CNTL_RESERVED243__VI           0x5B77
#define mmDCRX_PHY_MACRO_CNTL_RESERVED244__VI           0x5B78
#define mmDCRX_PHY_MACRO_CNTL_RESERVED245__VI           0x5B79
#define mmDCRX_PHY_MACRO_CNTL_RESERVED246__VI           0x5B7A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED247__VI           0x5B7B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED248__VI           0x5B7C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED249__VI           0x5B7D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED25__VI            0x5A9D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED250__VI           0x5B7E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED251__VI           0x5B7F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED252__VI           0x5B80
#define mmDCRX_PHY_MACRO_CNTL_RESERVED253__VI           0x5B81
#define mmDCRX_PHY_MACRO_CNTL_RESERVED254__VI           0x5B82
#define mmDCRX_PHY_MACRO_CNTL_RESERVED255__VI           0x5B83
#define mmDCRX_PHY_MACRO_CNTL_RESERVED256__VI           0x5B84
#define mmDCRX_PHY_MACRO_CNTL_RESERVED257__VI           0x5B85
#define mmDCRX_PHY_MACRO_CNTL_RESERVED258__VI           0x5B86
#define mmDCRX_PHY_MACRO_CNTL_RESERVED259__VI           0x5B87
#define mmDCRX_PHY_MACRO_CNTL_RESERVED26__VI            0x5A9E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED260__VI           0x5B88
#define mmDCRX_PHY_MACRO_CNTL_RESERVED261__VI           0x5B89
#define mmDCRX_PHY_MACRO_CNTL_RESERVED262__VI           0x5B8A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED263__VI           0x5B8B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED264__VI           0x5B8C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED265__VI           0x5B8D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED266__VI           0x5B8E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED267__VI           0x5B8F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED268__VI           0x5B90
#define mmDCRX_PHY_MACRO_CNTL_RESERVED269__VI           0x5B91
#define mmDCRX_PHY_MACRO_CNTL_RESERVED27__VI            0x5A9F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED270__VI           0x5B92
#define mmDCRX_PHY_MACRO_CNTL_RESERVED271__VI           0x5B93
#define mmDCRX_PHY_MACRO_CNTL_RESERVED272__VI           0x5B94
#define mmDCRX_PHY_MACRO_CNTL_RESERVED273__VI           0x5B95
#define mmDCRX_PHY_MACRO_CNTL_RESERVED274__VI           0x5B96
#define mmDCRX_PHY_MACRO_CNTL_RESERVED275__VI           0x5B97
#define mmDCRX_PHY_MACRO_CNTL_RESERVED276__VI           0x5B98
#define mmDCRX_PHY_MACRO_CNTL_RESERVED277__VI           0x5B99
#define mmDCRX_PHY_MACRO_CNTL_RESERVED278__VI           0x5B9A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED279__VI           0x5B9B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED28__VI            0x5AA0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED280__VI           0x5B9C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED281__VI           0x5B9D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED282__VI           0x5B9E
#define mmDCRX_PHY_MACRO_CNTL_RESERVED283__VI           0x5B9F
#define mmDCRX_PHY_MACRO_CNTL_RESERVED284__VI           0x5BA0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED285__VI           0x5BA1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED286__VI           0x5BA2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED287__VI           0x5BA3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED288__VI           0x5BA4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED289__VI           0x5BA5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED29__VI            0x5AA1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED290__VI           0x5BA6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED291__VI           0x5BA7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED292__VI           0x5BA8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED293__VI           0x5BA9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED294__VI           0x5BAA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED295__VI           0x5BAB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED296__VI           0x5BAC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED297__VI           0x5BAD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED298__VI           0x5BAE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED299__VI           0x5BAF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED3__VI             0x5A87
#define mmDCRX_PHY_MACRO_CNTL_RESERVED30__VI            0x5AA2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED300__VI           0x5BB0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED301__VI           0x5BB1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED302__VI           0x5BB2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED303__VI           0x5BB3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED304__VI           0x5BB4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED305__VI           0x5BB5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED306__VI           0x5BB6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED307__VI           0x5BB7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED308__VI           0x5BB8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED309__VI           0x5BB9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED31__VI            0x5AA3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED310__VI           0x5BBA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED311__VI           0x5BBB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED312__VI           0x5BBC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED313__VI           0x5BBD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED314__VI           0x5BBE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED315__VI           0x5BBF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED316__VI           0x5BC0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED317__VI           0x5BC1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED318__VI           0x5BC2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED319__VI           0x5BC3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED32__VI            0x5AA4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED320__VI           0x5BC4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED321__VI           0x5BC5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED322__VI           0x5BC6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED323__VI           0x5BC7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED324__VI           0x5BC8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED325__VI           0x5BC9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED326__VI           0x5BCA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED327__VI           0x5BCB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED328__VI           0x5BCC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED329__VI           0x5BCD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED33__VI            0x5AA5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED330__VI           0x5BCE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED331__VI           0x5BCF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED332__VI           0x5BD0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED333__VI           0x5BD1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED334__VI           0x5BD2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED335__VI           0x5BD3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED336__VI           0x5BD4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED337__VI           0x5BD5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED338__VI           0x5BD6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED339__VI           0x5BD7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED34__VI            0x5AA6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED340__VI           0x5BD8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED341__VI           0x5BD9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED342__VI           0x5BDA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED343__VI           0x5BDB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED344__VI           0x5BDC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED345__VI           0x5BDD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED346__VI           0x5BDE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED347__VI           0x5BDF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED348__VI           0x5BE0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED349__VI           0x5BE1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED35__VI            0x5AA7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED350__VI           0x5BE2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED351__VI           0x5BE3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED352__VI           0x5BE4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED353__VI           0x5BE5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED354__VI           0x5BE6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED355__VI           0x5BE7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED356__VI           0x5BE8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED357__VI           0x5BE9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED358__VI           0x5BEA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED359__VI           0x5BEB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED36__VI            0x5AA8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED360__VI           0x5BEC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED361__VI           0x5BED
#define mmDCRX_PHY_MACRO_CNTL_RESERVED362__VI           0x5BEE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED363__VI           0x5BEF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED364__VI           0x5BF0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED365__VI           0x5BF1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED366__VI           0x5BF2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED367__VI           0x5BF3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED368__VI           0x5BF4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED369__VI           0x5BF5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED37__VI            0x5AA9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED370__VI           0x5BF6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED371__VI           0x5BF7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED372__VI           0x5BF8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED373__VI           0x5BF9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED374__VI           0x5BFA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED375__VI           0x5BFB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED376__VI           0x5BFC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED377__VI           0x5BFD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED378__VI           0x5BFE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED379__VI           0x5BFF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED38__VI            0x5AAA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED39__VI            0x5AAB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED4__VI             0x5A88
#define mmDCRX_PHY_MACRO_CNTL_RESERVED40__VI            0x5AAC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED41__VI            0x5AAD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED42__VI            0x5AAE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED43__VI            0x5AAF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED44__VI            0x5AB0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED45__VI            0x5AB1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED46__VI            0x5AB2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED47__VI            0x5AB3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED48__VI            0x5AB4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED49__VI            0x5AB5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED5__VI             0x5A89
#define mmDCRX_PHY_MACRO_CNTL_RESERVED50__VI            0x5AB6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED51__VI            0x5AB7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED52__VI            0x5AB8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED53__VI            0x5AB9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED54__VI            0x5ABA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED55__VI            0x5ABB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED56__VI            0x5ABC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED57__VI            0x5ABD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED58__VI            0x5ABE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED59__VI            0x5ABF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED6__VI             0x5A8A
#define mmDCRX_PHY_MACRO_CNTL_RESERVED60__VI            0x5AC0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED61__VI            0x5AC1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED62__VI            0x5AC2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED63__VI            0x5AC3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED64__VI            0x5AC4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED65__VI            0x5AC5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED66__VI            0x5AC6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED67__VI            0x5AC7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED68__VI            0x5AC8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED69__VI            0x5AC9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED7__VI             0x5A8B
#define mmDCRX_PHY_MACRO_CNTL_RESERVED70__VI            0x5ACA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED71__VI            0x5ACB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED72__VI            0x5ACC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED73__VI            0x5ACD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED74__VI            0x5ACE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED75__VI            0x5ACF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED76__VI            0x5AD0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED77__VI            0x5AD1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED78__VI            0x5AD2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED79__VI            0x5AD3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED8__VI             0x5A8C
#define mmDCRX_PHY_MACRO_CNTL_RESERVED80__VI            0x5AD4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED81__VI            0x5AD5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED82__VI            0x5AD6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED83__VI            0x5AD7
#define mmDCRX_PHY_MACRO_CNTL_RESERVED84__VI            0x5AD8
#define mmDCRX_PHY_MACRO_CNTL_RESERVED85__VI            0x5AD9
#define mmDCRX_PHY_MACRO_CNTL_RESERVED86__VI            0x5ADA
#define mmDCRX_PHY_MACRO_CNTL_RESERVED87__VI            0x5ADB
#define mmDCRX_PHY_MACRO_CNTL_RESERVED88__VI            0x5ADC
#define mmDCRX_PHY_MACRO_CNTL_RESERVED89__VI            0x5ADD
#define mmDCRX_PHY_MACRO_CNTL_RESERVED9__VI             0x5A8D
#define mmDCRX_PHY_MACRO_CNTL_RESERVED90__VI            0x5ADE
#define mmDCRX_PHY_MACRO_CNTL_RESERVED91__VI            0x5ADF
#define mmDCRX_PHY_MACRO_CNTL_RESERVED92__VI            0x5AE0
#define mmDCRX_PHY_MACRO_CNTL_RESERVED93__VI            0x5AE1
#define mmDCRX_PHY_MACRO_CNTL_RESERVED94__VI            0x5AE2
#define mmDCRX_PHY_MACRO_CNTL_RESERVED95__VI            0x5AE3
#define mmDCRX_PHY_MACRO_CNTL_RESERVED96__VI            0x5AE4
#define mmDCRX_PHY_MACRO_CNTL_RESERVED97__VI            0x5AE5
#define mmDCRX_PHY_MACRO_CNTL_RESERVED98__VI            0x5AE6
#define mmDCRX_PHY_MACRO_CNTL_RESERVED99__VI            0x5AE7
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE__VI              0x169B
#define mmDC_DVODATA_CONFIG__VI                         0x481A
#define mmDC_GENERICA__VI                               0x4800
#define mmDC_GENERICB__VI                               0x4801
#define mmDC_GPIO_DDC1_A__VI                            0x4869
#define mmDC_GPIO_DDC1_EN__VI                           0x486A
#define mmDC_GPIO_DDC1_MASK__VI                         0x4868
#define mmDC_GPIO_DDC1_Y__VI                            0x486B
#define mmDC_GPIO_DDC2_A__VI                            0x486D
#define mmDC_GPIO_DDC2_EN__VI                           0x486E
#define mmDC_GPIO_DDC2_MASK__VI                         0x486C
#define mmDC_GPIO_DDC2_Y__VI                            0x486F
#define mmDC_GPIO_DDC3_A__VI                            0x4871
#define mmDC_GPIO_DDC3_EN__VI                           0x4872
#define mmDC_GPIO_DDC3_MASK__VI                         0x4870
#define mmDC_GPIO_DDC3_Y__VI                            0x4873
#define mmDC_GPIO_DDC4_A__VI                            0x4875
#define mmDC_GPIO_DDC4_EN__VI                           0x4876
#define mmDC_GPIO_DDC4_MASK__VI                         0x4874
#define mmDC_GPIO_DDC4_Y__VI                            0x4877
#define mmDC_GPIO_DDC5_A__VI                            0x4879
#define mmDC_GPIO_DDC5_EN__VI                           0x487A
#define mmDC_GPIO_DDC5_MASK__VI                         0x4878
#define mmDC_GPIO_DDC5_Y__VI                            0x487B
#define mmDC_GPIO_DDC6_A__VI                            0x487D
#define mmDC_GPIO_DDC6_EN__VI                           0x487E
#define mmDC_GPIO_DDC6_MASK__VI                         0x487C
#define mmDC_GPIO_DDC6_Y__VI                            0x487F
#define mmDC_GPIO_DDCVGA_A__VI                          0x4881
#define mmDC_GPIO_DDCVGA_EN__VI                         0x4882
#define mmDC_GPIO_DDCVGA_MASK__VI                       0x4880
#define mmDC_GPIO_DDCVGA_Y__VI                          0x4883
#define mmDC_GPIO_DEBUG__VI                             0x4804
#define mmDC_GPIO_DVODATA_A__VI                         0x4865
#define mmDC_GPIO_DVODATA_EN__VI                        0x4866
#define mmDC_GPIO_DVODATA_MASK__VI                      0x4864
#define mmDC_GPIO_DVODATA_Y__VI                         0x4867
#define mmDC_GPIO_GENERIC_A__VI                         0x4861
#define mmDC_GPIO_GENERIC_EN__VI                        0x4862
#define mmDC_GPIO_GENERIC_MASK__VI                      0x4860
#define mmDC_GPIO_GENERIC_Y__VI                         0x4863
#define mmDC_GPIO_GENLK_A__VI                           0x4889
#define mmDC_GPIO_GENLK_EN__VI                          0x488A
#define mmDC_GPIO_GENLK_MASK__VI                        0x4888
#define mmDC_GPIO_GENLK_Y__VI                           0x488B
#define mmDC_GPIO_HPD_A__VI                             0x488D
#define mmDC_GPIO_HPD_EN__VI                            0x488E
#define mmDC_GPIO_HPD_MASK__VI                          0x488C
#define mmDC_GPIO_HPD_Y__VI                             0x488F
#define mmDC_GPIO_I2CPAD_A__VI                          0x4899
#define mmDC_GPIO_I2CPAD_EN__VI                         0x489A
#define mmDC_GPIO_I2CPAD_MASK__VI                       0x4898
#define mmDC_GPIO_I2CPAD_STRENGTH__VI                   0x489C
#define mmDC_GPIO_I2CPAD_Y__VI                          0x489B
#define mmDC_GPIO_PAD_STRENGTH_1__VI                    0x4894
#define mmDC_GPIO_PAD_STRENGTH_2__VI                    0x4895
#define mmDC_GPIO_PWRSEQ_A__VI                          0x4891
#define mmDC_GPIO_PWRSEQ_EN__VI                         0x4892
#define mmDC_GPIO_PWRSEQ_MASK__VI                       0x4890
#define mmDC_GPIO_PWRSEQ_Y__VI                          0x4893
#define mmDC_GPIO_SYNCA_A__VI                           0x4885
#define mmDC_GPIO_SYNCA_EN__VI                          0x4886
#define mmDC_GPIO_SYNCA_MASK__VI                        0x4884
#define mmDC_GPIO_SYNCA_Y__VI                           0x4887
#define mmDC_GPU_TIMER_READ__VI                         0x482B
#define mmDC_GPU_TIMER_READ_CNTL__VI                    0x482C
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP__VI        0x482A
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE__VI      0x4829
#define mmDC_HPD_CONTROL__VI                            0x189A
#define mmDC_HPD_FAST_TRAIN_CNTL__VI                    0x189B
#define mmDC_HPD_INT_CONTROL__VI                        0x1899
#define mmDC_HPD_INT_STATUS__VI                         0x1898
#define mmDC_HPD_TOGGLE_FILT_CNTL__VI                   0x189C
#define mmDC_I2C_ARBITRATION__VI                        0x16D5
#define mmDC_I2C_CONTROL__VI                            0x16D4
#define mmDC_I2C_DATA__VI                               0x16EE
#define mmDC_I2C_DDC1_HW_STATUS__VI                     0x16D8
#define mmDC_I2C_DDC1_SETUP__VI                         0x16DF
#define mmDC_I2C_DDC1_SPEED__VI                         0x16DE
#define mmDC_I2C_DDC2_HW_STATUS__VI                     0x16D9
#define mmDC_I2C_DDC2_SETUP__VI                         0x16E1
#define mmDC_I2C_DDC2_SPEED__VI                         0x16E0
#define mmDC_I2C_DDC3_HW_STATUS__VI                     0x16DA
#define mmDC_I2C_DDC3_SETUP__VI                         0x16E3
#define mmDC_I2C_DDC3_SPEED__VI                         0x16E2
#define mmDC_I2C_DDC4_HW_STATUS__VI                     0x16DB
#define mmDC_I2C_DDC4_SETUP__VI                         0x16E5
#define mmDC_I2C_DDC4_SPEED__VI                         0x16E4
#define mmDC_I2C_DDC5_HW_STATUS__VI                     0x16DC
#define mmDC_I2C_DDC5_SETUP__VI                         0x16E7
#define mmDC_I2C_DDC5_SPEED__VI                         0x16E6
#define mmDC_I2C_DDC6_HW_STATUS__VI                     0x16DD
#define mmDC_I2C_DDC6_SETUP__VI                         0x16E9
#define mmDC_I2C_DDC6_SPEED__VI                         0x16E8
#define mmDC_I2C_DDCVGA_HW_STATUS__VI                   0x16EF
#define mmDC_I2C_DDCVGA_SETUP__VI                       0x16F1
#define mmDC_I2C_DDCVGA_SPEED__VI                       0x16F0
#define mmDC_I2C_EDID_DETECT_CTRL__VI                   0x16F2
#define mmDC_I2C_INTERRUPT_CONTROL__VI                  0x16D6
#define mmDC_I2C_SW_STATUS__VI                          0x16D7
#define mmDC_I2C_TRANSACTION0__VI                       0x16EA
#define mmDC_I2C_TRANSACTION1__VI                       0x16EB
#define mmDC_I2C_TRANSACTION2__VI                       0x16EC
#define mmDC_I2C_TRANSACTION3__VI                       0x16ED
#define mmDC_IP_REQUEST_CNTL__VI                        0x02D2
#define mmDC_LUT_VGA_ACCESS_ENABLE__VI                  0x1A7D
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL__VI                0x0132
#define mmDC_MVP_LB_CONTROL__VI                         0x1AE3
#define mmDC_PAD_EXTERN_SIG__VI                         0x4802
#define mmDC_PERFMON0_PERFCOUNTER_CNTL__VI              0x0170
#define mmDC_PERFMON0_PERFCOUNTER_STATE__VI             0x0171
#define mmDC_PERFMON0_PERFMON_CNTL__VI                  0x0173
#define mmDC_PERFMON0_PERFMON_CNTL2__VI                 0x017A
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC__VI       0x0172
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW__VI            0x0174
#define mmDC_PERFMON0_PERFMON_HI__VI                    0x0175
#define mmDC_PERFMON0_PERFMON_LOW__VI                   0x0176
#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA__VI       0x0178
#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX__VI      0x0177
#define mmDC_PERFMON10_PERFCOUNTER_CNTL__VI             0x59A0
#define mmDC_PERFMON10_PERFCOUNTER_STATE__VI            0x59A1
#define mmDC_PERFMON10_PERFMON_CNTL__VI                 0x59A3
#define mmDC_PERFMON10_PERFMON_CNTL2__VI                0x59AA
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC__VI      0x59A2
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW__VI           0x59A4
#define mmDC_PERFMON10_PERFMON_HI__VI                   0x59A5
#define mmDC_PERFMON10_PERFMON_LOW__VI                  0x59A6
#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA__VI      0x59A8
#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX__VI     0x59A7
#define mmDC_PERFMON11_PERFCOUNTER_CNTL__VI             0x4724
#define mmDC_PERFMON11_PERFCOUNTER_STATE__VI            0x4725
#define mmDC_PERFMON11_PERFMON_CNTL__VI                 0x4727
#define mmDC_PERFMON11_PERFMON_CNTL2__VI                0x472E
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC__VI      0x4726
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW__VI           0x4728
#define mmDC_PERFMON11_PERFMON_HI__VI                   0x4729
#define mmDC_PERFMON11_PERFMON_LOW__VI                  0x472A
#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA__VI      0x472C
#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX__VI     0x472B
#define mmDC_PERFMON1_PERFCOUNTER_CNTL__VI              0x0364
#define mmDC_PERFMON1_PERFCOUNTER_STATE__VI             0x0365
#define mmDC_PERFMON1_PERFMON_CNTL__VI                  0x0367
#define mmDC_PERFMON1_PERFMON_CNTL2__VI                 0x036E
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC__VI       0x0366
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW__VI            0x0368
#define mmDC_PERFMON1_PERFMON_HI__VI                    0x0369
#define mmDC_PERFMON1_PERFMON_LOW__VI                   0x036A
#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA__VI       0x036C
#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX__VI      0x036B
#define mmDC_PERFMON2_PERFCOUNTER_CNTL__VI              0x18C8
#define mmDC_PERFMON2_PERFCOUNTER_STATE__VI             0x18C9
#define mmDC_PERFMON2_PERFMON_CNTL__VI                  0x18CB
#define mmDC_PERFMON2_PERFMON_CNTL2__VI                 0x18D2
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC__VI       0x18CA
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW__VI            0x18CC
#define mmDC_PERFMON2_PERFMON_HI__VI                    0x18CD
#define mmDC_PERFMON2_PERFMON_LOW__VI                   0x18CE
#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA__VI       0x18D0
#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX__VI      0x18CF
#define mmDC_PERFMON3_PERFCOUNTER_CNTL__VI              0x1B24
#define mmDC_PERFMON3_PERFCOUNTER_STATE__VI             0x1B25
#define mmDC_PERFMON3_PERFMON_CNTL__VI                  0x1B27
#define mmDC_PERFMON3_PERFMON_CNTL2__VI                 0x1B2E
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC__VI       0x1B26
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW__VI            0x1B28
#define mmDC_PERFMON3_PERFMON_HI__VI                    0x1B29
#define mmDC_PERFMON3_PERFMON_LOW__VI                   0x1B2A
#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA__VI       0x1B2C
#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX__VI      0x1B2B
#define mmDC_PERFMON4_PERFCOUNTER_CNTL__VI              0x1D24
#define mmDC_PERFMON4_PERFCOUNTER_STATE__VI             0x1D25
#define mmDC_PERFMON4_PERFMON_CNTL__VI                  0x1D27
#define mmDC_PERFMON4_PERFMON_CNTL2__VI                 0x1D2E
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC__VI       0x1D26
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW__VI            0x1D28
#define mmDC_PERFMON4_PERFMON_HI__VI                    0x1D29
#define mmDC_PERFMON4_PERFMON_LOW__VI                   0x1D2A
#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA__VI       0x1D2C
#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX__VI      0x1D2B
#define mmDC_PERFMON5_PERFCOUNTER_CNTL__VI              0x1F24
#define mmDC_PERFMON5_PERFCOUNTER_STATE__VI             0x1F25
#define mmDC_PERFMON5_PERFMON_CNTL__VI                  0x1F27
#define mmDC_PERFMON5_PERFMON_CNTL2__VI                 0x1F2E
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC__VI       0x1F26
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW__VI            0x1F28
#define mmDC_PERFMON5_PERFMON_HI__VI                    0x1F29
#define mmDC_PERFMON5_PERFMON_LOW__VI                   0x1F2A
#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA__VI       0x1F2C
#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX__VI      0x1F2B
#define mmDC_PERFMON6_PERFCOUNTER_CNTL__VI              0x4124
#define mmDC_PERFMON6_PERFCOUNTER_STATE__VI             0x4125
#define mmDC_PERFMON6_PERFMON_CNTL__VI                  0x4127
#define mmDC_PERFMON6_PERFMON_CNTL2__VI                 0x412E
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC__VI       0x4126
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW__VI            0x4128
#define mmDC_PERFMON6_PERFMON_HI__VI                    0x4129
#define mmDC_PERFMON6_PERFMON_LOW__VI                   0x412A
#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA__VI       0x412C
#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX__VI      0x412B
#define mmDC_PERFMON7_PERFCOUNTER_CNTL__VI              0x4324
#define mmDC_PERFMON7_PERFCOUNTER_STATE__VI             0x4325
#define mmDC_PERFMON7_PERFMON_CNTL__VI                  0x4327
#define mmDC_PERFMON7_PERFMON_CNTL2__VI                 0x432E
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC__VI       0x4326
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW__VI            0x4328
#define mmDC_PERFMON7_PERFMON_HI__VI                    0x4329
#define mmDC_PERFMON7_PERFMON_LOW__VI                   0x432A
#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA__VI       0x432C
#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX__VI      0x432B
#define mmDC_PERFMON8_PERFCOUNTER_CNTL__VI              0x4524
#define mmDC_PERFMON8_PERFCOUNTER_STATE__VI             0x4525
#define mmDC_PERFMON8_PERFMON_CNTL__VI                  0x4527
#define mmDC_PERFMON8_PERFMON_CNTL2__VI                 0x452E
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC__VI       0x4526
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW__VI            0x4528
#define mmDC_PERFMON8_PERFMON_HI__VI                    0x4529
#define mmDC_PERFMON8_PERFMON_LOW__VI                   0x452A
#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA__VI       0x452C
#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX__VI      0x452B
#define mmDC_PERFMON9_PERFCOUNTER_CNTL__VI              0x5F68
#define mmDC_PERFMON9_PERFCOUNTER_STATE__VI             0x5F69
#define mmDC_PERFMON9_PERFMON_CNTL__VI                  0x5F6B
#define mmDC_PERFMON9_PERFMON_CNTL2__VI                 0x5F72
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC__VI       0x5F6A
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW__VI            0x5F6C
#define mmDC_PERFMON9_PERFMON_HI__VI                    0x5F6D
#define mmDC_PERFMON9_PERFMON_LOW__VI                   0x5F6E
#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA__VI       0x5F70
#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX__VI      0x5F6F
#define mmDC_PGCNTL_STATUS_REG__VI                      0x02D5
#define mmDC_PGFSM_CONFIG_REG__VI                       0x02D3
#define mmDC_PGFSM_WRITE_REG__VI                        0x02D4
#define mmDC_PINSTRAPS__VI                              0x4818
#define mmDC_REF_CLK_CNTL__VI                           0x4803
#define mmDC_TEST_DEBUG_DATA__VI                        0x157D
#define mmDC_TEST_DEBUG_INDEX__VI                       0x157C
#define mmDEGAMMA_CONTROL__VI                           0x1A58
#define mmDENORM_CLAMP_CONTROL__VI                      0x46C3
#define mmDENORM_CLAMP_RANGE_B_CB__VI                   0x46C6
#define mmDENORM_CLAMP_RANGE_G_Y__VI                    0x46C5
#define mmDENORM_CLAMP_RANGE_R_CR__VI                   0x46C4
#define mmDENORM_CONTROL__VI                            0x1A50
#define mmDENTIST_DISPCLK_CNTL__VI                      0x0124
#define mmDIG0_AFMT_60958_0__VI                         0x4A38
#define mmDIG0_AFMT_60958_1__VI                         0x4A39
#define mmDIG0_AFMT_60958_2__VI                         0x4A3F
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL__VI               0x4A3A
#define mmDIG0_AFMT_AUDIO_CRC_RESULT__VI                0x4A40
#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x4A46
#define mmDIG0_AFMT_AUDIO_INFO0__VI                     0x4A36
#define mmDIG0_AFMT_AUDIO_INFO1__VI                     0x4A37
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL__VI            0x4A42
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2__VI           0x4A14
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL__VI               0x4A45
#define mmDIG0_AFMT_AVI_INFO0__VI                       0x4A1E
#define mmDIG0_AFMT_AVI_INFO1__VI                       0x4A1F
#define mmDIG0_AFMT_AVI_INFO2__VI                       0x4A20
#define mmDIG0_AFMT_AVI_INFO3__VI                       0x4A21
#define mmDIG0_AFMT_GENERIC_0__VI                       0x4A25
#define mmDIG0_AFMT_GENERIC_1__VI                       0x4A26
#define mmDIG0_AFMT_GENERIC_2__VI                       0x4A27
#define mmDIG0_AFMT_GENERIC_3__VI                       0x4A28
#define mmDIG0_AFMT_GENERIC_4__VI                       0x4A29
#define mmDIG0_AFMT_GENERIC_5__VI                       0x4A2A
#define mmDIG0_AFMT_GENERIC_6__VI                       0x4A2B
#define mmDIG0_AFMT_GENERIC_7__VI                       0x4A2C
#define mmDIG0_AFMT_GENERIC_HDR__VI                     0x4A24
#define mmDIG0_AFMT_INFOFRAME_CONTROL0__VI              0x4A44
#define mmDIG0_AFMT_ISRC1_0__VI                         0x4A15
#define mmDIG0_AFMT_ISRC1_1__VI                         0x4A16
#define mmDIG0_AFMT_ISRC1_2__VI                         0x4A17
#define mmDIG0_AFMT_ISRC1_3__VI                         0x4A18
#define mmDIG0_AFMT_ISRC1_4__VI                         0x4A19
#define mmDIG0_AFMT_ISRC2_0__VI                         0x4A1A
#define mmDIG0_AFMT_ISRC2_1__VI                         0x4A1B
#define mmDIG0_AFMT_ISRC2_2__VI                         0x4A1C
#define mmDIG0_AFMT_ISRC2_3__VI                         0x4A1D
#define mmDIG0_AFMT_MPEG_INFO0__VI                      0x4A22
#define mmDIG0_AFMT_MPEG_INFO1__VI                      0x4A23
#define mmDIG0_AFMT_RAMP_CONTROL0__VI                   0x4A3B
#define mmDIG0_AFMT_RAMP_CONTROL1__VI                   0x4A3C
#define mmDIG0_AFMT_RAMP_CONTROL2__VI                   0x4A3D
#define mmDIG0_AFMT_RAMP_CONTROL3__VI                   0x4A3E
#define mmDIG0_AFMT_STATUS__VI                          0x4A41
#define mmDIG0_AFMT_VBI_PACKET_CONTROL__VI              0x4A43
#define mmDIG0_DIG_BE_CNTL__VI                          0x4A47
#define mmDIG0_DIG_BE_EN_CNTL__VI                       0x4A48
#define mmDIG0_DIG_CLOCK_PATTERN__VI                    0x4A03
#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL__VI              0x4A07
#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS__VI            0x4A08
#define mmDIG0_DIG_FE_CNTL__VI                          0x4A00
#define mmDIG0_DIG_FE_TEST_DEBUG_DATA__VI               0x4A7D
#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX__VI              0x4A7C
#define mmDIG0_DIG_FIFO_STATUS__VI                      0x4A06
#define mmDIG0_DIG_LANE_ENABLE__VI                      0x4A79
#define mmDIG0_DIG_OUTPUT_CRC_CNTL__VI                  0x4A01
#define mmDIG0_DIG_OUTPUT_CRC_RESULT__VI                0x4A02
#define mmDIG0_DIG_RANDOM_PATTERN_SEED__VI              0x4A05
#define mmDIG0_DIG_TEST_DEBUG_DATA__VI                  0x4A7B
#define mmDIG0_DIG_TEST_DEBUG_INDEX__VI                 0x4A7A
#define mmDIG0_DIG_TEST_PATTERN__VI                     0x4A04
#define mmDIG0_HDMI_ACR_32_0__VI                        0x4A2E
#define mmDIG0_HDMI_ACR_32_1__VI                        0x4A2F
#define mmDIG0_HDMI_ACR_44_0__VI                        0x4A30
#define mmDIG0_HDMI_ACR_44_1__VI                        0x4A31
#define mmDIG0_HDMI_ACR_48_0__VI                        0x4A32
#define mmDIG0_HDMI_ACR_48_1__VI                        0x4A33
#define mmDIG0_HDMI_ACR_PACKET_CONTROL__VI              0x4A0C
#define mmDIG0_HDMI_ACR_STATUS_0__VI                    0x4A34
#define mmDIG0_HDMI_ACR_STATUS_1__VI                    0x4A35
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL__VI            0x4A0B
#define mmDIG0_HDMI_CONTROL__VI                         0x4A09
#define mmDIG0_HDMI_GC__VI                              0x4A13
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0__VI         0x4A10
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1__VI         0x4A2D
#define mmDIG0_HDMI_INFOFRAME_CONTROL0__VI              0x4A0E
#define mmDIG0_HDMI_INFOFRAME_CONTROL1__VI              0x4A0F
#define mmDIG0_HDMI_STATUS__VI                          0x4A0A
#define mmDIG0_HDMI_VBI_PACKET_CONTROL__VI              0x4A0D
#define mmDIG0_LVDS_DATA_CNTL__VI                       0x4A78
#define mmDIG0_TMDS_CNTL__VI                            0x4A6B
#define mmDIG0_TMDS_CONTROL0_FEEDBACK__VI               0x4A6D
#define mmDIG0_TMDS_CONTROL_CHAR__VI                    0x4A6C
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL__VI                 0x4A75
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL__VI                 0x4A76
#define mmDIG0_TMDS_CTL_BITS__VI                        0x4A72
#define mmDIG0_TMDS_DCBALANCER_CONTROL__VI              0x4A73
#define mmDIG0_TMDS_DEBUG__VI                           0x4A71
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL__VI              0x4A6E
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x4A6F
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x4A70
#define mmDIG1_AFMT_60958_0__VI                         0x4B38
#define mmDIG1_AFMT_60958_1__VI                         0x4B39
#define mmDIG1_AFMT_60958_2__VI                         0x4B3F
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL__VI               0x4B3A
#define mmDIG1_AFMT_AUDIO_CRC_RESULT__VI                0x4B40
#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x4B46
#define mmDIG1_AFMT_AUDIO_INFO0__VI                     0x4B36
#define mmDIG1_AFMT_AUDIO_INFO1__VI                     0x4B37
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL__VI            0x4B42
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2__VI           0x4B14
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL__VI               0x4B45
#define mmDIG1_AFMT_AVI_INFO0__VI                       0x4B1E
#define mmDIG1_AFMT_AVI_INFO1__VI                       0x4B1F
#define mmDIG1_AFMT_AVI_INFO2__VI                       0x4B20
#define mmDIG1_AFMT_AVI_INFO3__VI                       0x4B21
#define mmDIG1_AFMT_GENERIC_0__VI                       0x4B25
#define mmDIG1_AFMT_GENERIC_1__VI                       0x4B26
#define mmDIG1_AFMT_GENERIC_2__VI                       0x4B27
#define mmDIG1_AFMT_GENERIC_3__VI                       0x4B28
#define mmDIG1_AFMT_GENERIC_4__VI                       0x4B29
#define mmDIG1_AFMT_GENERIC_5__VI                       0x4B2A
#define mmDIG1_AFMT_GENERIC_6__VI                       0x4B2B
#define mmDIG1_AFMT_GENERIC_7__VI                       0x4B2C
#define mmDIG1_AFMT_GENERIC_HDR__VI                     0x4B24
#define mmDIG1_AFMT_INFOFRAME_CONTROL0__VI              0x4B44
#define mmDIG1_AFMT_ISRC1_0__VI                         0x4B15
#define mmDIG1_AFMT_ISRC1_1__VI                         0x4B16
#define mmDIG1_AFMT_ISRC1_2__VI                         0x4B17
#define mmDIG1_AFMT_ISRC1_3__VI                         0x4B18
#define mmDIG1_AFMT_ISRC1_4__VI                         0x4B19
#define mmDIG1_AFMT_ISRC2_0__VI                         0x4B1A
#define mmDIG1_AFMT_ISRC2_1__VI                         0x4B1B
#define mmDIG1_AFMT_ISRC2_2__VI                         0x4B1C
#define mmDIG1_AFMT_ISRC2_3__VI                         0x4B1D
#define mmDIG1_AFMT_MPEG_INFO0__VI                      0x4B22
#define mmDIG1_AFMT_MPEG_INFO1__VI                      0x4B23
#define mmDIG1_AFMT_RAMP_CONTROL0__VI                   0x4B3B
#define mmDIG1_AFMT_RAMP_CONTROL1__VI                   0x4B3C
#define mmDIG1_AFMT_RAMP_CONTROL2__VI                   0x4B3D
#define mmDIG1_AFMT_RAMP_CONTROL3__VI                   0x4B3E
#define mmDIG1_AFMT_STATUS__VI                          0x4B41
#define mmDIG1_AFMT_VBI_PACKET_CONTROL__VI              0x4B43
#define mmDIG1_DIG_BE_CNTL__VI                          0x4B47
#define mmDIG1_DIG_BE_EN_CNTL__VI                       0x4B48
#define mmDIG1_DIG_CLOCK_PATTERN__VI                    0x4B03
#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL__VI              0x4B07
#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS__VI            0x4B08
#define mmDIG1_DIG_FE_CNTL__VI                          0x4B00
#define mmDIG1_DIG_FE_TEST_DEBUG_DATA__VI               0x4B7D
#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX__VI              0x4B7C
#define mmDIG1_DIG_FIFO_STATUS__VI                      0x4B06
#define mmDIG1_DIG_LANE_ENABLE__VI                      0x4B79
#define mmDIG1_DIG_OUTPUT_CRC_CNTL__VI                  0x4B01
#define mmDIG1_DIG_OUTPUT_CRC_RESULT__VI                0x4B02
#define mmDIG1_DIG_RANDOM_PATTERN_SEED__VI              0x4B05
#define mmDIG1_DIG_TEST_DEBUG_DATA__VI                  0x4B7B
#define mmDIG1_DIG_TEST_DEBUG_INDEX__VI                 0x4B7A
#define mmDIG1_DIG_TEST_PATTERN__VI                     0x4B04
#define mmDIG1_HDMI_ACR_32_0__VI                        0x4B2E
#define mmDIG1_HDMI_ACR_32_1__VI                        0x4B2F
#define mmDIG1_HDMI_ACR_44_0__VI                        0x4B30
#define mmDIG1_HDMI_ACR_44_1__VI                        0x4B31
#define mmDIG1_HDMI_ACR_48_0__VI                        0x4B32
#define mmDIG1_HDMI_ACR_48_1__VI                        0x4B33
#define mmDIG1_HDMI_ACR_PACKET_CONTROL__VI              0x4B0C
#define mmDIG1_HDMI_ACR_STATUS_0__VI                    0x4B34
#define mmDIG1_HDMI_ACR_STATUS_1__VI                    0x4B35
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL__VI            0x4B0B
#define mmDIG1_HDMI_CONTROL__VI                         0x4B09
#define mmDIG1_HDMI_GC__VI                              0x4B13
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0__VI         0x4B10
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1__VI         0x4B2D
#define mmDIG1_HDMI_INFOFRAME_CONTROL0__VI              0x4B0E
#define mmDIG1_HDMI_INFOFRAME_CONTROL1__VI              0x4B0F
#define mmDIG1_HDMI_STATUS__VI                          0x4B0A
#define mmDIG1_HDMI_VBI_PACKET_CONTROL__VI              0x4B0D
#define mmDIG1_LVDS_DATA_CNTL__VI                       0x4B78
#define mmDIG1_TMDS_CNTL__VI                            0x4B6B
#define mmDIG1_TMDS_CONTROL0_FEEDBACK__VI               0x4B6D
#define mmDIG1_TMDS_CONTROL_CHAR__VI                    0x4B6C
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL__VI                 0x4B75
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL__VI                 0x4B76
#define mmDIG1_TMDS_CTL_BITS__VI                        0x4B72
#define mmDIG1_TMDS_DCBALANCER_CONTROL__VI              0x4B73
#define mmDIG1_TMDS_DEBUG__VI                           0x4B71
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL__VI              0x4B6E
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x4B6F
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x4B70
#define mmDIG2_AFMT_60958_0__VI                         0x4C38
#define mmDIG2_AFMT_60958_1__VI                         0x4C39
#define mmDIG2_AFMT_60958_2__VI                         0x4C3F
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL__VI               0x4C3A
#define mmDIG2_AFMT_AUDIO_CRC_RESULT__VI                0x4C40
#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x4C46
#define mmDIG2_AFMT_AUDIO_INFO0__VI                     0x4C36
#define mmDIG2_AFMT_AUDIO_INFO1__VI                     0x4C37
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL__VI            0x4C42
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2__VI           0x4C14
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL__VI               0x4C45
#define mmDIG2_AFMT_AVI_INFO0__VI                       0x4C1E
#define mmDIG2_AFMT_AVI_INFO1__VI                       0x4C1F
#define mmDIG2_AFMT_AVI_INFO2__VI                       0x4C20
#define mmDIG2_AFMT_AVI_INFO3__VI                       0x4C21
#define mmDIG2_AFMT_GENERIC_0__VI                       0x4C25
#define mmDIG2_AFMT_GENERIC_1__VI                       0x4C26
#define mmDIG2_AFMT_GENERIC_2__VI                       0x4C27
#define mmDIG2_AFMT_GENERIC_3__VI                       0x4C28
#define mmDIG2_AFMT_GENERIC_4__VI                       0x4C29
#define mmDIG2_AFMT_GENERIC_5__VI                       0x4C2A
#define mmDIG2_AFMT_GENERIC_6__VI                       0x4C2B
#define mmDIG2_AFMT_GENERIC_7__VI                       0x4C2C
#define mmDIG2_AFMT_GENERIC_HDR__VI                     0x4C24
#define mmDIG2_AFMT_INFOFRAME_CONTROL0__VI              0x4C44
#define mmDIG2_AFMT_ISRC1_0__VI                         0x4C15
#define mmDIG2_AFMT_ISRC1_1__VI                         0x4C16
#define mmDIG2_AFMT_ISRC1_2__VI                         0x4C17
#define mmDIG2_AFMT_ISRC1_3__VI                         0x4C18
#define mmDIG2_AFMT_ISRC1_4__VI                         0x4C19
#define mmDIG2_AFMT_ISRC2_0__VI                         0x4C1A
#define mmDIG2_AFMT_ISRC2_1__VI                         0x4C1B
#define mmDIG2_AFMT_ISRC2_2__VI                         0x4C1C
#define mmDIG2_AFMT_ISRC2_3__VI                         0x4C1D
#define mmDIG2_AFMT_MPEG_INFO0__VI                      0x4C22
#define mmDIG2_AFMT_MPEG_INFO1__VI                      0x4C23
#define mmDIG2_AFMT_RAMP_CONTROL0__VI                   0x4C3B
#define mmDIG2_AFMT_RAMP_CONTROL1__VI                   0x4C3C
#define mmDIG2_AFMT_RAMP_CONTROL2__VI                   0x4C3D
#define mmDIG2_AFMT_RAMP_CONTROL3__VI                   0x4C3E
#define mmDIG2_AFMT_STATUS__VI                          0x4C41
#define mmDIG2_AFMT_VBI_PACKET_CONTROL__VI              0x4C43
#define mmDIG2_DIG_BE_CNTL__VI                          0x4C47
#define mmDIG2_DIG_BE_EN_CNTL__VI                       0x4C48
#define mmDIG2_DIG_CLOCK_PATTERN__VI                    0x4C03
#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL__VI              0x4C07
#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS__VI            0x4C08
#define mmDIG2_DIG_FE_CNTL__VI                          0x4C00
#define mmDIG2_DIG_FE_TEST_DEBUG_DATA__VI               0x4C7D
#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX__VI              0x4C7C
#define mmDIG2_DIG_FIFO_STATUS__VI                      0x4C06
#define mmDIG2_DIG_LANE_ENABLE__VI                      0x4C79
#define mmDIG2_DIG_OUTPUT_CRC_CNTL__VI                  0x4C01
#define mmDIG2_DIG_OUTPUT_CRC_RESULT__VI                0x4C02
#define mmDIG2_DIG_RANDOM_PATTERN_SEED__VI              0x4C05
#define mmDIG2_DIG_TEST_DEBUG_DATA__VI                  0x4C7B
#define mmDIG2_DIG_TEST_DEBUG_INDEX__VI                 0x4C7A
#define mmDIG2_DIG_TEST_PATTERN__VI                     0x4C04
#define mmDIG2_HDMI_ACR_32_0__VI                        0x4C2E
#define mmDIG2_HDMI_ACR_32_1__VI                        0x4C2F
#define mmDIG2_HDMI_ACR_44_0__VI                        0x4C30
#define mmDIG2_HDMI_ACR_44_1__VI                        0x4C31
#define mmDIG2_HDMI_ACR_48_0__VI                        0x4C32
#define mmDIG2_HDMI_ACR_48_1__VI                        0x4C33
#define mmDIG2_HDMI_ACR_PACKET_CONTROL__VI              0x4C0C
#define mmDIG2_HDMI_ACR_STATUS_0__VI                    0x4C34
#define mmDIG2_HDMI_ACR_STATUS_1__VI                    0x4C35
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL__VI            0x4C0B
#define mmDIG2_HDMI_CONTROL__VI                         0x4C09
#define mmDIG2_HDMI_GC__VI                              0x4C13
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0__VI         0x4C10
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1__VI         0x4C2D
#define mmDIG2_HDMI_INFOFRAME_CONTROL0__VI              0x4C0E
#define mmDIG2_HDMI_INFOFRAME_CONTROL1__VI              0x4C0F
#define mmDIG2_HDMI_STATUS__VI                          0x4C0A
#define mmDIG2_HDMI_VBI_PACKET_CONTROL__VI              0x4C0D
#define mmDIG2_LVDS_DATA_CNTL__VI                       0x4C78
#define mmDIG2_TMDS_CNTL__VI                            0x4C6B
#define mmDIG2_TMDS_CONTROL0_FEEDBACK__VI               0x4C6D
#define mmDIG2_TMDS_CONTROL_CHAR__VI                    0x4C6C
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL__VI                 0x4C75
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL__VI                 0x4C76
#define mmDIG2_TMDS_CTL_BITS__VI                        0x4C72
#define mmDIG2_TMDS_DCBALANCER_CONTROL__VI              0x4C73
#define mmDIG2_TMDS_DEBUG__VI                           0x4C71
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL__VI              0x4C6E
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x4C6F
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x4C70
#define mmDIG3_AFMT_60958_0__VI                         0x4D38
#define mmDIG3_AFMT_60958_1__VI                         0x4D39
#define mmDIG3_AFMT_60958_2__VI                         0x4D3F
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL__VI               0x4D3A
#define mmDIG3_AFMT_AUDIO_CRC_RESULT__VI                0x4D40
#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x4D46
#define mmDIG3_AFMT_AUDIO_INFO0__VI                     0x4D36
#define mmDIG3_AFMT_AUDIO_INFO1__VI                     0x4D37
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL__VI            0x4D42
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2__VI           0x4D14
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL__VI               0x4D45
#define mmDIG3_AFMT_AVI_INFO0__VI                       0x4D1E
#define mmDIG3_AFMT_AVI_INFO1__VI                       0x4D1F
#define mmDIG3_AFMT_AVI_INFO2__VI                       0x4D20
#define mmDIG3_AFMT_AVI_INFO3__VI                       0x4D21
#define mmDIG3_AFMT_GENERIC_0__VI                       0x4D25
#define mmDIG3_AFMT_GENERIC_1__VI                       0x4D26
#define mmDIG3_AFMT_GENERIC_2__VI                       0x4D27
#define mmDIG3_AFMT_GENERIC_3__VI                       0x4D28
#define mmDIG3_AFMT_GENERIC_4__VI                       0x4D29
#define mmDIG3_AFMT_GENERIC_5__VI                       0x4D2A
#define mmDIG3_AFMT_GENERIC_6__VI                       0x4D2B
#define mmDIG3_AFMT_GENERIC_7__VI                       0x4D2C
#define mmDIG3_AFMT_GENERIC_HDR__VI                     0x4D24
#define mmDIG3_AFMT_INFOFRAME_CONTROL0__VI              0x4D44
#define mmDIG3_AFMT_ISRC1_0__VI                         0x4D15
#define mmDIG3_AFMT_ISRC1_1__VI                         0x4D16
#define mmDIG3_AFMT_ISRC1_2__VI                         0x4D17
#define mmDIG3_AFMT_ISRC1_3__VI                         0x4D18
#define mmDIG3_AFMT_ISRC1_4__VI                         0x4D19
#define mmDIG3_AFMT_ISRC2_0__VI                         0x4D1A
#define mmDIG3_AFMT_ISRC2_1__VI                         0x4D1B
#define mmDIG3_AFMT_ISRC2_2__VI                         0x4D1C
#define mmDIG3_AFMT_ISRC2_3__VI                         0x4D1D
#define mmDIG3_AFMT_MPEG_INFO0__VI                      0x4D22
#define mmDIG3_AFMT_MPEG_INFO1__VI                      0x4D23
#define mmDIG3_AFMT_RAMP_CONTROL0__VI                   0x4D3B
#define mmDIG3_AFMT_RAMP_CONTROL1__VI                   0x4D3C
#define mmDIG3_AFMT_RAMP_CONTROL2__VI                   0x4D3D
#define mmDIG3_AFMT_RAMP_CONTROL3__VI                   0x4D3E
#define mmDIG3_AFMT_STATUS__VI                          0x4D41
#define mmDIG3_AFMT_VBI_PACKET_CONTROL__VI              0x4D43
#define mmDIG3_DIG_BE_CNTL__VI                          0x4D47
#define mmDIG3_DIG_BE_EN_CNTL__VI                       0x4D48
#define mmDIG3_DIG_CLOCK_PATTERN__VI                    0x4D03
#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL__VI              0x4D07
#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS__VI            0x4D08
#define mmDIG3_DIG_FE_CNTL__VI                          0x4D00
#define mmDIG3_DIG_FE_TEST_DEBUG_DATA__VI               0x4D7D
#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX__VI              0x4D7C
#define mmDIG3_DIG_FIFO_STATUS__VI                      0x4D06
#define mmDIG3_DIG_LANE_ENABLE__VI                      0x4D79
#define mmDIG3_DIG_OUTPUT_CRC_CNTL__VI                  0x4D01
#define mmDIG3_DIG_OUTPUT_CRC_RESULT__VI                0x4D02
#define mmDIG3_DIG_RANDOM_PATTERN_SEED__VI              0x4D05
#define mmDIG3_DIG_TEST_DEBUG_DATA__VI                  0x4D7B
#define mmDIG3_DIG_TEST_DEBUG_INDEX__VI                 0x4D7A
#define mmDIG3_DIG_TEST_PATTERN__VI                     0x4D04
#define mmDIG3_HDMI_ACR_32_0__VI                        0x4D2E
#define mmDIG3_HDMI_ACR_32_1__VI                        0x4D2F
#define mmDIG3_HDMI_ACR_44_0__VI                        0x4D30
#define mmDIG3_HDMI_ACR_44_1__VI                        0x4D31
#define mmDIG3_HDMI_ACR_48_0__VI                        0x4D32
#define mmDIG3_HDMI_ACR_48_1__VI                        0x4D33
#define mmDIG3_HDMI_ACR_PACKET_CONTROL__VI              0x4D0C
#define mmDIG3_HDMI_ACR_STATUS_0__VI                    0x4D34
#define mmDIG3_HDMI_ACR_STATUS_1__VI                    0x4D35
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL__VI            0x4D0B
#define mmDIG3_HDMI_CONTROL__VI                         0x4D09
#define mmDIG3_HDMI_GC__VI                              0x4D13
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0__VI         0x4D10
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1__VI         0x4D2D
#define mmDIG3_HDMI_INFOFRAME_CONTROL0__VI              0x4D0E
#define mmDIG3_HDMI_INFOFRAME_CONTROL1__VI              0x4D0F
#define mmDIG3_HDMI_STATUS__VI                          0x4D0A
#define mmDIG3_HDMI_VBI_PACKET_CONTROL__VI              0x4D0D
#define mmDIG3_LVDS_DATA_CNTL__VI                       0x4D78
#define mmDIG3_TMDS_CNTL__VI                            0x4D6B
#define mmDIG3_TMDS_CONTROL0_FEEDBACK__VI               0x4D6D
#define mmDIG3_TMDS_CONTROL_CHAR__VI                    0x4D6C
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL__VI                 0x4D75
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL__VI                 0x4D76
#define mmDIG3_TMDS_CTL_BITS__VI                        0x4D72
#define mmDIG3_TMDS_DCBALANCER_CONTROL__VI              0x4D73
#define mmDIG3_TMDS_DEBUG__VI                           0x4D71
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL__VI              0x4D6E
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x4D6F
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x4D70
#define mmDIG4_AFMT_60958_0__VI                         0x4E38
#define mmDIG4_AFMT_60958_1__VI                         0x4E39
#define mmDIG4_AFMT_60958_2__VI                         0x4E3F
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL__VI               0x4E3A
#define mmDIG4_AFMT_AUDIO_CRC_RESULT__VI                0x4E40
#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x4E46
#define mmDIG4_AFMT_AUDIO_INFO0__VI                     0x4E36
#define mmDIG4_AFMT_AUDIO_INFO1__VI                     0x4E37
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL__VI            0x4E42
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2__VI           0x4E14
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL__VI               0x4E45
#define mmDIG4_AFMT_AVI_INFO0__VI                       0x4E1E
#define mmDIG4_AFMT_AVI_INFO1__VI                       0x4E1F
#define mmDIG4_AFMT_AVI_INFO2__VI                       0x4E20
#define mmDIG4_AFMT_AVI_INFO3__VI                       0x4E21
#define mmDIG4_AFMT_GENERIC_0__VI                       0x4E25
#define mmDIG4_AFMT_GENERIC_1__VI                       0x4E26
#define mmDIG4_AFMT_GENERIC_2__VI                       0x4E27
#define mmDIG4_AFMT_GENERIC_3__VI                       0x4E28
#define mmDIG4_AFMT_GENERIC_4__VI                       0x4E29
#define mmDIG4_AFMT_GENERIC_5__VI                       0x4E2A
#define mmDIG4_AFMT_GENERIC_6__VI                       0x4E2B
#define mmDIG4_AFMT_GENERIC_7__VI                       0x4E2C
#define mmDIG4_AFMT_GENERIC_HDR__VI                     0x4E24
#define mmDIG4_AFMT_INFOFRAME_CONTROL0__VI              0x4E44
#define mmDIG4_AFMT_ISRC1_0__VI                         0x4E15
#define mmDIG4_AFMT_ISRC1_1__VI                         0x4E16
#define mmDIG4_AFMT_ISRC1_2__VI                         0x4E17
#define mmDIG4_AFMT_ISRC1_3__VI                         0x4E18
#define mmDIG4_AFMT_ISRC1_4__VI                         0x4E19
#define mmDIG4_AFMT_ISRC2_0__VI                         0x4E1A
#define mmDIG4_AFMT_ISRC2_1__VI                         0x4E1B
#define mmDIG4_AFMT_ISRC2_2__VI                         0x4E1C
#define mmDIG4_AFMT_ISRC2_3__VI                         0x4E1D
#define mmDIG4_AFMT_MPEG_INFO0__VI                      0x4E22
#define mmDIG4_AFMT_MPEG_INFO1__VI                      0x4E23
#define mmDIG4_AFMT_RAMP_CONTROL0__VI                   0x4E3B
#define mmDIG4_AFMT_RAMP_CONTROL1__VI                   0x4E3C
#define mmDIG4_AFMT_RAMP_CONTROL2__VI                   0x4E3D
#define mmDIG4_AFMT_RAMP_CONTROL3__VI                   0x4E3E
#define mmDIG4_AFMT_STATUS__VI                          0x4E41
#define mmDIG4_AFMT_VBI_PACKET_CONTROL__VI              0x4E43
#define mmDIG4_DIG_BE_CNTL__VI                          0x4E47
#define mmDIG4_DIG_BE_EN_CNTL__VI                       0x4E48
#define mmDIG4_DIG_CLOCK_PATTERN__VI                    0x4E03
#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL__VI              0x4E07
#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS__VI            0x4E08
#define mmDIG4_DIG_FE_CNTL__VI                          0x4E00
#define mmDIG4_DIG_FE_TEST_DEBUG_DATA__VI               0x4E7D
#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX__VI              0x4E7C
#define mmDIG4_DIG_FIFO_STATUS__VI                      0x4E06
#define mmDIG4_DIG_LANE_ENABLE__VI                      0x4E79
#define mmDIG4_DIG_OUTPUT_CRC_CNTL__VI                  0x4E01
#define mmDIG4_DIG_OUTPUT_CRC_RESULT__VI                0x4E02
#define mmDIG4_DIG_RANDOM_PATTERN_SEED__VI              0x4E05
#define mmDIG4_DIG_TEST_DEBUG_DATA__VI                  0x4E7B
#define mmDIG4_DIG_TEST_DEBUG_INDEX__VI                 0x4E7A
#define mmDIG4_DIG_TEST_PATTERN__VI                     0x4E04
#define mmDIG4_HDMI_ACR_32_0__VI                        0x4E2E
#define mmDIG4_HDMI_ACR_32_1__VI                        0x4E2F
#define mmDIG4_HDMI_ACR_44_0__VI                        0x4E30
#define mmDIG4_HDMI_ACR_44_1__VI                        0x4E31
#define mmDIG4_HDMI_ACR_48_0__VI                        0x4E32
#define mmDIG4_HDMI_ACR_48_1__VI                        0x4E33
#define mmDIG4_HDMI_ACR_PACKET_CONTROL__VI              0x4E0C
#define mmDIG4_HDMI_ACR_STATUS_0__VI                    0x4E34
#define mmDIG4_HDMI_ACR_STATUS_1__VI                    0x4E35
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL__VI            0x4E0B
#define mmDIG4_HDMI_CONTROL__VI                         0x4E09
#define mmDIG4_HDMI_GC__VI                              0x4E13
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0__VI         0x4E10
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1__VI         0x4E2D
#define mmDIG4_HDMI_INFOFRAME_CONTROL0__VI              0x4E0E
#define mmDIG4_HDMI_INFOFRAME_CONTROL1__VI              0x4E0F
#define mmDIG4_HDMI_STATUS__VI                          0x4E0A
#define mmDIG4_HDMI_VBI_PACKET_CONTROL__VI              0x4E0D
#define mmDIG4_LVDS_DATA_CNTL__VI                       0x4E78
#define mmDIG4_TMDS_CNTL__VI                            0x4E6B
#define mmDIG4_TMDS_CONTROL0_FEEDBACK__VI               0x4E6D
#define mmDIG4_TMDS_CONTROL_CHAR__VI                    0x4E6C
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL__VI                 0x4E75
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL__VI                 0x4E76
#define mmDIG4_TMDS_CTL_BITS__VI                        0x4E72
#define mmDIG4_TMDS_DCBALANCER_CONTROL__VI              0x4E73
#define mmDIG4_TMDS_DEBUG__VI                           0x4E71
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL__VI              0x4E6E
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x4E6F
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x4E70
#define mmDIG5_AFMT_60958_0__VI                         0x4F38
#define mmDIG5_AFMT_60958_1__VI                         0x4F39
#define mmDIG5_AFMT_60958_2__VI                         0x4F3F
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL__VI               0x4F3A
#define mmDIG5_AFMT_AUDIO_CRC_RESULT__VI                0x4F40
#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x4F46
#define mmDIG5_AFMT_AUDIO_INFO0__VI                     0x4F36
#define mmDIG5_AFMT_AUDIO_INFO1__VI                     0x4F37
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL__VI            0x4F42
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2__VI           0x4F14
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL__VI               0x4F45
#define mmDIG5_AFMT_AVI_INFO0__VI                       0x4F1E
#define mmDIG5_AFMT_AVI_INFO1__VI                       0x4F1F
#define mmDIG5_AFMT_AVI_INFO2__VI                       0x4F20
#define mmDIG5_AFMT_AVI_INFO3__VI                       0x4F21
#define mmDIG5_AFMT_GENERIC_0__VI                       0x4F25
#define mmDIG5_AFMT_GENERIC_1__VI                       0x4F26
#define mmDIG5_AFMT_GENERIC_2__VI                       0x4F27
#define mmDIG5_AFMT_GENERIC_3__VI                       0x4F28
#define mmDIG5_AFMT_GENERIC_4__VI                       0x4F29
#define mmDIG5_AFMT_GENERIC_5__VI                       0x4F2A
#define mmDIG5_AFMT_GENERIC_6__VI                       0x4F2B
#define mmDIG5_AFMT_GENERIC_7__VI                       0x4F2C
#define mmDIG5_AFMT_GENERIC_HDR__VI                     0x4F24
#define mmDIG5_AFMT_INFOFRAME_CONTROL0__VI              0x4F44
#define mmDIG5_AFMT_ISRC1_0__VI                         0x4F15
#define mmDIG5_AFMT_ISRC1_1__VI                         0x4F16
#define mmDIG5_AFMT_ISRC1_2__VI                         0x4F17
#define mmDIG5_AFMT_ISRC1_3__VI                         0x4F18
#define mmDIG5_AFMT_ISRC1_4__VI                         0x4F19
#define mmDIG5_AFMT_ISRC2_0__VI                         0x4F1A
#define mmDIG5_AFMT_ISRC2_1__VI                         0x4F1B
#define mmDIG5_AFMT_ISRC2_2__VI                         0x4F1C
#define mmDIG5_AFMT_ISRC2_3__VI                         0x4F1D
#define mmDIG5_AFMT_MPEG_INFO0__VI                      0x4F22
#define mmDIG5_AFMT_MPEG_INFO1__VI                      0x4F23
#define mmDIG5_AFMT_RAMP_CONTROL0__VI                   0x4F3B
#define mmDIG5_AFMT_RAMP_CONTROL1__VI                   0x4F3C
#define mmDIG5_AFMT_RAMP_CONTROL2__VI                   0x4F3D
#define mmDIG5_AFMT_RAMP_CONTROL3__VI                   0x4F3E
#define mmDIG5_AFMT_STATUS__VI                          0x4F41
#define mmDIG5_AFMT_VBI_PACKET_CONTROL__VI              0x4F43
#define mmDIG5_DIG_BE_CNTL__VI                          0x4F47
#define mmDIG5_DIG_BE_EN_CNTL__VI                       0x4F48
#define mmDIG5_DIG_CLOCK_PATTERN__VI                    0x4F03
#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL__VI              0x4F07
#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS__VI            0x4F08
#define mmDIG5_DIG_FE_CNTL__VI                          0x4F00
#define mmDIG5_DIG_FE_TEST_DEBUG_DATA__VI               0x4F7D
#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX__VI              0x4F7C
#define mmDIG5_DIG_FIFO_STATUS__VI                      0x4F06
#define mmDIG5_DIG_LANE_ENABLE__VI                      0x4F79
#define mmDIG5_DIG_OUTPUT_CRC_CNTL__VI                  0x4F01
#define mmDIG5_DIG_OUTPUT_CRC_RESULT__VI                0x4F02
#define mmDIG5_DIG_RANDOM_PATTERN_SEED__VI              0x4F05
#define mmDIG5_DIG_TEST_DEBUG_DATA__VI                  0x4F7B
#define mmDIG5_DIG_TEST_DEBUG_INDEX__VI                 0x4F7A
#define mmDIG5_DIG_TEST_PATTERN__VI                     0x4F04
#define mmDIG5_HDMI_ACR_32_0__VI                        0x4F2E
#define mmDIG5_HDMI_ACR_32_1__VI                        0x4F2F
#define mmDIG5_HDMI_ACR_44_0__VI                        0x4F30
#define mmDIG5_HDMI_ACR_44_1__VI                        0x4F31
#define mmDIG5_HDMI_ACR_48_0__VI                        0x4F32
#define mmDIG5_HDMI_ACR_48_1__VI                        0x4F33
#define mmDIG5_HDMI_ACR_PACKET_CONTROL__VI              0x4F0C
#define mmDIG5_HDMI_ACR_STATUS_0__VI                    0x4F34
#define mmDIG5_HDMI_ACR_STATUS_1__VI                    0x4F35
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL__VI            0x4F0B
#define mmDIG5_HDMI_CONTROL__VI                         0x4F09
#define mmDIG5_HDMI_GC__VI                              0x4F13
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0__VI         0x4F10
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1__VI         0x4F2D
#define mmDIG5_HDMI_INFOFRAME_CONTROL0__VI              0x4F0E
#define mmDIG5_HDMI_INFOFRAME_CONTROL1__VI              0x4F0F
#define mmDIG5_HDMI_STATUS__VI                          0x4F0A
#define mmDIG5_HDMI_VBI_PACKET_CONTROL__VI              0x4F0D
#define mmDIG5_LVDS_DATA_CNTL__VI                       0x4F78
#define mmDIG5_TMDS_CNTL__VI                            0x4F6B
#define mmDIG5_TMDS_CONTROL0_FEEDBACK__VI               0x4F6D
#define mmDIG5_TMDS_CONTROL_CHAR__VI                    0x4F6C
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL__VI                 0x4F75
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL__VI                 0x4F76
#define mmDIG5_TMDS_CTL_BITS__VI                        0x4F72
#define mmDIG5_TMDS_DCBALANCER_CONTROL__VI              0x4F73
#define mmDIG5_TMDS_DEBUG__VI                           0x4F71
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL__VI              0x4F6E
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x4F6F
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x4F70
#define mmDIG6_AFMT_60958_0__VI                         0x5438
#define mmDIG6_AFMT_60958_1__VI                         0x5439
#define mmDIG6_AFMT_60958_2__VI                         0x543F
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL__VI               0x543A
#define mmDIG6_AFMT_AUDIO_CRC_RESULT__VI                0x5440
#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL__VI              0x5446
#define mmDIG6_AFMT_AUDIO_INFO0__VI                     0x5436
#define mmDIG6_AFMT_AUDIO_INFO1__VI                     0x5437
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL__VI            0x5442
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2__VI           0x5414
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL__VI               0x5445
#define mmDIG6_AFMT_AVI_INFO0__VI                       0x541E
#define mmDIG6_AFMT_AVI_INFO1__VI                       0x541F
#define mmDIG6_AFMT_AVI_INFO2__VI                       0x5420
#define mmDIG6_AFMT_AVI_INFO3__VI                       0x5421
#define mmDIG6_AFMT_GENERIC_0__VI                       0x5425
#define mmDIG6_AFMT_GENERIC_1__VI                       0x5426
#define mmDIG6_AFMT_GENERIC_2__VI                       0x5427
#define mmDIG6_AFMT_GENERIC_3__VI                       0x5428
#define mmDIG6_AFMT_GENERIC_4__VI                       0x5429
#define mmDIG6_AFMT_GENERIC_5__VI                       0x542A
#define mmDIG6_AFMT_GENERIC_6__VI                       0x542B
#define mmDIG6_AFMT_GENERIC_7__VI                       0x542C
#define mmDIG6_AFMT_GENERIC_HDR__VI                     0x5424
#define mmDIG6_AFMT_INFOFRAME_CONTROL0__VI              0x5444
#define mmDIG6_AFMT_ISRC1_0__VI                         0x5415
#define mmDIG6_AFMT_ISRC1_1__VI                         0x5416
#define mmDIG6_AFMT_ISRC1_2__VI                         0x5417
#define mmDIG6_AFMT_ISRC1_3__VI                         0x5418
#define mmDIG6_AFMT_ISRC1_4__VI                         0x5419
#define mmDIG6_AFMT_ISRC2_0__VI                         0x541A
#define mmDIG6_AFMT_ISRC2_1__VI                         0x541B
#define mmDIG6_AFMT_ISRC2_2__VI                         0x541C
#define mmDIG6_AFMT_ISRC2_3__VI                         0x541D
#define mmDIG6_AFMT_MPEG_INFO0__VI                      0x5422
#define mmDIG6_AFMT_MPEG_INFO1__VI                      0x5423
#define mmDIG6_AFMT_RAMP_CONTROL0__VI                   0x543B
#define mmDIG6_AFMT_RAMP_CONTROL1__VI                   0x543C
#define mmDIG6_AFMT_RAMP_CONTROL2__VI                   0x543D
#define mmDIG6_AFMT_RAMP_CONTROL3__VI                   0x543E
#define mmDIG6_AFMT_STATUS__VI                          0x5441
#define mmDIG6_AFMT_VBI_PACKET_CONTROL__VI              0x5443
#define mmDIG6_DIG_BE_CNTL__VI                          0x5447
#define mmDIG6_DIG_BE_EN_CNTL__VI                       0x5448
#define mmDIG6_DIG_CLOCK_PATTERN__VI                    0x5403
#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL__VI              0x5407
#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS__VI            0x5408
#define mmDIG6_DIG_FE_CNTL__VI                          0x5400
#define mmDIG6_DIG_FE_TEST_DEBUG_DATA__VI               0x547D
#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX__VI              0x547C
#define mmDIG6_DIG_FIFO_STATUS__VI                      0x5406
#define mmDIG6_DIG_LANE_ENABLE__VI                      0x5479
#define mmDIG6_DIG_OUTPUT_CRC_CNTL__VI                  0x5401
#define mmDIG6_DIG_OUTPUT_CRC_RESULT__VI                0x5402
#define mmDIG6_DIG_RANDOM_PATTERN_SEED__VI              0x5405
#define mmDIG6_DIG_TEST_DEBUG_DATA__VI                  0x547B
#define mmDIG6_DIG_TEST_DEBUG_INDEX__VI                 0x547A
#define mmDIG6_DIG_TEST_PATTERN__VI                     0x5404
#define mmDIG6_HDMI_ACR_32_0__VI                        0x542E
#define mmDIG6_HDMI_ACR_32_1__VI                        0x542F
#define mmDIG6_HDMI_ACR_44_0__VI                        0x5430
#define mmDIG6_HDMI_ACR_44_1__VI                        0x5431
#define mmDIG6_HDMI_ACR_48_0__VI                        0x5432
#define mmDIG6_HDMI_ACR_48_1__VI                        0x5433
#define mmDIG6_HDMI_ACR_PACKET_CONTROL__VI              0x540C
#define mmDIG6_HDMI_ACR_STATUS_0__VI                    0x5434
#define mmDIG6_HDMI_ACR_STATUS_1__VI                    0x5435
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL__VI            0x540B
#define mmDIG6_HDMI_CONTROL__VI                         0x5409
#define mmDIG6_HDMI_GC__VI                              0x5413
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0__VI         0x5410
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1__VI         0x542D
#define mmDIG6_HDMI_INFOFRAME_CONTROL0__VI              0x540E
#define mmDIG6_HDMI_INFOFRAME_CONTROL1__VI              0x540F
#define mmDIG6_HDMI_STATUS__VI                          0x540A
#define mmDIG6_HDMI_VBI_PACKET_CONTROL__VI              0x540D
#define mmDIG6_LVDS_DATA_CNTL__VI                       0x5478
#define mmDIG6_TMDS_CNTL__VI                            0x546B
#define mmDIG6_TMDS_CONTROL0_FEEDBACK__VI               0x546D
#define mmDIG6_TMDS_CONTROL_CHAR__VI                    0x546C
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL__VI                 0x5475
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL__VI                 0x5476
#define mmDIG6_TMDS_CTL_BITS__VI                        0x5472
#define mmDIG6_TMDS_DCBALANCER_CONTROL__VI              0x5473
#define mmDIG6_TMDS_DEBUG__VI                           0x5471
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL__VI              0x546E
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1__VI           0x546F
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3__VI           0x5470
#define mmDIG_BE_CNTL__VI                               0x4A47
#define mmDIG_BE_EN_CNTL__VI                            0x4A48
#define mmDIG_CLOCK_PATTERN__VI                         0x4A03
#define mmDIG_DISPCLK_SWITCH_CNTL__VI                   0x4A07
#define mmDIG_DISPCLK_SWITCH_STATUS__VI                 0x4A08
#define mmDIG_FE_CNTL__VI                               0x4A00
#define mmDIG_FE_TEST_DEBUG_DATA__VI                    0x4A7D
#define mmDIG_FE_TEST_DEBUG_INDEX__VI                   0x4A7C
#define mmDIG_FIFO_STATUS__VI                           0x4A06
#define mmDIG_LANE_ENABLE__VI                           0x4A79
#define mmDIG_OUTPUT_CRC_CNTL__VI                       0x4A01
#define mmDIG_OUTPUT_CRC_RESULT__VI                     0x4A02
#define mmDIG_RANDOM_PATTERN_SEED__VI                   0x4A05
#define mmDIG_SOFT_RESET__VI                            0x1872
#define mmDIG_TEST_DEBUG_DATA__VI                       0x4A7B
#define mmDIG_TEST_DEBUG_INDEX__VI                      0x4A7A
#define mmDIG_TEST_PATTERN__VI                          0x4A04
#define mmDISPCLK_CGTT_BLK_CTRL_REG__VI                 0x0135
#define mmDISPCLK_FREQ_CHANGE_CNTL__VI                  0x0131
#define mmDISPPLL_BG_CNTL__VI                           0x171E
#define mmDISP_INTERRUPT_STATUS__VI                     0x1857
#define mmDISP_INTERRUPT_STATUS_CONTINUE__VI            0x1858
#define mmDISP_INTERRUPT_STATUS_CONTINUE2__VI           0x1859
#define mmDISP_INTERRUPT_STATUS_CONTINUE3__VI           0x185A
#define mmDISP_INTERRUPT_STATUS_CONTINUE4__VI           0x185B
#define mmDISP_INTERRUPT_STATUS_CONTINUE5__VI           0x185C
#define mmDISP_INTERRUPT_STATUS_CONTINUE6__VI           0x185D
#define mmDISP_INTERRUPT_STATUS_CONTINUE7__VI           0x185E
#define mmDISP_INTERRUPT_STATUS_CONTINUE8__VI           0x185F
#define mmDISP_INTERRUPT_STATUS_CONTINUE9__VI           0x1860
#define mmDMCU_DPRX_INTERRUPT_STATUS1__VI               0x1634
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__VI        0x1635
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI   0x1636
#define mmDMCU_PERFMON_INTERRUPT_STATUS1__VI            0x1644
#define mmDMCU_PERFMON_INTERRUPT_STATUS2__VI            0x1645
#define mmDMCU_PERFMON_INTERRUPT_STATUS3__VI            0x1646
#define mmDMCU_PERFMON_INTERRUPT_STATUS4__VI            0x1647
#define mmDMCU_PERFMON_INTERRUPT_STATUS5__VI            0x1642
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__VI   0x167C
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__VI   0x167D
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__VI   0x167E
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__VI   0x167F
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__VI   0x1633
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__VI     0x1674
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__VI     0x1675
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__VI     0x1676
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__VI     0x1677
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__VI     0x1643
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI 0x1678
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__VI 0x1679
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__VI 0x167A
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__VI 0x167B
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__VI 0x1673
#define mmDMCU_SMU_INTERRUPT_CNTL__VI                   0x012C
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS__VI             0x1613
#define mmDMCU_UC_CLK_GATING_CNTL__VI                   0x161B
#define mmDMIF_ADDR_CALC__VI                            0x0303
#define mmDMIF_ADDR_CONFIG__VI                          0x02F5
#define mmDMIF_PG0_DPG_HW_DEBUG_11__VI                  0x1B3D
#define mmDMIF_PG0_DPG_HW_DEBUG_A__VI                   0x1B3B
#define mmDMIF_PG0_DPG_HW_DEBUG_B__VI                   0x1B3C
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x1B30
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x1B31
#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL__VI             0x1B34
#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x1B36
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL__VI         0x1B35
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x1B37
#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL__VI         0x1B33
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM__VI             0x1B3A
#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA__VI              0x1B39
#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX__VI             0x1B38
#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL__VI       0x1B32
#define mmDMIF_PG1_DPG_HW_DEBUG_11__VI                  0x1D3D
#define mmDMIF_PG1_DPG_HW_DEBUG_A__VI                   0x1D3B
#define mmDMIF_PG1_DPG_HW_DEBUG_B__VI                   0x1D3C
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x1D30
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x1D31
#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL__VI             0x1D34
#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x1D36
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL__VI         0x1D35
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x1D37
#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL__VI         0x1D33
#define mmDMIF_PG1_DPG_REPEATER_PROGRAM__VI             0x1D3A
#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA__VI              0x1D39
#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX__VI             0x1D38
#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL__VI       0x1D32
#define mmDMIF_PG2_DPG_HW_DEBUG_11__VI                  0x1F3D
#define mmDMIF_PG2_DPG_HW_DEBUG_A__VI                   0x1F3B
#define mmDMIF_PG2_DPG_HW_DEBUG_B__VI                   0x1F3C
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x1F30
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x1F31
#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL__VI             0x1F34
#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x1F36
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL__VI         0x1F35
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x1F37
#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL__VI         0x1F33
#define mmDMIF_PG2_DPG_REPEATER_PROGRAM__VI             0x1F3A
#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA__VI              0x1F39
#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX__VI             0x1F38
#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL__VI       0x1F32
#define mmDMIF_PG3_DPG_HW_DEBUG_11__VI                  0x413D
#define mmDMIF_PG3_DPG_HW_DEBUG_A__VI                   0x413B
#define mmDMIF_PG3_DPG_HW_DEBUG_B__VI                   0x413C
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x4130
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x4131
#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL__VI             0x4134
#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x4136
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL__VI         0x4135
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x4137
#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL__VI         0x4133
#define mmDMIF_PG3_DPG_REPEATER_PROGRAM__VI             0x413A
#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA__VI              0x4139
#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX__VI             0x4138
#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL__VI       0x4132
#define mmDMIF_PG4_DPG_HW_DEBUG_11__VI                  0x433D
#define mmDMIF_PG4_DPG_HW_DEBUG_A__VI                   0x433B
#define mmDMIF_PG4_DPG_HW_DEBUG_B__VI                   0x433C
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x4330
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x4331
#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL__VI             0x4334
#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x4336
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL__VI         0x4335
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x4337
#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL__VI         0x4333
#define mmDMIF_PG4_DPG_REPEATER_PROGRAM__VI             0x433A
#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA__VI              0x4339
#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX__VI             0x4338
#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL__VI       0x4332
#define mmDMIF_PG5_DPG_HW_DEBUG_11__VI                  0x453D
#define mmDMIF_PG5_DPG_HW_DEBUG_A__VI                   0x453B
#define mmDMIF_PG5_DPG_HW_DEBUG_B__VI                   0x453C
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x4530
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x4531
#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL__VI             0x4534
#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x4536
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL__VI         0x4535
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x4537
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL__VI         0x4533
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM__VI             0x453A
#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA__VI              0x4539
#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX__VI             0x4538
#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL__VI       0x4532
#define mmDMIF_PG6_DPG_HW_DEBUG_11__VI                  0x473D
#define mmDMIF_PG6_DPG_HW_DEBUG_A__VI                   0x473B
#define mmDMIF_PG6_DPG_HW_DEBUG_B__VI                   0x473C
#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1__VI    0x4730
#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2__VI    0x4731
#define mmDMIF_PG6_DPG_PIPE_DPM_CONTROL__VI             0x4734
#define mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI 0x4736
#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL__VI         0x4735
#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI 0x4737
#define mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL__VI         0x4733
#define mmDMIF_PG6_DPG_REPEATER_PROGRAM__VI             0x473A
#define mmDMIF_PG6_DPG_TEST_DEBUG_DATA__VI              0x4739
#define mmDMIF_PG6_DPG_TEST_DEBUG_INDEX__VI             0x4738
#define mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL__VI       0x4732
#define mmDMIF_P_VMID__VI                               0x0300
#define mmDMIF_STATUS2__VI                              0x0304
#define mmDMIF_TEST_DEBUG_DATA__VI                      0x0302
#define mmDMIF_TEST_DEBUG_INDEX__VI                     0x0301
#define mmDMIF_URG_OVERRIDE__VI                         0x0329
#define mmDP0_DP_CONFIG__VI                             0x4AA3
#define mmDP0_DP_DPHY_8B10B_CNTL__VI                    0x4AB4
#define mmDP0_DP_DPHY_CNTL__VI                          0x4AAF
#define mmDP0_DP_DPHY_CRC_CNTL__VI                      0x4AB8
#define mmDP0_DP_DPHY_CRC_EN__VI                        0x4AB7
#define mmDP0_DP_DPHY_CRC_MST_CNTL__VI                  0x4ABA
#define mmDP0_DP_DPHY_CRC_MST_STATUS__VI                0x4ABB
#define mmDP0_DP_DPHY_CRC_RESULT__VI                    0x4AB9
#define mmDP0_DP_DPHY_FAST_TRAINING__VI                 0x4ABC
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS__VI          0x4ABD
#define mmDP0_DP_DPHY_PRBS_CNTL__VI                     0x4AB5
#define mmDP0_DP_DPHY_SYM0__VI                          0x4AB1
#define mmDP0_DP_DPHY_SYM1__VI                          0x4AB2
#define mmDP0_DP_DPHY_SYM2__VI                          0x4AB3
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x4AB0
#define mmDP0_DP_FE_TEST_DEBUG_DATA__VI                 0x4ADB
#define mmDP0_DP_FE_TEST_DEBUG_INDEX__VI                0x4ADA
#define mmDP0_DP_HBR2_EYE_PATTERN__VI                   0x4AAC
#define mmDP0_DP_LINK_CNTL__VI                          0x4AA0
#define mmDP0_DP_LINK_FRAMING_CNTL__VI                  0x4AAB
#define mmDP0_DP_MSA_COLORIMETRY__VI                    0x4AA2
#define mmDP0_DP_MSA_MISC__VI                           0x4AA6
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1__VI             0x4ABE
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2__VI             0x4ABF
#define mmDP0_DP_MSE_LINK_TIMING__VI                    0x4AD6
#define mmDP0_DP_MSE_MISC_CNTL__VI                      0x4AD7
#define mmDP0_DP_MSE_RATE_CNTL__VI                      0x4ACF
#define mmDP0_DP_MSE_RATE_UPDATE__VI                    0x4AD1
#define mmDP0_DP_MSE_SAT0__VI                           0x4AD2
#define mmDP0_DP_MSE_SAT1__VI                           0x4AD3
#define mmDP0_DP_MSE_SAT2__VI                           0x4AD4
#define mmDP0_DP_MSE_SAT_UPDATE__VI                     0x4AD5
#define mmDP0_DP_PIXEL_FORMAT__VI                       0x4AA1
#define mmDP0_DP_SEC_AUD_M__VI                          0x4ACB
#define mmDP0_DP_SEC_AUD_M_READBACK__VI                 0x4ACC
#define mmDP0_DP_SEC_AUD_N__VI                          0x4AC9
#define mmDP0_DP_SEC_AUD_N_READBACK__VI                 0x4ACA
#define mmDP0_DP_SEC_CNTL__VI                           0x4AC3
#define mmDP0_DP_SEC_CNTL1__VI                          0x4AC4
#define mmDP0_DP_SEC_FRAMING1__VI                       0x4AC5
#define mmDP0_DP_SEC_FRAMING2__VI                       0x4AC6
#define mmDP0_DP_SEC_FRAMING3__VI                       0x4AC7
#define mmDP0_DP_SEC_FRAMING4__VI                       0x4AC8
#define mmDP0_DP_SEC_PACKET_CNTL__VI                    0x4ACE
#define mmDP0_DP_SEC_TIMESTAMP__VI                      0x4ACD
#define mmDP0_DP_STEER_FIFO__VI                         0x4AA5
#define mmDP0_DP_TEST_DEBUG_DATA__VI                    0x4AD9
#define mmDP0_DP_TEST_DEBUG_INDEX__VI                   0x4AD8
#define mmDP0_DP_VID_INTERRUPT_CNTL__VI                 0x4AAE
#define mmDP0_DP_VID_M__VI                              0x4AAA
#define mmDP0_DP_VID_MSA_VBID__VI                       0x4AAD
#define mmDP0_DP_VID_N__VI                              0x4AA9
#define mmDP0_DP_VID_STREAM_CNTL__VI                    0x4AA4
#define mmDP0_DP_VID_TIMING__VI                         0x4AA8
#define mmDP1_DP_CONFIG__VI                             0x4BA3
#define mmDP1_DP_DPHY_8B10B_CNTL__VI                    0x4BB4
#define mmDP1_DP_DPHY_CNTL__VI                          0x4BAF
#define mmDP1_DP_DPHY_CRC_CNTL__VI                      0x4BB8
#define mmDP1_DP_DPHY_CRC_EN__VI                        0x4BB7
#define mmDP1_DP_DPHY_CRC_MST_CNTL__VI                  0x4BBA
#define mmDP1_DP_DPHY_CRC_MST_STATUS__VI                0x4BBB
#define mmDP1_DP_DPHY_CRC_RESULT__VI                    0x4BB9
#define mmDP1_DP_DPHY_FAST_TRAINING__VI                 0x4BBC
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS__VI          0x4BBD
#define mmDP1_DP_DPHY_PRBS_CNTL__VI                     0x4BB5
#define mmDP1_DP_DPHY_SYM0__VI                          0x4BB1
#define mmDP1_DP_DPHY_SYM1__VI                          0x4BB2
#define mmDP1_DP_DPHY_SYM2__VI                          0x4BB3
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x4BB0
#define mmDP1_DP_FE_TEST_DEBUG_DATA__VI                 0x4BDB
#define mmDP1_DP_FE_TEST_DEBUG_INDEX__VI                0x4BDA
#define mmDP1_DP_HBR2_EYE_PATTERN__VI                   0x4BAC
#define mmDP1_DP_LINK_CNTL__VI                          0x4BA0
#define mmDP1_DP_LINK_FRAMING_CNTL__VI                  0x4BAB
#define mmDP1_DP_MSA_COLORIMETRY__VI                    0x4BA2
#define mmDP1_DP_MSA_MISC__VI                           0x4BA6
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1__VI             0x4BBE
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2__VI             0x4BBF
#define mmDP1_DP_MSE_LINK_TIMING__VI                    0x4BD6
#define mmDP1_DP_MSE_MISC_CNTL__VI                      0x4BD7
#define mmDP1_DP_MSE_RATE_CNTL__VI                      0x4BCF
#define mmDP1_DP_MSE_RATE_UPDATE__VI                    0x4BD1
#define mmDP1_DP_MSE_SAT0__VI                           0x4BD2
#define mmDP1_DP_MSE_SAT1__VI                           0x4BD3
#define mmDP1_DP_MSE_SAT2__VI                           0x4BD4
#define mmDP1_DP_MSE_SAT_UPDATE__VI                     0x4BD5
#define mmDP1_DP_PIXEL_FORMAT__VI                       0x4BA1
#define mmDP1_DP_SEC_AUD_M__VI                          0x4BCB
#define mmDP1_DP_SEC_AUD_M_READBACK__VI                 0x4BCC
#define mmDP1_DP_SEC_AUD_N__VI                          0x4BC9
#define mmDP1_DP_SEC_AUD_N_READBACK__VI                 0x4BCA
#define mmDP1_DP_SEC_CNTL__VI                           0x4BC3
#define mmDP1_DP_SEC_CNTL1__VI                          0x4BC4
#define mmDP1_DP_SEC_FRAMING1__VI                       0x4BC5
#define mmDP1_DP_SEC_FRAMING2__VI                       0x4BC6
#define mmDP1_DP_SEC_FRAMING3__VI                       0x4BC7
#define mmDP1_DP_SEC_FRAMING4__VI                       0x4BC8
#define mmDP1_DP_SEC_PACKET_CNTL__VI                    0x4BCE
#define mmDP1_DP_SEC_TIMESTAMP__VI                      0x4BCD
#define mmDP1_DP_STEER_FIFO__VI                         0x4BA5
#define mmDP1_DP_TEST_DEBUG_DATA__VI                    0x4BD9
#define mmDP1_DP_TEST_DEBUG_INDEX__VI                   0x4BD8
#define mmDP1_DP_VID_INTERRUPT_CNTL__VI                 0x4BAE
#define mmDP1_DP_VID_M__VI                              0x4BAA
#define mmDP1_DP_VID_MSA_VBID__VI                       0x4BAD
#define mmDP1_DP_VID_N__VI                              0x4BA9
#define mmDP1_DP_VID_STREAM_CNTL__VI                    0x4BA4
#define mmDP1_DP_VID_TIMING__VI                         0x4BA8
#define mmDP2_DP_CONFIG__VI                             0x4CA3
#define mmDP2_DP_DPHY_8B10B_CNTL__VI                    0x4CB4
#define mmDP2_DP_DPHY_CNTL__VI                          0x4CAF
#define mmDP2_DP_DPHY_CRC_CNTL__VI                      0x4CB8
#define mmDP2_DP_DPHY_CRC_EN__VI                        0x4CB7
#define mmDP2_DP_DPHY_CRC_MST_CNTL__VI                  0x4CBA
#define mmDP2_DP_DPHY_CRC_MST_STATUS__VI                0x4CBB
#define mmDP2_DP_DPHY_CRC_RESULT__VI                    0x4CB9
#define mmDP2_DP_DPHY_FAST_TRAINING__VI                 0x4CBC
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS__VI          0x4CBD
#define mmDP2_DP_DPHY_PRBS_CNTL__VI                     0x4CB5
#define mmDP2_DP_DPHY_SYM0__VI                          0x4CB1
#define mmDP2_DP_DPHY_SYM1__VI                          0x4CB2
#define mmDP2_DP_DPHY_SYM2__VI                          0x4CB3
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x4CB0
#define mmDP2_DP_FE_TEST_DEBUG_DATA__VI                 0x4CDB
#define mmDP2_DP_FE_TEST_DEBUG_INDEX__VI                0x4CDA
#define mmDP2_DP_HBR2_EYE_PATTERN__VI                   0x4CAC
#define mmDP2_DP_LINK_CNTL__VI                          0x4CA0
#define mmDP2_DP_LINK_FRAMING_CNTL__VI                  0x4CAB
#define mmDP2_DP_MSA_COLORIMETRY__VI                    0x4CA2
#define mmDP2_DP_MSA_MISC__VI                           0x4CA6
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1__VI             0x4CBE
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2__VI             0x4CBF
#define mmDP2_DP_MSE_LINK_TIMING__VI                    0x4CD6
#define mmDP2_DP_MSE_MISC_CNTL__VI                      0x4CD7
#define mmDP2_DP_MSE_RATE_CNTL__VI                      0x4CCF
#define mmDP2_DP_MSE_RATE_UPDATE__VI                    0x4CD1
#define mmDP2_DP_MSE_SAT0__VI                           0x4CD2
#define mmDP2_DP_MSE_SAT1__VI                           0x4CD3
#define mmDP2_DP_MSE_SAT2__VI                           0x4CD4
#define mmDP2_DP_MSE_SAT_UPDATE__VI                     0x4CD5
#define mmDP2_DP_PIXEL_FORMAT__VI                       0x4CA1
#define mmDP2_DP_SEC_AUD_M__VI                          0x4CCB
#define mmDP2_DP_SEC_AUD_M_READBACK__VI                 0x4CCC
#define mmDP2_DP_SEC_AUD_N__VI                          0x4CC9
#define mmDP2_DP_SEC_AUD_N_READBACK__VI                 0x4CCA
#define mmDP2_DP_SEC_CNTL__VI                           0x4CC3
#define mmDP2_DP_SEC_CNTL1__VI                          0x4CC4
#define mmDP2_DP_SEC_FRAMING1__VI                       0x4CC5
#define mmDP2_DP_SEC_FRAMING2__VI                       0x4CC6
#define mmDP2_DP_SEC_FRAMING3__VI                       0x4CC7
#define mmDP2_DP_SEC_FRAMING4__VI                       0x4CC8
#define mmDP2_DP_SEC_PACKET_CNTL__VI                    0x4CCE
#define mmDP2_DP_SEC_TIMESTAMP__VI                      0x4CCD
#define mmDP2_DP_STEER_FIFO__VI                         0x4CA5
#define mmDP2_DP_TEST_DEBUG_DATA__VI                    0x4CD9
#define mmDP2_DP_TEST_DEBUG_INDEX__VI                   0x4CD8
#define mmDP2_DP_VID_INTERRUPT_CNTL__VI                 0x4CAE
#define mmDP2_DP_VID_M__VI                              0x4CAA
#define mmDP2_DP_VID_MSA_VBID__VI                       0x4CAD
#define mmDP2_DP_VID_N__VI                              0x4CA9
#define mmDP2_DP_VID_STREAM_CNTL__VI                    0x4CA4
#define mmDP2_DP_VID_TIMING__VI                         0x4CA8
#define mmDP3_DP_CONFIG__VI                             0x4DA3
#define mmDP3_DP_DPHY_8B10B_CNTL__VI                    0x4DB4
#define mmDP3_DP_DPHY_CNTL__VI                          0x4DAF
#define mmDP3_DP_DPHY_CRC_CNTL__VI                      0x4DB8
#define mmDP3_DP_DPHY_CRC_EN__VI                        0x4DB7
#define mmDP3_DP_DPHY_CRC_MST_CNTL__VI                  0x4DBA
#define mmDP3_DP_DPHY_CRC_MST_STATUS__VI                0x4DBB
#define mmDP3_DP_DPHY_CRC_RESULT__VI                    0x4DB9
#define mmDP3_DP_DPHY_FAST_TRAINING__VI                 0x4DBC
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS__VI          0x4DBD
#define mmDP3_DP_DPHY_PRBS_CNTL__VI                     0x4DB5
#define mmDP3_DP_DPHY_SYM0__VI                          0x4DB1
#define mmDP3_DP_DPHY_SYM1__VI                          0x4DB2
#define mmDP3_DP_DPHY_SYM2__VI                          0x4DB3
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x4DB0
#define mmDP3_DP_FE_TEST_DEBUG_DATA__VI                 0x4DDB
#define mmDP3_DP_FE_TEST_DEBUG_INDEX__VI                0x4DDA
#define mmDP3_DP_HBR2_EYE_PATTERN__VI                   0x4DAC
#define mmDP3_DP_LINK_CNTL__VI                          0x4DA0
#define mmDP3_DP_LINK_FRAMING_CNTL__VI                  0x4DAB
#define mmDP3_DP_MSA_COLORIMETRY__VI                    0x4DA2
#define mmDP3_DP_MSA_MISC__VI                           0x4DA6
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1__VI             0x4DBE
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2__VI             0x4DBF
#define mmDP3_DP_MSE_LINK_TIMING__VI                    0x4DD6
#define mmDP3_DP_MSE_MISC_CNTL__VI                      0x4DD7
#define mmDP3_DP_MSE_RATE_CNTL__VI                      0x4DCF
#define mmDP3_DP_MSE_RATE_UPDATE__VI                    0x4DD1
#define mmDP3_DP_MSE_SAT0__VI                           0x4DD2
#define mmDP3_DP_MSE_SAT1__VI                           0x4DD3
#define mmDP3_DP_MSE_SAT2__VI                           0x4DD4
#define mmDP3_DP_MSE_SAT_UPDATE__VI                     0x4DD5
#define mmDP3_DP_PIXEL_FORMAT__VI                       0x4DA1
#define mmDP3_DP_SEC_AUD_M__VI                          0x4DCB
#define mmDP3_DP_SEC_AUD_M_READBACK__VI                 0x4DCC
#define mmDP3_DP_SEC_AUD_N__VI                          0x4DC9
#define mmDP3_DP_SEC_AUD_N_READBACK__VI                 0x4DCA
#define mmDP3_DP_SEC_CNTL__VI                           0x4DC3
#define mmDP3_DP_SEC_CNTL1__VI                          0x4DC4
#define mmDP3_DP_SEC_FRAMING1__VI                       0x4DC5
#define mmDP3_DP_SEC_FRAMING2__VI                       0x4DC6
#define mmDP3_DP_SEC_FRAMING3__VI                       0x4DC7
#define mmDP3_DP_SEC_FRAMING4__VI                       0x4DC8
#define mmDP3_DP_SEC_PACKET_CNTL__VI                    0x4DCE
#define mmDP3_DP_SEC_TIMESTAMP__VI                      0x4DCD
#define mmDP3_DP_STEER_FIFO__VI                         0x4DA5
#define mmDP3_DP_TEST_DEBUG_DATA__VI                    0x4DD9
#define mmDP3_DP_TEST_DEBUG_INDEX__VI                   0x4DD8
#define mmDP3_DP_VID_INTERRUPT_CNTL__VI                 0x4DAE
#define mmDP3_DP_VID_M__VI                              0x4DAA
#define mmDP3_DP_VID_MSA_VBID__VI                       0x4DAD
#define mmDP3_DP_VID_N__VI                              0x4DA9
#define mmDP3_DP_VID_STREAM_CNTL__VI                    0x4DA4
#define mmDP3_DP_VID_TIMING__VI                         0x4DA8
#define mmDP4_DP_CONFIG__VI                             0x4EA3
#define mmDP4_DP_DPHY_8B10B_CNTL__VI                    0x4EB4
#define mmDP4_DP_DPHY_CNTL__VI                          0x4EAF
#define mmDP4_DP_DPHY_CRC_CNTL__VI                      0x4EB8
#define mmDP4_DP_DPHY_CRC_EN__VI                        0x4EB7
#define mmDP4_DP_DPHY_CRC_MST_CNTL__VI                  0x4EBA
#define mmDP4_DP_DPHY_CRC_MST_STATUS__VI                0x4EBB
#define mmDP4_DP_DPHY_CRC_RESULT__VI                    0x4EB9
#define mmDP4_DP_DPHY_FAST_TRAINING__VI                 0x4EBC
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS__VI          0x4EBD
#define mmDP4_DP_DPHY_PRBS_CNTL__VI                     0x4EB5
#define mmDP4_DP_DPHY_SYM0__VI                          0x4EB1
#define mmDP4_DP_DPHY_SYM1__VI                          0x4EB2
#define mmDP4_DP_DPHY_SYM2__VI                          0x4EB3
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x4EB0
#define mmDP4_DP_FE_TEST_DEBUG_DATA__VI                 0x4EDB
#define mmDP4_DP_FE_TEST_DEBUG_INDEX__VI                0x4EDA
#define mmDP4_DP_HBR2_EYE_PATTERN__VI                   0x4EAC
#define mmDP4_DP_LINK_CNTL__VI                          0x4EA0
#define mmDP4_DP_LINK_FRAMING_CNTL__VI                  0x4EAB
#define mmDP4_DP_MSA_COLORIMETRY__VI                    0x4EA2
#define mmDP4_DP_MSA_MISC__VI                           0x4EA6
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1__VI             0x4EBE
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2__VI             0x4EBF
#define mmDP4_DP_MSE_LINK_TIMING__VI                    0x4ED6
#define mmDP4_DP_MSE_MISC_CNTL__VI                      0x4ED7
#define mmDP4_DP_MSE_RATE_CNTL__VI                      0x4ECF
#define mmDP4_DP_MSE_RATE_UPDATE__VI                    0x4ED1
#define mmDP4_DP_MSE_SAT0__VI                           0x4ED2
#define mmDP4_DP_MSE_SAT1__VI                           0x4ED3
#define mmDP4_DP_MSE_SAT2__VI                           0x4ED4
#define mmDP4_DP_MSE_SAT_UPDATE__VI                     0x4ED5
#define mmDP4_DP_PIXEL_FORMAT__VI                       0x4EA1
#define mmDP4_DP_SEC_AUD_M__VI                          0x4ECB
#define mmDP4_DP_SEC_AUD_M_READBACK__VI                 0x4ECC
#define mmDP4_DP_SEC_AUD_N__VI                          0x4EC9
#define mmDP4_DP_SEC_AUD_N_READBACK__VI                 0x4ECA
#define mmDP4_DP_SEC_CNTL__VI                           0x4EC3
#define mmDP4_DP_SEC_CNTL1__VI                          0x4EC4
#define mmDP4_DP_SEC_FRAMING1__VI                       0x4EC5
#define mmDP4_DP_SEC_FRAMING2__VI                       0x4EC6
#define mmDP4_DP_SEC_FRAMING3__VI                       0x4EC7
#define mmDP4_DP_SEC_FRAMING4__VI                       0x4EC8
#define mmDP4_DP_SEC_PACKET_CNTL__VI                    0x4ECE
#define mmDP4_DP_SEC_TIMESTAMP__VI                      0x4ECD
#define mmDP4_DP_STEER_FIFO__VI                         0x4EA5
#define mmDP4_DP_TEST_DEBUG_DATA__VI                    0x4ED9
#define mmDP4_DP_TEST_DEBUG_INDEX__VI                   0x4ED8
#define mmDP4_DP_VID_INTERRUPT_CNTL__VI                 0x4EAE
#define mmDP4_DP_VID_M__VI                              0x4EAA
#define mmDP4_DP_VID_MSA_VBID__VI                       0x4EAD
#define mmDP4_DP_VID_N__VI                              0x4EA9
#define mmDP4_DP_VID_STREAM_CNTL__VI                    0x4EA4
#define mmDP4_DP_VID_TIMING__VI                         0x4EA8
#define mmDP5_DP_CONFIG__VI                             0x4FA3
#define mmDP5_DP_DPHY_8B10B_CNTL__VI                    0x4FB4
#define mmDP5_DP_DPHY_CNTL__VI                          0x4FAF
#define mmDP5_DP_DPHY_CRC_CNTL__VI                      0x4FB8
#define mmDP5_DP_DPHY_CRC_EN__VI                        0x4FB7
#define mmDP5_DP_DPHY_CRC_MST_CNTL__VI                  0x4FBA
#define mmDP5_DP_DPHY_CRC_MST_STATUS__VI                0x4FBB
#define mmDP5_DP_DPHY_CRC_RESULT__VI                    0x4FB9
#define mmDP5_DP_DPHY_FAST_TRAINING__VI                 0x4FBC
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS__VI          0x4FBD
#define mmDP5_DP_DPHY_PRBS_CNTL__VI                     0x4FB5
#define mmDP5_DP_DPHY_SYM0__VI                          0x4FB1
#define mmDP5_DP_DPHY_SYM1__VI                          0x4FB2
#define mmDP5_DP_DPHY_SYM2__VI                          0x4FB3
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x4FB0
#define mmDP5_DP_FE_TEST_DEBUG_DATA__VI                 0x4FDB
#define mmDP5_DP_FE_TEST_DEBUG_INDEX__VI                0x4FDA
#define mmDP5_DP_HBR2_EYE_PATTERN__VI                   0x4FAC
#define mmDP5_DP_LINK_CNTL__VI                          0x4FA0
#define mmDP5_DP_LINK_FRAMING_CNTL__VI                  0x4FAB
#define mmDP5_DP_MSA_COLORIMETRY__VI                    0x4FA2
#define mmDP5_DP_MSA_MISC__VI                           0x4FA6
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1__VI             0x4FBE
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2__VI             0x4FBF
#define mmDP5_DP_MSE_LINK_TIMING__VI                    0x4FD6
#define mmDP5_DP_MSE_MISC_CNTL__VI                      0x4FD7
#define mmDP5_DP_MSE_RATE_CNTL__VI                      0x4FCF
#define mmDP5_DP_MSE_RATE_UPDATE__VI                    0x4FD1
#define mmDP5_DP_MSE_SAT0__VI                           0x4FD2
#define mmDP5_DP_MSE_SAT1__VI                           0x4FD3
#define mmDP5_DP_MSE_SAT2__VI                           0x4FD4
#define mmDP5_DP_MSE_SAT_UPDATE__VI                     0x4FD5
#define mmDP5_DP_PIXEL_FORMAT__VI                       0x4FA1
#define mmDP5_DP_SEC_AUD_M__VI                          0x4FCB
#define mmDP5_DP_SEC_AUD_M_READBACK__VI                 0x4FCC
#define mmDP5_DP_SEC_AUD_N__VI                          0x4FC9
#define mmDP5_DP_SEC_AUD_N_READBACK__VI                 0x4FCA
#define mmDP5_DP_SEC_CNTL__VI                           0x4FC3
#define mmDP5_DP_SEC_CNTL1__VI                          0x4FC4
#define mmDP5_DP_SEC_FRAMING1__VI                       0x4FC5
#define mmDP5_DP_SEC_FRAMING2__VI                       0x4FC6
#define mmDP5_DP_SEC_FRAMING3__VI                       0x4FC7
#define mmDP5_DP_SEC_FRAMING4__VI                       0x4FC8
#define mmDP5_DP_SEC_PACKET_CNTL__VI                    0x4FCE
#define mmDP5_DP_SEC_TIMESTAMP__VI                      0x4FCD
#define mmDP5_DP_STEER_FIFO__VI                         0x4FA5
#define mmDP5_DP_TEST_DEBUG_DATA__VI                    0x4FD9
#define mmDP5_DP_TEST_DEBUG_INDEX__VI                   0x4FD8
#define mmDP5_DP_VID_INTERRUPT_CNTL__VI                 0x4FAE
#define mmDP5_DP_VID_M__VI                              0x4FAA
#define mmDP5_DP_VID_MSA_VBID__VI                       0x4FAD
#define mmDP5_DP_VID_N__VI                              0x4FA9
#define mmDP5_DP_VID_STREAM_CNTL__VI                    0x4FA4
#define mmDP5_DP_VID_TIMING__VI                         0x4FA8
#define mmDP6_DP_CONFIG__VI                             0x54A3
#define mmDP6_DP_DPHY_8B10B_CNTL__VI                    0x54B4
#define mmDP6_DP_DPHY_CNTL__VI                          0x54AF
#define mmDP6_DP_DPHY_CRC_CNTL__VI                      0x54B8
#define mmDP6_DP_DPHY_CRC_EN__VI                        0x54B7
#define mmDP6_DP_DPHY_CRC_MST_CNTL__VI                  0x54BA
#define mmDP6_DP_DPHY_CRC_MST_STATUS__VI                0x54BB
#define mmDP6_DP_DPHY_CRC_RESULT__VI                    0x54B9
#define mmDP6_DP_DPHY_FAST_TRAINING__VI                 0x54BC
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS__VI          0x54BD
#define mmDP6_DP_DPHY_PRBS_CNTL__VI                     0x54B5
#define mmDP6_DP_DPHY_SYM0__VI                          0x54B1
#define mmDP6_DP_DPHY_SYM1__VI                          0x54B2
#define mmDP6_DP_DPHY_SYM2__VI                          0x54B3
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL__VI          0x54B0
#define mmDP6_DP_FE_TEST_DEBUG_DATA__VI                 0x54DB
#define mmDP6_DP_FE_TEST_DEBUG_INDEX__VI                0x54DA
#define mmDP6_DP_HBR2_EYE_PATTERN__VI                   0x54AC
#define mmDP6_DP_LINK_CNTL__VI                          0x54A0
#define mmDP6_DP_LINK_FRAMING_CNTL__VI                  0x54AB
#define mmDP6_DP_MSA_COLORIMETRY__VI                    0x54A2
#define mmDP6_DP_MSA_MISC__VI                           0x54A6
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1__VI             0x54BE
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2__VI             0x54BF
#define mmDP6_DP_MSE_LINK_TIMING__VI                    0x54D6
#define mmDP6_DP_MSE_MISC_CNTL__VI                      0x54D7
#define mmDP6_DP_MSE_RATE_CNTL__VI                      0x54CF
#define mmDP6_DP_MSE_RATE_UPDATE__VI                    0x54D1
#define mmDP6_DP_MSE_SAT0__VI                           0x54D2
#define mmDP6_DP_MSE_SAT1__VI                           0x54D3
#define mmDP6_DP_MSE_SAT2__VI                           0x54D4
#define mmDP6_DP_MSE_SAT_UPDATE__VI                     0x54D5
#define mmDP6_DP_PIXEL_FORMAT__VI                       0x54A1
#define mmDP6_DP_SEC_AUD_M__VI                          0x54CB
#define mmDP6_DP_SEC_AUD_M_READBACK__VI                 0x54CC
#define mmDP6_DP_SEC_AUD_N__VI                          0x54C9
#define mmDP6_DP_SEC_AUD_N_READBACK__VI                 0x54CA
#define mmDP6_DP_SEC_CNTL__VI                           0x54C3
#define mmDP6_DP_SEC_CNTL1__VI                          0x54C4
#define mmDP6_DP_SEC_FRAMING1__VI                       0x54C5
#define mmDP6_DP_SEC_FRAMING2__VI                       0x54C6
#define mmDP6_DP_SEC_FRAMING3__VI                       0x54C7
#define mmDP6_DP_SEC_FRAMING4__VI                       0x54C8
#define mmDP6_DP_SEC_PACKET_CNTL__VI                    0x54CE
#define mmDP6_DP_SEC_TIMESTAMP__VI                      0x54CD
#define mmDP6_DP_STEER_FIFO__VI                         0x54A5
#define mmDP6_DP_TEST_DEBUG_DATA__VI                    0x54D9
#define mmDP6_DP_TEST_DEBUG_INDEX__VI                   0x54D8
#define mmDP6_DP_VID_INTERRUPT_CNTL__VI                 0x54AE
#define mmDP6_DP_VID_M__VI                              0x54AA
#define mmDP6_DP_VID_MSA_VBID__VI                       0x54AD
#define mmDP6_DP_VID_N__VI                              0x54A9
#define mmDP6_DP_VID_STREAM_CNTL__VI                    0x54A4
#define mmDP6_DP_VID_TIMING__VI                         0x54A8
#define mmDPDBG_CLK_FORCE_CONTROL__VI                   0x010D
#define mmDPDBG_CNTL__VI                                0x1866
#define mmDPDBG_INTERRUPT__VI                           0x1867
#define mmDPG_HW_DEBUG_11__VI                           0x1B3D
#define mmDPG_HW_DEBUG_A__VI                            0x1B3B
#define mmDPG_HW_DEBUG_B__VI                            0x1B3C
#define mmDPG_PIPE_ARBITRATION_CONTROL1__VI             0x1B30
#define mmDPG_PIPE_ARBITRATION_CONTROL2__VI             0x1B31
#define mmDPG_PIPE_DPM_CONTROL__VI                      0x1B34
#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI         0x1B36
#define mmDPG_PIPE_STUTTER_CONTROL__VI                  0x1B35
#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI         0x1B37
#define mmDPG_PIPE_URGENCY_CONTROL__VI                  0x1B33
#define mmDPG_REPEATER_PROGRAM__VI                      0x1B3A
#define mmDPG_TEST_DEBUG_DATA__VI                       0x1B39
#define mmDPG_TEST_DEBUG_INDEX__VI                      0x1B38
#define mmDPG_WATERMARK_MASK_CONTROL__VI                0x1B32
#define mmDPHY_MACRO_CNTL_RESERVED0__VI                 0x5D98
#define mmDPHY_MACRO_CNTL_RESERVED1__VI                 0x5D99
#define mmDPHY_MACRO_CNTL_RESERVED10__VI                0x5DA2
#define mmDPHY_MACRO_CNTL_RESERVED11__VI                0x5DA3
#define mmDPHY_MACRO_CNTL_RESERVED12__VI                0x5DA4
#define mmDPHY_MACRO_CNTL_RESERVED13__VI                0x5DA5
#define mmDPHY_MACRO_CNTL_RESERVED14__VI                0x5DA6
#define mmDPHY_MACRO_CNTL_RESERVED15__VI                0x5DA7
#define mmDPHY_MACRO_CNTL_RESERVED16__VI                0x5DA8
#define mmDPHY_MACRO_CNTL_RESERVED17__VI                0x5DA9
#define mmDPHY_MACRO_CNTL_RESERVED18__VI                0x5DAA
#define mmDPHY_MACRO_CNTL_RESERVED19__VI                0x5DAB
#define mmDPHY_MACRO_CNTL_RESERVED2__VI                 0x5D9A
#define mmDPHY_MACRO_CNTL_RESERVED20__VI                0x5DAC
#define mmDPHY_MACRO_CNTL_RESERVED21__VI                0x5DAD
#define mmDPHY_MACRO_CNTL_RESERVED22__VI                0x5DAE
#define mmDPHY_MACRO_CNTL_RESERVED23__VI                0x5DAF
#define mmDPHY_MACRO_CNTL_RESERVED24__VI                0x5DB0
#define mmDPHY_MACRO_CNTL_RESERVED25__VI                0x5DB1
#define mmDPHY_MACRO_CNTL_RESERVED26__VI                0x5DB2
#define mmDPHY_MACRO_CNTL_RESERVED27__VI                0x5DB3
#define mmDPHY_MACRO_CNTL_RESERVED28__VI                0x5DB4
#define mmDPHY_MACRO_CNTL_RESERVED29__VI                0x5DB5
#define mmDPHY_MACRO_CNTL_RESERVED3__VI                 0x5D9B
#define mmDPHY_MACRO_CNTL_RESERVED30__VI                0x5DB6
#define mmDPHY_MACRO_CNTL_RESERVED31__VI                0x5DB7
#define mmDPHY_MACRO_CNTL_RESERVED32__VI                0x5DB8
#define mmDPHY_MACRO_CNTL_RESERVED33__VI                0x5DB9
#define mmDPHY_MACRO_CNTL_RESERVED34__VI                0x5DBA
#define mmDPHY_MACRO_CNTL_RESERVED35__VI                0x5DBB
#define mmDPHY_MACRO_CNTL_RESERVED36__VI                0x5DBC
#define mmDPHY_MACRO_CNTL_RESERVED37__VI                0x5DBD
#define mmDPHY_MACRO_CNTL_RESERVED38__VI                0x5DBE
#define mmDPHY_MACRO_CNTL_RESERVED39__VI                0x5DBF
#define mmDPHY_MACRO_CNTL_RESERVED4__VI                 0x5D9C
#define mmDPHY_MACRO_CNTL_RESERVED40__VI                0x5DC0
#define mmDPHY_MACRO_CNTL_RESERVED41__VI                0x5DC1
#define mmDPHY_MACRO_CNTL_RESERVED42__VI                0x5DC2
#define mmDPHY_MACRO_CNTL_RESERVED43__VI                0x5DC3
#define mmDPHY_MACRO_CNTL_RESERVED44__VI                0x5DC4
#define mmDPHY_MACRO_CNTL_RESERVED45__VI                0x5DC5
#define mmDPHY_MACRO_CNTL_RESERVED46__VI                0x5DC6
#define mmDPHY_MACRO_CNTL_RESERVED47__VI                0x5DC7
#define mmDPHY_MACRO_CNTL_RESERVED48__VI                0x5DC8
#define mmDPHY_MACRO_CNTL_RESERVED49__VI                0x5DC9
#define mmDPHY_MACRO_CNTL_RESERVED5__VI                 0x5D9D
#define mmDPHY_MACRO_CNTL_RESERVED50__VI                0x5DCA
#define mmDPHY_MACRO_CNTL_RESERVED51__VI                0x5DCB
#define mmDPHY_MACRO_CNTL_RESERVED52__VI                0x5DCC
#define mmDPHY_MACRO_CNTL_RESERVED53__VI                0x5DCD
#define mmDPHY_MACRO_CNTL_RESERVED54__VI                0x5DCE
#define mmDPHY_MACRO_CNTL_RESERVED55__VI                0x5DCF
#define mmDPHY_MACRO_CNTL_RESERVED56__VI                0x5DD0
#define mmDPHY_MACRO_CNTL_RESERVED57__VI                0x5DD1
#define mmDPHY_MACRO_CNTL_RESERVED58__VI                0x5DD2
#define mmDPHY_MACRO_CNTL_RESERVED59__VI                0x5DD3
#define mmDPHY_MACRO_CNTL_RESERVED6__VI                 0x5D9E
#define mmDPHY_MACRO_CNTL_RESERVED60__VI                0x5DD4
#define mmDPHY_MACRO_CNTL_RESERVED61__VI                0x5DD5
#define mmDPHY_MACRO_CNTL_RESERVED62__VI                0x5DD6
#define mmDPHY_MACRO_CNTL_RESERVED63__VI                0x5DD7
#define mmDPHY_MACRO_CNTL_RESERVED7__VI                 0x5D9F
#define mmDPHY_MACRO_CNTL_RESERVED8__VI                 0x5DA0
#define mmDPHY_MACRO_CNTL_RESERVED9__VI                 0x5DA1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG__VI                0x0108
#define mmDPREFCLK_CNTL__VI                             0x0118
#define mmDP_AUX0_AUX_ARB_CONTROL__VI                   0x5C02
#define mmDP_AUX0_AUX_CONTROL__VI                       0x5C00
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0__VI              0x5C0A
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1__VI              0x5C0B
#define mmDP_AUX0_AUX_DPHY_RX_STATUS__VI                0x5C0D
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL__VI               0x5C09
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL__VI           0x5C08
#define mmDP_AUX0_AUX_DPHY_TX_STATUS__VI                0x5C0C
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL__VI              0x5C0E
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__VI    0x5C10
#define mmDP_AUX0_AUX_GTC_SYNC_DATA__VI                 0x5C12
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__VI        0x5C0F
#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI 0x5C13
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS__VI               0x5C11
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL__VI             0x5C03
#define mmDP_AUX0_AUX_LS_DATA__VI                       0x5C07
#define mmDP_AUX0_AUX_LS_STATUS__VI                     0x5C05
#define mmDP_AUX0_AUX_SW_CONTROL__VI                    0x5C01
#define mmDP_AUX0_AUX_SW_DATA__VI                       0x5C06
#define mmDP_AUX0_AUX_SW_STATUS__VI                     0x5C04
#define mmDP_AUX0_AUX_TEST_DEBUG_DATA__VI               0x5C15
#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX__VI              0x5C14
#define mmDP_AUX1_AUX_ARB_CONTROL__VI                   0x5C1E
#define mmDP_AUX1_AUX_CONTROL__VI                       0x5C1C
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0__VI              0x5C26
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1__VI              0x5C27
#define mmDP_AUX1_AUX_DPHY_RX_STATUS__VI                0x5C29
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL__VI               0x5C25
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL__VI           0x5C24
#define mmDP_AUX1_AUX_DPHY_TX_STATUS__VI                0x5C28
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL__VI              0x5C2A
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__VI    0x5C2C
#define mmDP_AUX1_AUX_GTC_SYNC_DATA__VI                 0x5C2E
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__VI        0x5C2B
#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI 0x5C2F
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS__VI               0x5C2D
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL__VI             0x5C1F
#define mmDP_AUX1_AUX_LS_DATA__VI                       0x5C23
#define mmDP_AUX1_AUX_LS_STATUS__VI                     0x5C21
#define mmDP_AUX1_AUX_SW_CONTROL__VI                    0x5C1D
#define mmDP_AUX1_AUX_SW_DATA__VI                       0x5C22
#define mmDP_AUX1_AUX_SW_STATUS__VI                     0x5C20
#define mmDP_AUX1_AUX_TEST_DEBUG_DATA__VI               0x5C31
#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX__VI              0x5C30
#define mmDP_AUX2_AUX_ARB_CONTROL__VI                   0x5C3A
#define mmDP_AUX2_AUX_CONTROL__VI                       0x5C38
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0__VI              0x5C42
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1__VI              0x5C43
#define mmDP_AUX2_AUX_DPHY_RX_STATUS__VI                0x5C45
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL__VI               0x5C41
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL__VI           0x5C40
#define mmDP_AUX2_AUX_DPHY_TX_STATUS__VI                0x5C44
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL__VI              0x5C46
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__VI    0x5C48
#define mmDP_AUX2_AUX_GTC_SYNC_DATA__VI                 0x5C4A
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__VI        0x5C47
#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI 0x5C4B
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS__VI               0x5C49
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL__VI             0x5C3B
#define mmDP_AUX2_AUX_LS_DATA__VI                       0x5C3F
#define mmDP_AUX2_AUX_LS_STATUS__VI                     0x5C3D
#define mmDP_AUX2_AUX_SW_CONTROL__VI                    0x5C39
#define mmDP_AUX2_AUX_SW_DATA__VI                       0x5C3E
#define mmDP_AUX2_AUX_SW_STATUS__VI                     0x5C3C
#define mmDP_AUX2_AUX_TEST_DEBUG_DATA__VI               0x5C4D
#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX__VI              0x5C4C
#define mmDP_AUX3_AUX_ARB_CONTROL__VI                   0x5C56
#define mmDP_AUX3_AUX_CONTROL__VI                       0x5C54
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0__VI              0x5C5E
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1__VI              0x5C5F
#define mmDP_AUX3_AUX_DPHY_RX_STATUS__VI                0x5C61
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL__VI               0x5C5D
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL__VI           0x5C5C
#define mmDP_AUX3_AUX_DPHY_TX_STATUS__VI                0x5C60
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL__VI              0x5C62
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__VI    0x5C64
#define mmDP_AUX3_AUX_GTC_SYNC_DATA__VI                 0x5C66
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__VI        0x5C63
#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI 0x5C67
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS__VI               0x5C65
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL__VI             0x5C57
#define mmDP_AUX3_AUX_LS_DATA__VI                       0x5C5B
#define mmDP_AUX3_AUX_LS_STATUS__VI                     0x5C59
#define mmDP_AUX3_AUX_SW_CONTROL__VI                    0x5C55
#define mmDP_AUX3_AUX_SW_DATA__VI                       0x5C5A
#define mmDP_AUX3_AUX_SW_STATUS__VI                     0x5C58
#define mmDP_AUX3_AUX_TEST_DEBUG_DATA__VI               0x5C69
#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX__VI              0x5C68
#define mmDP_AUX4_AUX_ARB_CONTROL__VI                   0x5C72
#define mmDP_AUX4_AUX_CONTROL__VI                       0x5C70
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0__VI              0x5C7A
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1__VI              0x5C7B
#define mmDP_AUX4_AUX_DPHY_RX_STATUS__VI                0x5C7D
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL__VI               0x5C79
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL__VI           0x5C78
#define mmDP_AUX4_AUX_DPHY_TX_STATUS__VI                0x5C7C
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL__VI              0x5C7E
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__VI    0x5C80
#define mmDP_AUX4_AUX_GTC_SYNC_DATA__VI                 0x5C82
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__VI        0x5C7F
#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI 0x5C83
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS__VI               0x5C81
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL__VI             0x5C73
#define mmDP_AUX4_AUX_LS_DATA__VI                       0x5C77
#define mmDP_AUX4_AUX_LS_STATUS__VI                     0x5C75
#define mmDP_AUX4_AUX_SW_CONTROL__VI                    0x5C71
#define mmDP_AUX4_AUX_SW_DATA__VI                       0x5C76
#define mmDP_AUX4_AUX_SW_STATUS__VI                     0x5C74
#define mmDP_AUX4_AUX_TEST_DEBUG_DATA__VI               0x5C85
#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX__VI              0x5C84
#define mmDP_AUX5_AUX_ARB_CONTROL__VI                   0x5C8E
#define mmDP_AUX5_AUX_CONTROL__VI                       0x5C8C
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0__VI              0x5C96
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1__VI              0x5C97
#define mmDP_AUX5_AUX_DPHY_RX_STATUS__VI                0x5C99
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL__VI               0x5C95
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL__VI           0x5C94
#define mmDP_AUX5_AUX_DPHY_TX_STATUS__VI                0x5C98
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL__VI              0x5C9A
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__VI    0x5C9C
#define mmDP_AUX5_AUX_GTC_SYNC_DATA__VI                 0x5C9E
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__VI        0x5C9B
#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI 0x5C9F
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS__VI               0x5C9D
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL__VI             0x5C8F
#define mmDP_AUX5_AUX_LS_DATA__VI                       0x5C93
#define mmDP_AUX5_AUX_LS_STATUS__VI                     0x5C91
#define mmDP_AUX5_AUX_SW_CONTROL__VI                    0x5C8D
#define mmDP_AUX5_AUX_SW_DATA__VI                       0x5C92
#define mmDP_AUX5_AUX_SW_STATUS__VI                     0x5C90
#define mmDP_AUX5_AUX_TEST_DEBUG_DATA__VI               0x5CA1
#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX__VI              0x5CA0
#define mmDP_CONFIG__VI                                 0x4AA3
#define mmDP_DPHY_8B10B_CNTL__VI                        0x4AB4
#define mmDP_DPHY_CNTL__VI                              0x4AAF
#define mmDP_DPHY_CRC_CNTL__VI                          0x4AB8
#define mmDP_DPHY_CRC_EN__VI                            0x4AB7
#define mmDP_DPHY_CRC_MST_CNTL__VI                      0x4ABA
#define mmDP_DPHY_CRC_MST_STATUS__VI                    0x4ABB
#define mmDP_DPHY_CRC_RESULT__VI                        0x4AB9
#define mmDP_DPHY_FAST_TRAINING__VI                     0x4ABC
#define mmDP_DPHY_FAST_TRAINING_STATUS__VI              0x4ABD
#define mmDP_DPHY_PRBS_CNTL__VI                         0x4AB5
#define mmDP_DPHY_SYM0__VI                              0x4AB1
#define mmDP_DPHY_SYM1__VI                              0x4AB2
#define mmDP_DPHY_SYM2__VI                              0x4AB3
#define mmDP_DPHY_TRAINING_PATTERN_SEL__VI              0x4AB0
#define mmDP_DTO0_MODULO__VI                            0x0142
#define mmDP_DTO0_PHASE__VI                             0x0141
#define mmDP_DTO1_MODULO__VI                            0x0146
#define mmDP_DTO1_PHASE__VI                             0x0145
#define mmDP_DTO2_MODULO__VI                            0x014A
#define mmDP_DTO2_PHASE__VI                             0x0149
#define mmDP_DTO3_MODULO__VI                            0x014E
#define mmDP_DTO3_PHASE__VI                             0x014D
#define mmDP_DTO4_MODULO__VI                            0x0152
#define mmDP_DTO4_PHASE__VI                             0x0151
#define mmDP_DTO5_MODULO__VI                            0x0156
#define mmDP_DTO5_PHASE__VI                             0x0155
#define mmDP_FE_TEST_DEBUG_DATA__VI                     0x4ADB
#define mmDP_FE_TEST_DEBUG_INDEX__VI                    0x4ADA
#define mmDP_HBR2_EYE_PATTERN__VI                       0x4AAC
#define mmDP_LINK_CNTL__VI                              0x4AA0
#define mmDP_LINK_FRAMING_CNTL__VI                      0x4AAB
#define mmDP_MSA_COLORIMETRY__VI                        0x4AA2
#define mmDP_MSA_MISC__VI                               0x4AA6
#define mmDP_MSA_V_TIMING_OVERRIDE1__VI                 0x4ABE
#define mmDP_MSA_V_TIMING_OVERRIDE2__VI                 0x4ABF
#define mmDP_MSE_LINK_TIMING__VI                        0x4AD6
#define mmDP_MSE_MISC_CNTL__VI                          0x4AD7
#define mmDP_MSE_RATE_CNTL__VI                          0x4ACF
#define mmDP_MSE_RATE_UPDATE__VI                        0x4AD1
#define mmDP_MSE_SAT0__VI                               0x4AD2
#define mmDP_MSE_SAT1__VI                               0x4AD3
#define mmDP_MSE_SAT2__VI                               0x4AD4
#define mmDP_MSE_SAT_UPDATE__VI                         0x4AD5
#define mmDP_PIXEL_FORMAT__VI                           0x4AA1
#define mmDP_SEC_AUD_M__VI                              0x4ACB
#define mmDP_SEC_AUD_M_READBACK__VI                     0x4ACC
#define mmDP_SEC_AUD_N__VI                              0x4AC9
#define mmDP_SEC_AUD_N_READBACK__VI                     0x4ACA
#define mmDP_SEC_CNTL__VI                               0x4AC3
#define mmDP_SEC_CNTL1__VI                              0x4AC4
#define mmDP_SEC_FRAMING1__VI                           0x4AC5
#define mmDP_SEC_FRAMING2__VI                           0x4AC6
#define mmDP_SEC_FRAMING3__VI                           0x4AC7
#define mmDP_SEC_FRAMING4__VI                           0x4AC8
#define mmDP_SEC_PACKET_CNTL__VI                        0x4ACE
#define mmDP_SEC_TIMESTAMP__VI                          0x4ACD
#define mmDP_STEER_FIFO__VI                             0x4AA5
#define mmDP_TEST_DEBUG_DATA__VI                        0x4AD9
#define mmDP_TEST_DEBUG_INDEX__VI                       0x4AD8
#define mmDP_VID_INTERRUPT_CNTL__VI                     0x4AAE
#define mmDP_VID_M__VI                                  0x4AAA
#define mmDP_VID_MSA_VBID__VI                           0x4AAD
#define mmDP_VID_N__VI                                  0x4AA9
#define mmDP_VID_STREAM_CNTL__VI                        0x4AA4
#define mmDP_VID_TIMING__VI                             0x4AA8
#define mmDVOACLKC_CNTL__VI                             0x016A
#define mmDVOACLKC_MVP_CNTL__VI                         0x0169
#define mmDVOACLKD_CNTL__VI                             0x0168
#define mmDVO_CLK_ENABLE__VI                            0x0129
#define mmDVO_CONTROL__VI                               0x16A3
#define mmDVO_CRC2_SIG_MASK__VI                         0x16A5
#define mmDVO_CRC2_SIG_RESULT__VI                       0x16A6
#define mmDVO_CRC_EN__VI                                0x16A4
#define mmDVO_ENABLE__VI                                0x16A0
#define mmDVO_FIFO_ERROR_STATUS__VI                     0x16A7
#define mmDVO_OUTPUT__VI                                0x16A2
#define mmDVO_SKEW_ADJUST__VI                           0x489F
#define mmDVO_SOURCE_SELECT__VI                         0x16A1
#define mmDVO_STRENGTH_CONTROL__VI                      0x489D
#define mmDVO_TEST_DEBUG_DATA__VI                       0x16A9
#define mmDVO_TEST_DEBUG_INDEX__VI                      0x16A8
#define mmDVO_VREF_CONTROL__VI                          0x489E
#define mmFBC_CLIENT_REGION_MASK__VI                    0x029B
#define mmFBC_CNTL__VI                                  0x0280
#define mmFBC_COMP_CNTL__VI                             0x0284
#define mmFBC_COMP_MODE__VI                             0x0285
#define mmFBC_CSM_REGION_OFFSET_01__VI                  0x0299
#define mmFBC_CSM_REGION_OFFSET_23__VI                  0x029A
#define mmFBC_DEBUG0__VI                                0x0286
#define mmFBC_DEBUG1__VI                                0x0287
#define mmFBC_DEBUG2__VI                                0x0288
#define mmFBC_DEBUG_COMP__VI                            0x029C
#define mmFBC_DEBUG_CSR__VI                             0x029D
#define mmFBC_DEBUG_CSR_RDATA__VI                       0x029E
#define mmFBC_DEBUG_CSR_RDATA_HI__VI                    0x02A0
#define mmFBC_DEBUG_CSR_WDATA__VI                       0x029F
#define mmFBC_DEBUG_CSR_WDATA_HI__VI                    0x02A1
#define mmFBC_IDLE_FORCE_CLEAR_MASK__VI                 0x0282
#define mmFBC_IDLE_MASK__VI                             0x0281
#define mmFBC_IND_LUT0__VI                              0x0289
#define mmFBC_IND_LUT1__VI                              0x028A
#define mmFBC_IND_LUT10__VI                             0x0293
#define mmFBC_IND_LUT11__VI                             0x0294
#define mmFBC_IND_LUT12__VI                             0x0295
#define mmFBC_IND_LUT13__VI                             0x0296
#define mmFBC_IND_LUT14__VI                             0x0297
#define mmFBC_IND_LUT15__VI                             0x0298
#define mmFBC_IND_LUT2__VI                              0x028B
#define mmFBC_IND_LUT3__VI                              0x028C
#define mmFBC_IND_LUT4__VI                              0x028D
#define mmFBC_IND_LUT5__VI                              0x028E
#define mmFBC_IND_LUT6__VI                              0x028F
#define mmFBC_IND_LUT7__VI                              0x0290
#define mmFBC_IND_LUT8__VI                              0x0291
#define mmFBC_IND_LUT9__VI                              0x0292
#define mmFBC_MISC__VI                                  0x02A2
#define mmFBC_START_STOP_DELAY__VI                      0x0283
#define mmFBC_STATUS__VI                                0x02A3
#define mmFBC_TEST_DEBUG_DATA__VI                       0x02A5
#define mmFBC_TEST_DEBUG_INDEX__VI                      0x02A4
#define mmFMT0_FMT_CLAMP_COMPONENT_B__VI                0x1BEA
#define mmFMT0_FMT_CLAMP_COMPONENT_G__VI                0x1BE9
#define mmFMT0_FMT_CLAMP_COMPONENT_R__VI                0x1BE8
#define mmFMT0_FMT_TEST_DEBUG_DATA__VI                  0x1BEC
#define mmFMT0_FMT_TEST_DEBUG_INDEX__VI                 0x1BEB
#define mmFMT1_FMT_BIT_DEPTH_CONTROL__VI                0x1DF2
#define mmFMT1_FMT_CLAMP_CNTL__VI                       0x1DF9
#define mmFMT1_FMT_CLAMP_COMPONENT_B__VI                0x1DEA
#define mmFMT1_FMT_CLAMP_COMPONENT_G__VI                0x1DE9
#define mmFMT1_FMT_CLAMP_COMPONENT_R__VI                0x1DE8
#define mmFMT1_FMT_CONTROL__VI                          0x1DEE
#define mmFMT1_FMT_CRC_CNTL__VI                         0x1DFA
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL__VI             0x1DFE
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI        0x1DFC
#define mmFMT1_FMT_CRC_SIG_RED_GREEN__VI                0x1DFD
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK__VI           0x1DFB
#define mmFMT1_FMT_DEBUG_CNTL__VI                       0x1DFF
#define mmFMT1_FMT_DITHER_RAND_B_SEED__VI               0x1DF5
#define mmFMT1_FMT_DITHER_RAND_G_SEED__VI               0x1DF4
#define mmFMT1_FMT_DITHER_RAND_R_SEED__VI               0x1DF3
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL__VI                 0x1DED
#define mmFMT1_FMT_FORCE_DATA_0_1__VI                   0x1DF0
#define mmFMT1_FMT_FORCE_DATA_2_3__VI                   0x1DF1
#define mmFMT1_FMT_FORCE_OUTPUT_CNTL__VI                0x1DEF
#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI  0x1DF6
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI 0x1DF7
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI 0x1DF8
#define mmFMT1_FMT_TEST_DEBUG_DATA__VI                  0x1DEC
#define mmFMT1_FMT_TEST_DEBUG_INDEX__VI                 0x1DEB
#define mmFMT2_FMT_BIT_DEPTH_CONTROL__VI                0x1FF2
#define mmFMT2_FMT_CLAMP_CNTL__VI                       0x1FF9
#define mmFMT2_FMT_CLAMP_COMPONENT_B__VI                0x1FEA
#define mmFMT2_FMT_CLAMP_COMPONENT_G__VI                0x1FE9
#define mmFMT2_FMT_CLAMP_COMPONENT_R__VI                0x1FE8
#define mmFMT2_FMT_CONTROL__VI                          0x1FEE
#define mmFMT2_FMT_CRC_CNTL__VI                         0x1FFA
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL__VI             0x1FFE
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI        0x1FFC
#define mmFMT2_FMT_CRC_SIG_RED_GREEN__VI                0x1FFD
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK__VI           0x1FFB
#define mmFMT2_FMT_DEBUG_CNTL__VI                       0x1FFF
#define mmFMT2_FMT_DITHER_RAND_B_SEED__VI               0x1FF5
#define mmFMT2_FMT_DITHER_RAND_G_SEED__VI               0x1FF4
#define mmFMT2_FMT_DITHER_RAND_R_SEED__VI               0x1FF3
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL__VI                 0x1FED
#define mmFMT2_FMT_FORCE_DATA_0_1__VI                   0x1FF0
#define mmFMT2_FMT_FORCE_DATA_2_3__VI                   0x1FF1
#define mmFMT2_FMT_FORCE_OUTPUT_CNTL__VI                0x1FEF
#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI  0x1FF6
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI 0x1FF7
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI 0x1FF8
#define mmFMT2_FMT_TEST_DEBUG_DATA__VI                  0x1FEC
#define mmFMT2_FMT_TEST_DEBUG_INDEX__VI                 0x1FEB
#define mmFMT3_FMT_BIT_DEPTH_CONTROL__VI                0x41F2
#define mmFMT3_FMT_CLAMP_CNTL__VI                       0x41F9
#define mmFMT3_FMT_CLAMP_COMPONENT_B__VI                0x41EA
#define mmFMT3_FMT_CLAMP_COMPONENT_G__VI                0x41E9
#define mmFMT3_FMT_CLAMP_COMPONENT_R__VI                0x41E8
#define mmFMT3_FMT_CONTROL__VI                          0x41EE
#define mmFMT3_FMT_CRC_CNTL__VI                         0x41FA
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL__VI             0x41FE
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI        0x41FC
#define mmFMT3_FMT_CRC_SIG_RED_GREEN__VI                0x41FD
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK__VI           0x41FB
#define mmFMT3_FMT_DEBUG_CNTL__VI                       0x41FF
#define mmFMT3_FMT_DITHER_RAND_B_SEED__VI               0x41F5
#define mmFMT3_FMT_DITHER_RAND_G_SEED__VI               0x41F4
#define mmFMT3_FMT_DITHER_RAND_R_SEED__VI               0x41F3
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL__VI                 0x41ED
#define mmFMT3_FMT_FORCE_DATA_0_1__VI                   0x41F0
#define mmFMT3_FMT_FORCE_DATA_2_3__VI                   0x41F1
#define mmFMT3_FMT_FORCE_OUTPUT_CNTL__VI                0x41EF
#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI  0x41F6
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI 0x41F7
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI 0x41F8
#define mmFMT3_FMT_TEST_DEBUG_DATA__VI                  0x41EC
#define mmFMT3_FMT_TEST_DEBUG_INDEX__VI                 0x41EB
#define mmFMT4_FMT_BIT_DEPTH_CONTROL__VI                0x43F2
#define mmFMT4_FMT_CLAMP_CNTL__VI                       0x43F9
#define mmFMT4_FMT_CLAMP_COMPONENT_B__VI                0x43EA
#define mmFMT4_FMT_CLAMP_COMPONENT_G__VI                0x43E9
#define mmFMT4_FMT_CLAMP_COMPONENT_R__VI                0x43E8
#define mmFMT4_FMT_CONTROL__VI                          0x43EE
#define mmFMT4_FMT_CRC_CNTL__VI                         0x43FA
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL__VI             0x43FE
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI        0x43FC
#define mmFMT4_FMT_CRC_SIG_RED_GREEN__VI                0x43FD
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK__VI           0x43FB
#define mmFMT4_FMT_DEBUG_CNTL__VI                       0x43FF
#define mmFMT4_FMT_DITHER_RAND_B_SEED__VI               0x43F5
#define mmFMT4_FMT_DITHER_RAND_G_SEED__VI               0x43F4
#define mmFMT4_FMT_DITHER_RAND_R_SEED__VI               0x43F3
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL__VI                 0x43ED
#define mmFMT4_FMT_FORCE_DATA_0_1__VI                   0x43F0
#define mmFMT4_FMT_FORCE_DATA_2_3__VI                   0x43F1
#define mmFMT4_FMT_FORCE_OUTPUT_CNTL__VI                0x43EF
#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI  0x43F6
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI 0x43F7
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI 0x43F8
#define mmFMT4_FMT_TEST_DEBUG_DATA__VI                  0x43EC
#define mmFMT4_FMT_TEST_DEBUG_INDEX__VI                 0x43EB
#define mmFMT5_FMT_BIT_DEPTH_CONTROL__VI                0x45F2
#define mmFMT5_FMT_CLAMP_CNTL__VI                       0x45F9
#define mmFMT5_FMT_CLAMP_COMPONENT_B__VI                0x45EA
#define mmFMT5_FMT_CLAMP_COMPONENT_G__VI                0x45E9
#define mmFMT5_FMT_CLAMP_COMPONENT_R__VI                0x45E8
#define mmFMT5_FMT_CONTROL__VI                          0x45EE
#define mmFMT5_FMT_CRC_CNTL__VI                         0x45FA
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL__VI             0x45FE
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI        0x45FC
#define mmFMT5_FMT_CRC_SIG_RED_GREEN__VI                0x45FD
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK__VI           0x45FB
#define mmFMT5_FMT_DEBUG_CNTL__VI                       0x45FF
#define mmFMT5_FMT_DITHER_RAND_B_SEED__VI               0x45F5
#define mmFMT5_FMT_DITHER_RAND_G_SEED__VI               0x45F4
#define mmFMT5_FMT_DITHER_RAND_R_SEED__VI               0x45F3
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL__VI                 0x45ED
#define mmFMT5_FMT_FORCE_DATA_0_1__VI                   0x45F0
#define mmFMT5_FMT_FORCE_DATA_2_3__VI                   0x45F1
#define mmFMT5_FMT_FORCE_OUTPUT_CNTL__VI                0x45EF
#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI  0x45F6
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI 0x45F7
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI 0x45F8
#define mmFMT5_FMT_TEST_DEBUG_DATA__VI                  0x45EC
#define mmFMT5_FMT_TEST_DEBUG_INDEX__VI                 0x45EB
#define mmFMT_CLAMP_COMPONENT_B__VI                     0x1BEA
#define mmFMT_CLAMP_COMPONENT_G__VI                     0x1BE9
#define mmFMT_CLAMP_COMPONENT_R__VI                     0x1BE8
#define mmFMT_TEST_DEBUG_DATA__VI                       0x1BEC
#define mmFMT_TEST_DEBUG_INDEX__VI                      0x1BEB
#define mmGAMMA_CORR_CNTLA_END_CNTL1__VI                0x46CE
#define mmGAMMA_CORR_CNTLA_END_CNTL2__VI                0x46CF
#define mmGAMMA_CORR_CNTLA_REGION_0_1__VI               0x46D0
#define mmGAMMA_CORR_CNTLA_REGION_10_11__VI             0x46D5
#define mmGAMMA_CORR_CNTLA_REGION_12_13__VI             0x46D6
#define mmGAMMA_CORR_CNTLA_REGION_14_15__VI             0x46D7
#define mmGAMMA_CORR_CNTLA_REGION_2_3__VI               0x46D1
#define mmGAMMA_CORR_CNTLA_REGION_4_5__VI               0x46D2
#define mmGAMMA_CORR_CNTLA_REGION_6_7__VI               0x46D3
#define mmGAMMA_CORR_CNTLA_REGION_8_9__VI               0x46D4
#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL__VI               0x46CD
#define mmGAMMA_CORR_CNTLA_START_CNTL__VI               0x46CC
#define mmGAMMA_CORR_CNTLB_END_CNTL1__VI                0x46DA
#define mmGAMMA_CORR_CNTLB_END_CNTL2__VI                0x46DB
#define mmGAMMA_CORR_CNTLB_REGION_0_1__VI               0x46DC
#define mmGAMMA_CORR_CNTLB_REGION_10_11__VI             0x46E1
#define mmGAMMA_CORR_CNTLB_REGION_12_13__VI             0x46E2
#define mmGAMMA_CORR_CNTLB_REGION_14_15__VI             0x46E3
#define mmGAMMA_CORR_CNTLB_REGION_2_3__VI               0x46DD
#define mmGAMMA_CORR_CNTLB_REGION_4_5__VI               0x46DE
#define mmGAMMA_CORR_CNTLB_REGION_6_7__VI               0x46DF
#define mmGAMMA_CORR_CNTLB_REGION_8_9__VI               0x46E0
#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL__VI               0x46D9
#define mmGAMMA_CORR_CNTLB_START_CNTL__VI               0x46D8
#define mmGAMMA_CORR_CONTROL__VI                        0x46C8
#define mmGAMMA_CORR_LUT_DATA__VI                       0x46CA
#define mmGAMMA_CORR_LUT_INDEX__VI                      0x46C9
#define mmGAMMA_CORR_LUT_WRITE_EN_MASK__VI              0x46CB
#define mmGAMUT_REMAP_C11_C12__VI                       0x1A5A
#define mmGAMUT_REMAP_C13_C14__VI                       0x1A5B
#define mmGAMUT_REMAP_C21_C22__VI                       0x1A5C
#define mmGAMUT_REMAP_C23_C24__VI                       0x1A5D
#define mmGAMUT_REMAP_C31_C32__VI                       0x1A5E
#define mmGAMUT_REMAP_C33_C34__VI                       0x1A5F
#define mmGAMUT_REMAP_CONTROL__VI                       0x1A59
#define mmGARLIC_COHE_CP_DMA_ME_COMMAND__VI             0x141B
#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND__VI            0x141C
#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND__VI            0x1424
#define mmGARLIC_COHE_CP_RB0_WPTR__VI                   0x1415
#define mmGARLIC_COHE_CP_RB1_WPTR__VI                   0x1416
#define mmGARLIC_COHE_CP_RB2_WPTR__VI                   0x1417
#define mmGARLIC_COHE_GARLIC_FLUSH_REQ__VI              0x1425
#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR__VI              0x141D
#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR__VI              0x141E
#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR__VI             0x1419
#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR__VI             0x141A
#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR__VI             0x1422
#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR__VI             0x1423
#define mmGARLIC_COHE_UVD_RBC_RB_WPTR__VI               0x1418
#define mmGARLIC_COHE_VCE_OUT_RB_WPTR__VI               0x141F
#define mmGARLIC_COHE_VCE_RB_WPTR__VI                   0x1421
#define mmGARLIC_COHE_VCE_RB_WPTR2__VI                  0x1420
#define mmGC_CAC_CGTT_CLK_CTRL__VI                      0x3292
#define mmGC_CAC_LKG_AGGR_LOWER__VI                     0x3296
#define mmGC_CAC_LKG_AGGR_UPPER__VI                     0x3297
#define mmGC_USER_SHADER_RATE_CONFIG__VI                0x2313
#define mmGDS_CS_CTXSW_CNT0__VI                         0x334E
#define mmGDS_CS_CTXSW_CNT1__VI                         0x334F
#define mmGDS_CS_CTXSW_CNT2__VI                         0x3350
#define mmGDS_CS_CTXSW_CNT3__VI                         0x3351
#define mmGDS_CS_CTXSW_STATUS__VI                       0x334D
#define mmGDS_DSM_CNTL__VI                              0x25CA
#define mmGDS_EDC_CNT__VI                               0x25C5
#define mmGDS_EDC_GRBM_CNT__VI                          0x25C6
#define mmGDS_EDC_OA_DED__VI                            0x25C7
#define mmGDS_GFX_CTXSW_STATUS__VI                      0x3352
#define mmGDS_PS0_CTXSW_CNT0__VI                        0x3357
#define mmGDS_PS0_CTXSW_CNT1__VI                        0x3358
#define mmGDS_PS0_CTXSW_CNT2__VI                        0x3359
#define mmGDS_PS0_CTXSW_CNT3__VI                        0x335A
#define mmGDS_PS1_CTXSW_CNT0__VI                        0x335B
#define mmGDS_PS1_CTXSW_CNT1__VI                        0x335C
#define mmGDS_PS1_CTXSW_CNT2__VI                        0x335D
#define mmGDS_PS1_CTXSW_CNT3__VI                        0x335E
#define mmGDS_PS2_CTXSW_CNT0__VI                        0x335F
#define mmGDS_PS2_CTXSW_CNT1__VI                        0x3360
#define mmGDS_PS2_CTXSW_CNT2__VI                        0x3361
#define mmGDS_PS2_CTXSW_CNT3__VI                        0x3362
#define mmGDS_PS3_CTXSW_CNT0__VI                        0x3363
#define mmGDS_PS3_CTXSW_CNT1__VI                        0x3364
#define mmGDS_PS3_CTXSW_CNT2__VI                        0x3365
#define mmGDS_PS3_CTXSW_CNT3__VI                        0x3366
#define mmGDS_PS4_CTXSW_CNT0__VI                        0x3367
#define mmGDS_PS4_CTXSW_CNT1__VI                        0x3368
#define mmGDS_PS4_CTXSW_CNT2__VI                        0x3369
#define mmGDS_PS4_CTXSW_CNT3__VI                        0x336A
#define mmGDS_PS5_CTXSW_CNT0__VI                        0x336B
#define mmGDS_PS5_CTXSW_CNT1__VI                        0x336C
#define mmGDS_PS5_CTXSW_CNT2__VI                        0x336D
#define mmGDS_PS5_CTXSW_CNT3__VI                        0x336E
#define mmGDS_PS6_CTXSW_CNT0__VI                        0x336F
#define mmGDS_PS6_CTXSW_CNT1__VI                        0x3370
#define mmGDS_PS6_CTXSW_CNT2__VI                        0x3371
#define mmGDS_PS6_CTXSW_CNT3__VI                        0x3372
#define mmGDS_PS7_CTXSW_CNT0__VI                        0x3373
#define mmGDS_PS7_CTXSW_CNT1__VI                        0x3374
#define mmGDS_PS7_CTXSW_CNT2__VI                        0x3375
#define mmGDS_PS7_CTXSW_CNT3__VI                        0x3376
#define mmGDS_VS_CTXSW_CNT0__VI                         0x3353
#define mmGDS_VS_CTXSW_CNT1__VI                         0x3354
#define mmGDS_VS_CTXSW_CNT2__VI                         0x3355
#define mmGDS_VS_CTXSW_CNT3__VI                         0x3356
#define mmGENERIC_I2C_CONTROL__VI                       0x16F4
#define mmGENERIC_I2C_DATA__VI                          0x16FA
#define mmGENERIC_I2C_INTERRUPT_CONTROL__VI             0x16F5
#define mmGENERIC_I2C_PIN_DEBUG__VI                     0x16FC
#define mmGENERIC_I2C_PIN_SELECTION__VI                 0x16FB
#define mmGENERIC_I2C_SETUP__VI                         0x16F8
#define mmGENERIC_I2C_SPEED__VI                         0x16F7
#define mmGENERIC_I2C_STATUS__VI                        0x16F6
#define mmGENERIC_I2C_TRANSACTION__VI                   0x16F9
#define mmGMCON_LPT_TARGET__VI                          0x0D53
#define mmGPU_BIST_CONTROL__VI                          0xF835
#define mmGRBM_CAM_DATA__SI__CI                         0x3001
#define mmGRBM_CAM_DATA__VI                             0xF83F
#define mmGRBM_CAM_INDEX__SI__CI                        0x3000
#define mmGRBM_CAM_INDEX__VI                            0xF83E
#define mmGRBM_DSM_BYPASS__VI                           0x201E
#define mmGRBM_HYP_CAM_DATA__VI                         0xF83F
#define mmGRBM_HYP_CAM_INDEX__VI                        0xF83E
#define mmGRBM_TRAP_ADDR__VI                            0x201A
#define mmGRBM_TRAP_ADDR_MSK__VI                        0x201B
#define mmGRBM_TRAP_OP__VI                              0x2019
#define mmGRBM_TRAP_WD__VI                              0x201C
#define mmGRBM_TRAP_WD_MSK__VI                          0x201D
#define mmGRBM_WRITE_ERROR__VI                          0x201F
#define mmGRPH_FLIP_RATE_CNTL__VI                       0x1A8E
#define mmGRPH_STEREOSYNC_FLIP__VI                      0x1A97
#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI        0x1A9F
#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI      0x1ABF
#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI        0x1ABD
#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI   0x1ABE
#define mmGSKT_CONTROL__VI                              0x14BF
#define mmHDMI_ACR_32_0__VI                             0x4A2E
#define mmHDMI_ACR_32_1__VI                             0x4A2F
#define mmHDMI_ACR_44_0__VI                             0x4A30
#define mmHDMI_ACR_44_1__VI                             0x4A31
#define mmHDMI_ACR_48_0__VI                             0x4A32
#define mmHDMI_ACR_48_1__VI                             0x4A33
#define mmHDMI_ACR_PACKET_CONTROL__VI                   0x4A0C
#define mmHDMI_ACR_STATUS_0__VI                         0x4A34
#define mmHDMI_ACR_STATUS_1__VI                         0x4A35
#define mmHDMI_AUDIO_PACKET_CONTROL__VI                 0x4A0B
#define mmHDMI_CONTROL__VI                              0x4A09
#define mmHDMI_GC__VI                                   0x4A13
#define mmHDMI_GENERIC_PACKET_CONTROL0__VI              0x4A10
#define mmHDMI_GENERIC_PACKET_CONTROL1__VI              0x4A2D
#define mmHDMI_INFOFRAME_CONTROL0__VI                   0x4A0E
#define mmHDMI_INFOFRAME_CONTROL1__VI                   0x4A0F
#define mmHDMI_STATUS__VI                               0x4A0A
#define mmHDMI_VBI_PACKET_CONTROL__VI                   0x4A0D
#define mmHDP_ADDR_CONFIG__VI                           0x0BD2
#define mmHDP_MEMIO_ADDR__VI                            0x0BF7
#define mmHDP_MEMIO_CNTL__VI                            0x0BF6
#define mmHDP_MEMIO_RD_DATA__VI                         0x0BFA
#define mmHDP_MEMIO_STATUS__VI                          0x0BF8
#define mmHDP_MEMIO_WR_DATA__VI                         0x0BF9
#define mmHDP_MEM_POWER_LS__VI                          0x0BD4
#define mmHDP_MISC_CNTL__VI                             0x0BD3
#define mmHDP_NONSURFACE_PREFETCH__VI                   0x0BD5
#define mmHDP_VF_ENABLE__VI                             0x0BFB
#define mmHDP_XDP_BARS_ADDR_39_36__VI                   0x0C44
#define mmHPD0_DC_HPD_CONTROL__VI                       0x189A
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL__VI               0x189B
#define mmHPD0_DC_HPD_INT_CONTROL__VI                   0x1899
#define mmHPD0_DC_HPD_INT_STATUS__VI                    0x1898
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL__VI              0x189C
#define mmHPD1_DC_HPD_CONTROL__VI                       0x18A2
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL__VI               0x18A3
#define mmHPD1_DC_HPD_INT_CONTROL__VI                   0x18A1
#define mmHPD1_DC_HPD_INT_STATUS__VI                    0x18A0
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL__VI              0x18A4
#define mmHPD2_DC_HPD_CONTROL__VI                       0x18AA
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL__VI               0x18AB
#define mmHPD2_DC_HPD_INT_CONTROL__VI                   0x18A9
#define mmHPD2_DC_HPD_INT_STATUS__VI                    0x18A8
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL__VI              0x18AC
#define mmHPD3_DC_HPD_CONTROL__VI                       0x18B2
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL__VI               0x18B3
#define mmHPD3_DC_HPD_INT_CONTROL__VI                   0x18B1
#define mmHPD3_DC_HPD_INT_STATUS__VI                    0x18B0
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL__VI              0x18B4
#define mmHPD4_DC_HPD_CONTROL__VI                       0x18BA
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL__VI               0x18BB
#define mmHPD4_DC_HPD_INT_CONTROL__VI                   0x18B9
#define mmHPD4_DC_HPD_INT_STATUS__VI                    0x18B8
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL__VI              0x18BC
#define mmHPD5_DC_HPD_CONTROL__VI                       0x18C2
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL__VI               0x18C3
#define mmHPD5_DC_HPD_INT_CONTROL__VI                   0x18C1
#define mmHPD5_DC_HPD_INT_STATUS__VI                    0x18C0
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL__VI              0x18C4
#define mmHW_ROTATION__VI                               0x1A9E
#define mmIH_ACTIVE_FCN_ID__VI                          0x0E43
#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT__VI         0x0E4B
#define mmIH_CNTL__SI__CI                               0x0F86
#define mmIH_CNTL__VI                                   0x0E36
#define mmIH_DEBUG__VI                                  0x0E3C
#define mmIH_DOORBELL_RPTR__VI                          0x0E42
#define mmIH_DSM_MATCH_DATA_CONTROL__VI                 0x0E41
#define mmIH_DSM_MATCH_FIELD_CONTROL__VI                0x0E40
#define mmIH_DSM_MATCH_VALUE_BIT_31_0__VI               0x0E3D
#define mmIH_DSM_MATCH_VALUE_BIT_63_32__VI              0x0E3E
#define mmIH_DSM_MATCH_VALUE_BIT_95_64__VI              0x0E3F
#define mmIH_LEVEL_INTR_MASK__VI                        0x0E49
#define mmIH_LEVEL_STATUS__SI__CI                       0x0F87
#define mmIH_LEVEL_STATUS__VI                           0x0E37
#define mmIH_PERFCOUNTER0_RESULT__VI                    0x0E3A
#define mmIH_PERFCOUNTER1_RESULT__VI                    0x0E3B
#define mmIH_PERFMON_CNTL__VI                           0x0E39
#define mmIH_RB_BASE__SI__CI                            0x0F81
#define mmIH_RB_BASE__VI                                0x0E31
#define mmIH_RB_CNTL__SI__CI                            0x0F80
#define mmIH_RB_CNTL__VI                                0x0E30
#define mmIH_RB_RPTR__SI__CI                            0x0F82
#define mmIH_RB_RPTR__VI                                0x0E32
#define mmIH_RB_WPTR__SI__CI                            0x0F83
#define mmIH_RB_WPTR__VI                                0x0E33
#define mmIH_RB_WPTR_ADDR_HI__SI__CI                    0x0F84
#define mmIH_RB_WPTR_ADDR_HI__VI                        0x0E34
#define mmIH_RB_WPTR_ADDR_LO__SI__CI                    0x0F85
#define mmIH_RB_WPTR_ADDR_LO__VI                        0x0E35
#define mmIH_RESET_INCOMPLETE_INT_CNTL__VI              0x0E4A
#define mmIH_STATUS__SI__CI                             0x0F88
#define mmIH_STATUS__VI                                 0x0E38
#define mmIH_VERSION__VI                                0x0E48
#define mmIH_VF_ENABLE__VI                              0x0E45
#define mmIH_VF_RB_BIF_STATUS__VI                       0x0E47
#define mmIH_VF_RB_STATUS__VI                           0x0E44
#define mmIH_VIRT_RESET_REQ__VI                         0x0E46
#define mmIH_VMID_0_LUT__VI                             0x0E00
#define mmIH_VMID_10_LUT__VI                            0x0E0A
#define mmIH_VMID_11_LUT__VI                            0x0E0B
#define mmIH_VMID_12_LUT__VI                            0x0E0C
#define mmIH_VMID_13_LUT__VI                            0x0E0D
#define mmIH_VMID_14_LUT__VI                            0x0E0E
#define mmIH_VMID_15_LUT__VI                            0x0E0F
#define mmIH_VMID_1_LUT__VI                             0x0E01
#define mmIH_VMID_2_LUT__VI                             0x0E02
#define mmIH_VMID_3_LUT__VI                             0x0E03
#define mmIH_VMID_4_LUT__VI                             0x0E04
#define mmIH_VMID_5_LUT__VI                             0x0E05
#define mmIH_VMID_6_LUT__VI                             0x0E06
#define mmIH_VMID_7_LUT__VI                             0x0E07
#define mmIH_VMID_8_LUT__VI                             0x0E08
#define mmIH_VMID_9_LUT__VI                             0x0E09
#define mmINPUT_CSC_C11_C12__VI                         0x1A36
#define mmINPUT_CSC_C11_C12_A__VI                       0x46A6
#define mmINPUT_CSC_C11_C12_B__VI                       0x46AC
#define mmINPUT_CSC_C13_C14__VI                         0x1A37
#define mmINPUT_CSC_C13_C14_A__VI                       0x46A7
#define mmINPUT_CSC_C13_C14_B__VI                       0x46AD
#define mmINPUT_CSC_C21_C22__VI                         0x1A38
#define mmINPUT_CSC_C21_C22_A__VI                       0x46A8
#define mmINPUT_CSC_C21_C22_B__VI                       0x46AE
#define mmINPUT_CSC_C23_C24__VI                         0x1A39
#define mmINPUT_CSC_C23_C24_A__VI                       0x46A9
#define mmINPUT_CSC_C23_C24_B__VI                       0x46AF
#define mmINPUT_CSC_C31_C32__VI                         0x1A3A
#define mmINPUT_CSC_C31_C32_A__VI                       0x46AA
#define mmINPUT_CSC_C31_C32_B__VI                       0x46B0
#define mmINPUT_CSC_C33_C34__VI                         0x1A3B
#define mmINPUT_CSC_C33_C34_A__VI                       0x46AB
#define mmINPUT_CSC_C33_C34_B__VI                       0x46B1
#define mmINPUT_CSC_CONTROL__VI                         0x1A35
#define mmINPUT_GAMMA_CONTROL__VI                       0x1A10
#define mmKEY_CONTROL__VI                               0x1A53
#define mmKEY_RANGE_ALPHA__VI                           0x1A54
#define mmKEY_RANGE_BLUE__VI                            0x1A57
#define mmKEY_RANGE_GREEN__VI                           0x1A56
#define mmKEY_RANGE_RED__VI                             0x1A55
#define mmLB0_DC_MVP_LB_CONTROL__VI                     0x1AE3
#define mmLB0_LB_BLACK_KEYER_B_CB__VI                   0x1ACF
#define mmLB0_LB_BLACK_KEYER_G_Y__VI                    0x1ACE
#define mmLB0_LB_BLACK_KEYER_R_CR__VI                   0x1ACD
#define mmLB0_LB_BUFFER_LEVEL_STATUS__VI                0x1AD7
#define mmLB0_LB_BUFFER_STATUS__VI                      0x1ADA
#define mmLB0_LB_BUFFER_URGENCY_CTRL__VI                0x1AD8
#define mmLB0_LB_BUFFER_URGENCY_STATUS__VI              0x1AD9
#define mmLB0_LB_DATA_FORMAT__VI                        0x1AC0
#define mmLB0_LB_DEBUG__VI                              0x1AE4
#define mmLB0_LB_DEBUG2__VI                             0x1AE5
#define mmLB0_LB_DEBUG3__VI                             0x1AE6
#define mmLB0_LB_DESKTOP_HEIGHT__VI                     0x1AC3
#define mmLB0_LB_INTERRUPT_MASK__VI                     0x1AC8
#define mmLB0_LB_KEYER_COLOR_B_CB__VI                   0x1AD3
#define mmLB0_LB_KEYER_COLOR_CTRL__VI                   0x1AD0
#define mmLB0_LB_KEYER_COLOR_G_Y__VI                    0x1AD2
#define mmLB0_LB_KEYER_COLOR_REP_B_CB__VI               0x1AD6
#define mmLB0_LB_KEYER_COLOR_REP_G_Y__VI                0x1AD5
#define mmLB0_LB_KEYER_COLOR_REP_R_CR__VI               0x1AD4
#define mmLB0_LB_KEYER_COLOR_R_CR__VI                   0x1AD1
#define mmLB0_LB_MEMORY_CTRL__VI                        0x1AC1
#define mmLB0_LB_MEMORY_SIZE_STATUS__VI                 0x1AC2
#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS__VI          0x1ADC
#define mmLB0_LB_SNAPSHOT_V_COUNTER__VI                 0x1AC7
#define mmLB0_LB_SYNC_RESET_SEL__VI                     0x1ACC
#define mmLB0_LB_VBLANK_STATUS__VI                      0x1ACB
#define mmLB0_LB_VLINE2_START_END__VI                   0x1AC5
#define mmLB0_LB_VLINE2_STATUS__VI                      0x1ACA
#define mmLB0_LB_VLINE_START_END__VI                    0x1AC4
#define mmLB0_LB_VLINE_STATUS__VI                       0x1AC9
#define mmLB0_LB_V_COUNTER__VI                          0x1AC6
#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL__VI                0x1AE1
#define mmLB0_MVP_AFR_FLIP_MODE__VI                     0x1AE0
#define mmLB0_MVP_FLIP_LINE_NUM_INSERT__VI              0x1AE2
#define mmLB1_DC_MVP_LB_CONTROL__VI                     0x1CE3
#define mmLB1_LB_BLACK_KEYER_B_CB__VI                   0x1CCF
#define mmLB1_LB_BLACK_KEYER_G_Y__VI                    0x1CCE
#define mmLB1_LB_BLACK_KEYER_R_CR__VI                   0x1CCD
#define mmLB1_LB_BUFFER_LEVEL_STATUS__VI                0x1CD7
#define mmLB1_LB_BUFFER_STATUS__VI                      0x1CDA
#define mmLB1_LB_BUFFER_URGENCY_CTRL__VI                0x1CD8
#define mmLB1_LB_BUFFER_URGENCY_STATUS__VI              0x1CD9
#define mmLB1_LB_DATA_FORMAT__VI                        0x1CC0
#define mmLB1_LB_DEBUG__VI                              0x1CE4
#define mmLB1_LB_DEBUG2__VI                             0x1CE5
#define mmLB1_LB_DEBUG3__VI                             0x1CE6
#define mmLB1_LB_DESKTOP_HEIGHT__VI                     0x1CC3
#define mmLB1_LB_INTERRUPT_MASK__VI                     0x1CC8
#define mmLB1_LB_KEYER_COLOR_B_CB__VI                   0x1CD3
#define mmLB1_LB_KEYER_COLOR_CTRL__VI                   0x1CD0
#define mmLB1_LB_KEYER_COLOR_G_Y__VI                    0x1CD2
#define mmLB1_LB_KEYER_COLOR_REP_B_CB__VI               0x1CD6
#define mmLB1_LB_KEYER_COLOR_REP_G_Y__VI                0x1CD5
#define mmLB1_LB_KEYER_COLOR_REP_R_CR__VI               0x1CD4
#define mmLB1_LB_KEYER_COLOR_R_CR__VI                   0x1CD1
#define mmLB1_LB_MEMORY_CTRL__VI                        0x1CC1
#define mmLB1_LB_MEMORY_SIZE_STATUS__VI                 0x1CC2
#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS__VI          0x1CDC
#define mmLB1_LB_SNAPSHOT_V_COUNTER__VI                 0x1CC7
#define mmLB1_LB_SYNC_RESET_SEL__VI                     0x1CCC
#define mmLB1_LB_TEST_DEBUG_DATA__VI                    0x1CFF
#define mmLB1_LB_TEST_DEBUG_INDEX__VI                   0x1CFE
#define mmLB1_LB_VBLANK_STATUS__VI                      0x1CCB
#define mmLB1_LB_VLINE2_START_END__VI                   0x1CC5
#define mmLB1_LB_VLINE2_STATUS__VI                      0x1CCA
#define mmLB1_LB_VLINE_START_END__VI                    0x1CC4
#define mmLB1_LB_VLINE_STATUS__VI                       0x1CC9
#define mmLB1_LB_V_COUNTER__VI                          0x1CC6
#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL__VI                0x1CE1
#define mmLB1_MVP_AFR_FLIP_MODE__VI                     0x1CE0
#define mmLB1_MVP_FLIP_LINE_NUM_INSERT__VI              0x1CE2
#define mmLB2_DC_MVP_LB_CONTROL__VI                     0x1EE3
#define mmLB2_LB_BLACK_KEYER_B_CB__VI                   0x1ECF
#define mmLB2_LB_BLACK_KEYER_G_Y__VI                    0x1ECE
#define mmLB2_LB_BLACK_KEYER_R_CR__VI                   0x1ECD
#define mmLB2_LB_BUFFER_LEVEL_STATUS__VI                0x1ED7
#define mmLB2_LB_BUFFER_STATUS__VI                      0x1EDA
#define mmLB2_LB_BUFFER_URGENCY_CTRL__VI                0x1ED8
#define mmLB2_LB_BUFFER_URGENCY_STATUS__VI              0x1ED9
#define mmLB2_LB_DATA_FORMAT__VI                        0x1EC0
#define mmLB2_LB_DEBUG__VI                              0x1EE4
#define mmLB2_LB_DEBUG2__VI                             0x1EE5
#define mmLB2_LB_DEBUG3__VI                             0x1EE6
#define mmLB2_LB_DESKTOP_HEIGHT__VI                     0x1EC3
#define mmLB2_LB_INTERRUPT_MASK__VI                     0x1EC8
#define mmLB2_LB_KEYER_COLOR_B_CB__VI                   0x1ED3
#define mmLB2_LB_KEYER_COLOR_CTRL__VI                   0x1ED0
#define mmLB2_LB_KEYER_COLOR_G_Y__VI                    0x1ED2
#define mmLB2_LB_KEYER_COLOR_REP_B_CB__VI               0x1ED6
#define mmLB2_LB_KEYER_COLOR_REP_G_Y__VI                0x1ED5
#define mmLB2_LB_KEYER_COLOR_REP_R_CR__VI               0x1ED4
#define mmLB2_LB_KEYER_COLOR_R_CR__VI                   0x1ED1
#define mmLB2_LB_MEMORY_CTRL__VI                        0x1EC1
#define mmLB2_LB_MEMORY_SIZE_STATUS__VI                 0x1EC2
#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS__VI          0x1EDC
#define mmLB2_LB_SNAPSHOT_V_COUNTER__VI                 0x1EC7
#define mmLB2_LB_SYNC_RESET_SEL__VI                     0x1ECC
#define mmLB2_LB_TEST_DEBUG_DATA__VI                    0x1EFF
#define mmLB2_LB_TEST_DEBUG_INDEX__VI                   0x1EFE
#define mmLB2_LB_VBLANK_STATUS__VI                      0x1ECB
#define mmLB2_LB_VLINE2_START_END__VI                   0x1EC5
#define mmLB2_LB_VLINE2_STATUS__VI                      0x1ECA
#define mmLB2_LB_VLINE_START_END__VI                    0x1EC4
#define mmLB2_LB_VLINE_STATUS__VI                       0x1EC9
#define mmLB2_LB_V_COUNTER__VI                          0x1EC6
#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL__VI                0x1EE1
#define mmLB2_MVP_AFR_FLIP_MODE__VI                     0x1EE0
#define mmLB2_MVP_FLIP_LINE_NUM_INSERT__VI              0x1EE2
#define mmLB3_DC_MVP_LB_CONTROL__VI                     0x40E3
#define mmLB3_LB_BLACK_KEYER_B_CB__VI                   0x40CF
#define mmLB3_LB_BLACK_KEYER_G_Y__VI                    0x40CE
#define mmLB3_LB_BLACK_KEYER_R_CR__VI                   0x40CD
#define mmLB3_LB_BUFFER_LEVEL_STATUS__VI                0x40D7
#define mmLB3_LB_BUFFER_STATUS__VI                      0x40DA
#define mmLB3_LB_BUFFER_URGENCY_CTRL__VI                0x40D8
#define mmLB3_LB_BUFFER_URGENCY_STATUS__VI              0x40D9
#define mmLB3_LB_DATA_FORMAT__VI                        0x40C0
#define mmLB3_LB_DEBUG__VI                              0x40E4
#define mmLB3_LB_DEBUG2__VI                             0x40E5
#define mmLB3_LB_DEBUG3__VI                             0x40E6
#define mmLB3_LB_DESKTOP_HEIGHT__VI                     0x40C3
#define mmLB3_LB_INTERRUPT_MASK__VI                     0x40C8
#define mmLB3_LB_KEYER_COLOR_B_CB__VI                   0x40D3
#define mmLB3_LB_KEYER_COLOR_CTRL__VI                   0x40D0
#define mmLB3_LB_KEYER_COLOR_G_Y__VI                    0x40D2
#define mmLB3_LB_KEYER_COLOR_REP_B_CB__VI               0x40D6
#define mmLB3_LB_KEYER_COLOR_REP_G_Y__VI                0x40D5
#define mmLB3_LB_KEYER_COLOR_REP_R_CR__VI               0x40D4
#define mmLB3_LB_KEYER_COLOR_R_CR__VI                   0x40D1
#define mmLB3_LB_MEMORY_CTRL__VI                        0x40C1
#define mmLB3_LB_MEMORY_SIZE_STATUS__VI                 0x40C2
#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS__VI          0x40DC
#define mmLB3_LB_SNAPSHOT_V_COUNTER__VI                 0x40C7
#define mmLB3_LB_SYNC_RESET_SEL__VI                     0x40CC
#define mmLB3_LB_TEST_DEBUG_DATA__VI                    0x40FF
#define mmLB3_LB_TEST_DEBUG_INDEX__VI                   0x40FE
#define mmLB3_LB_VBLANK_STATUS__VI                      0x40CB
#define mmLB3_LB_VLINE2_START_END__VI                   0x40C5
#define mmLB3_LB_VLINE2_STATUS__VI                      0x40CA
#define mmLB3_LB_VLINE_START_END__VI                    0x40C4
#define mmLB3_LB_VLINE_STATUS__VI                       0x40C9
#define mmLB3_LB_V_COUNTER__VI                          0x40C6
#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL__VI                0x40E1
#define mmLB3_MVP_AFR_FLIP_MODE__VI                     0x40E0
#define mmLB3_MVP_FLIP_LINE_NUM_INSERT__VI              0x40E2
#define mmLB4_DC_MVP_LB_CONTROL__VI                     0x42E3
#define mmLB4_LB_BLACK_KEYER_B_CB__VI                   0x42CF
#define mmLB4_LB_BLACK_KEYER_G_Y__VI                    0x42CE
#define mmLB4_LB_BLACK_KEYER_R_CR__VI                   0x42CD
#define mmLB4_LB_BUFFER_LEVEL_STATUS__VI                0x42D7
#define mmLB4_LB_BUFFER_STATUS__VI                      0x42DA
#define mmLB4_LB_BUFFER_URGENCY_CTRL__VI                0x42D8
#define mmLB4_LB_BUFFER_URGENCY_STATUS__VI              0x42D9
#define mmLB4_LB_DATA_FORMAT__VI                        0x42C0
#define mmLB4_LB_DEBUG__VI                              0x42E4
#define mmLB4_LB_DEBUG2__VI                             0x42E5
#define mmLB4_LB_DEBUG3__VI                             0x42E6
#define mmLB4_LB_DESKTOP_HEIGHT__VI                     0x42C3
#define mmLB4_LB_INTERRUPT_MASK__VI                     0x42C8
#define mmLB4_LB_KEYER_COLOR_B_CB__VI                   0x42D3
#define mmLB4_LB_KEYER_COLOR_CTRL__VI                   0x42D0
#define mmLB4_LB_KEYER_COLOR_G_Y__VI                    0x42D2
#define mmLB4_LB_KEYER_COLOR_REP_B_CB__VI               0x42D6
#define mmLB4_LB_KEYER_COLOR_REP_G_Y__VI                0x42D5
#define mmLB4_LB_KEYER_COLOR_REP_R_CR__VI               0x42D4
#define mmLB4_LB_KEYER_COLOR_R_CR__VI                   0x42D1
#define mmLB4_LB_MEMORY_CTRL__VI                        0x42C1
#define mmLB4_LB_MEMORY_SIZE_STATUS__VI                 0x42C2
#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS__VI          0x42DC
#define mmLB4_LB_SNAPSHOT_V_COUNTER__VI                 0x42C7
#define mmLB4_LB_SYNC_RESET_SEL__VI                     0x42CC
#define mmLB4_LB_TEST_DEBUG_DATA__VI                    0x42FF
#define mmLB4_LB_TEST_DEBUG_INDEX__VI                   0x42FE
#define mmLB4_LB_VBLANK_STATUS__VI                      0x42CB
#define mmLB4_LB_VLINE2_START_END__VI                   0x42C5
#define mmLB4_LB_VLINE2_STATUS__VI                      0x42CA
#define mmLB4_LB_VLINE_START_END__VI                    0x42C4
#define mmLB4_LB_VLINE_STATUS__VI                       0x42C9
#define mmLB4_LB_V_COUNTER__VI                          0x42C6
#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL__VI                0x42E1
#define mmLB4_MVP_AFR_FLIP_MODE__VI                     0x42E0
#define mmLB4_MVP_FLIP_LINE_NUM_INSERT__VI              0x42E2
#define mmLB5_DC_MVP_LB_CONTROL__VI                     0x44E3
#define mmLB5_LB_BLACK_KEYER_B_CB__VI                   0x44CF
#define mmLB5_LB_BLACK_KEYER_G_Y__VI                    0x44CE
#define mmLB5_LB_BLACK_KEYER_R_CR__VI                   0x44CD
#define mmLB5_LB_BUFFER_LEVEL_STATUS__VI                0x44D7
#define mmLB5_LB_BUFFER_STATUS__VI                      0x44DA
#define mmLB5_LB_BUFFER_URGENCY_CTRL__VI                0x44D8
#define mmLB5_LB_BUFFER_URGENCY_STATUS__VI              0x44D9
#define mmLB5_LB_DATA_FORMAT__VI                        0x44C0
#define mmLB5_LB_DEBUG__VI                              0x44E4
#define mmLB5_LB_DEBUG2__VI                             0x44E5
#define mmLB5_LB_DEBUG3__VI                             0x44E6
#define mmLB5_LB_DESKTOP_HEIGHT__VI                     0x44C3
#define mmLB5_LB_INTERRUPT_MASK__VI                     0x44C8
#define mmLB5_LB_KEYER_COLOR_B_CB__VI                   0x44D3
#define mmLB5_LB_KEYER_COLOR_CTRL__VI                   0x44D0
#define mmLB5_LB_KEYER_COLOR_G_Y__VI                    0x44D2
#define mmLB5_LB_KEYER_COLOR_REP_B_CB__VI               0x44D6
#define mmLB5_LB_KEYER_COLOR_REP_G_Y__VI                0x44D5
#define mmLB5_LB_KEYER_COLOR_REP_R_CR__VI               0x44D4
#define mmLB5_LB_KEYER_COLOR_R_CR__VI                   0x44D1
#define mmLB5_LB_MEMORY_CTRL__VI                        0x44C1
#define mmLB5_LB_MEMORY_SIZE_STATUS__VI                 0x44C2
#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS__VI          0x44DC
#define mmLB5_LB_SNAPSHOT_V_COUNTER__VI                 0x44C7
#define mmLB5_LB_SYNC_RESET_SEL__VI                     0x44CC
#define mmLB5_LB_TEST_DEBUG_DATA__VI                    0x44FF
#define mmLB5_LB_TEST_DEBUG_INDEX__VI                   0x44FE
#define mmLB5_LB_VBLANK_STATUS__VI                      0x44CB
#define mmLB5_LB_VLINE2_START_END__VI                   0x44C5
#define mmLB5_LB_VLINE2_STATUS__VI                      0x44CA
#define mmLB5_LB_VLINE_START_END__VI                    0x44C4
#define mmLB5_LB_VLINE_STATUS__VI                       0x44C9
#define mmLB5_LB_V_COUNTER__VI                          0x44C6
#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL__VI                0x44E1
#define mmLB5_MVP_AFR_FLIP_MODE__VI                     0x44E0
#define mmLB5_MVP_FLIP_LINE_NUM_INSERT__VI              0x44E2
#define mmLBV_BLACK_KEYER_B_CB__VI                      0x464D
#define mmLBV_BLACK_KEYER_G_Y__VI                       0x464C
#define mmLBV_BLACK_KEYER_R_CR__VI                      0x464B
#define mmLBV_BUFFER_LEVEL_STATUS__VI                   0x4655
#define mmLBV_BUFFER_STATUS__VI                         0x4658
#define mmLBV_BUFFER_URGENCY_CTRL__VI                   0x4656
#define mmLBV_BUFFER_URGENCY_STATUS__VI                 0x4657
#define mmLBV_DATA_FORMAT__VI                           0x463C
#define mmLBV_DEBUG__VI                                 0x465A
#define mmLBV_DEBUG2__VI                                0x465B
#define mmLBV_DEBUG3__VI                                0x465C
#define mmLBV_DESKTOP_HEIGHT__VI                        0x463F
#define mmLBV_INTERRUPT_MASK__VI                        0x4646
#define mmLBV_KEYER_COLOR_B_CB__VI                      0x4651
#define mmLBV_KEYER_COLOR_CTRL__VI                      0x464E
#define mmLBV_KEYER_COLOR_G_Y__VI                       0x4650
#define mmLBV_KEYER_COLOR_REP_B_CB__VI                  0x4654
#define mmLBV_KEYER_COLOR_REP_G_Y__VI                   0x4653
#define mmLBV_KEYER_COLOR_REP_R_CR__VI                  0x4652
#define mmLBV_KEYER_COLOR_R_CR__VI                      0x464F
#define mmLBV_MEMORY_CTRL__VI                           0x463D
#define mmLBV_MEMORY_SIZE_STATUS__VI                    0x463E
#define mmLBV_NO_OUTSTANDING_REQ_STATUS__VI             0x4659
#define mmLBV_SNAPSHOT_V_COUNTER__VI                    0x4643
#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA__VI             0x4645
#define mmLBV_SYNC_RESET_SEL__VI                        0x464A
#define mmLBV_TEST_DEBUG_DATA__VI                       0x4667
#define mmLBV_TEST_DEBUG_INDEX__VI                      0x4666
#define mmLBV_VBLANK_STATUS__VI                         0x4649
#define mmLBV_VLINE2_START_END__VI                      0x4641
#define mmLBV_VLINE2_STATUS__VI                         0x4648
#define mmLBV_VLINE_START_END__VI                       0x4640
#define mmLBV_VLINE_STATUS__VI                          0x4647
#define mmLBV_V_COUNTER__VI                             0x4642
#define mmLBV_V_COUNTER_CHROMA__VI                      0x4644
#define mmLB_BLACK_KEYER_B_CB__VI                       0x1ACF
#define mmLB_BLACK_KEYER_G_Y__VI                        0x1ACE
#define mmLB_BLACK_KEYER_R_CR__VI                       0x1ACD
#define mmLB_BUFFER_LEVEL_STATUS__VI                    0x1AD7
#define mmLB_BUFFER_STATUS__VI                          0x1ADA
#define mmLB_BUFFER_URGENCY_CTRL__VI                    0x1AD8
#define mmLB_BUFFER_URGENCY_STATUS__VI                  0x1AD9
#define mmLB_DATA_FORMAT__VI                            0x1AC0
#define mmLB_DEBUG__VI                                  0x1AE4
#define mmLB_DEBUG2__VI                                 0x1AE5
#define mmLB_DEBUG3__VI                                 0x1AE6
#define mmLB_DESKTOP_HEIGHT__VI                         0x1AC3
#define mmLB_INTERRUPT_MASK__VI                         0x1AC8
#define mmLB_KEYER_COLOR_B_CB__VI                       0x1AD3
#define mmLB_KEYER_COLOR_CTRL__VI                       0x1AD0
#define mmLB_KEYER_COLOR_G_Y__VI                        0x1AD2
#define mmLB_KEYER_COLOR_REP_B_CB__VI                   0x1AD6
#define mmLB_KEYER_COLOR_REP_G_Y__VI                    0x1AD5
#define mmLB_KEYER_COLOR_REP_R_CR__VI                   0x1AD4
#define mmLB_KEYER_COLOR_R_CR__VI                       0x1AD1
#define mmLB_MEMORY_CTRL__VI                            0x1AC1
#define mmLB_MEMORY_SIZE_STATUS__VI                     0x1AC2
#define mmLB_NO_OUTSTANDING_REQ_STATUS__VI              0x1ADC
#define mmLB_SNAPSHOT_V_COUNTER__VI                     0x1AC7
#define mmLB_SYNC_RESET_SEL__VI                         0x1ACC
#define mmLB_VBLANK_STATUS__VI                          0x1ACB
#define mmLB_VLINE2_START_END__VI                       0x1AC5
#define mmLB_VLINE2_STATUS__VI                          0x1ACA
#define mmLB_VLINE_START_END__VI                        0x1AC4
#define mmLB_VLINE_STATUS__VI                           0x1AC9
#define mmLB_V_COUNTER__VI                              0x1AC6
#define mmLOW_POWER_TILING_CONTROL__VI                  0x030B
#define mmLVDS_DATA_CNTL__VI                            0x4A78
#define mmLVTMA_PWRSEQ_CNTL__VI                         0x481B
#define mmLVTMA_PWRSEQ_DELAY1__VI                       0x481E
#define mmLVTMA_PWRSEQ_DELAY2__VI                       0x481F
#define mmLVTMA_PWRSEQ_REF_DIV__VI                      0x481D
#define mmLVTMA_PWRSEQ_STATE__VI                        0x481C
#define mmMAILBOX_CONTROL__VI                           0x14D0
#define mmMAILBOX_INDEX__VI                             0x14C6
#define mmMAILBOX_INT_CNTL__VI                          0x14D1
#define mmMAILBOX_MSGBUF_RCV_DW0__VI                    0x14CC
#define mmMAILBOX_MSGBUF_RCV_DW1__VI                    0x14CD
#define mmMAILBOX_MSGBUF_RCV_DW2__VI                    0x14CE
#define mmMAILBOX_MSGBUF_RCV_DW3__VI                    0x14CF
#define mmMAILBOX_MSGBUF_TRN_DW0__VI                    0x14C8
#define mmMAILBOX_MSGBUF_TRN_DW1__VI                    0x14C9
#define mmMAILBOX_MSGBUF_TRN_DW2__VI                    0x14CA
#define mmMAILBOX_MSGBUF_TRN_DW3__VI                    0x14CB
#define mmMCIF_CONTROL__VI                              0x030C
#define mmMCIF_MEM_CONTROL__VI                          0x0311
#define mmMCIF_TEST_DEBUG_DATA__VI                      0x030F
#define mmMCIF_TEST_DEBUG_INDEX__VI                     0x030E
#define mmMCIF_VMID__VI                                 0x0310
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__VI      0x5E84
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__VI        0x5E79
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS__VI            0x5E7A
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__VI        0x5E78
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__VI       0x5E98
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C__VI             0x5E8A
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__VI      0x5E8B
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__VI             0x5E88
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI      0x5E89
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS__VI             0x5E7C
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2__VI            0x5E7D
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C__VI             0x5E8E
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__VI      0x5E8F
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__VI             0x5E8C
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI      0x5E8D
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS__VI             0x5E7E
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2__VI            0x5E7F
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C__VI             0x5E92
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__VI      0x5E93
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__VI             0x5E90
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI      0x5E91
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS__VI             0x5E80
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2__VI            0x5E81
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C__VI             0x5E96
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__VI      0x5E97
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__VI             0x5E94
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI      0x5E95
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS__VI             0x5E82
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2__VI            0x5E83
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH__VI                0x5E7B
#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL__VI           0x5E99
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__VI          0x5E87
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__VI         0x5E86
#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK__VI        0x5E85
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__VI      0x5EC4
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__VI        0x5EB9
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS__VI            0x5EBA
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__VI        0x5EB8
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__VI       0x5ED8
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C__VI             0x5ECA
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__VI      0x5ECB
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__VI             0x5EC8
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI      0x5EC9
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS__VI             0x5EBC
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2__VI            0x5EBD
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C__VI             0x5ECE
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__VI      0x5ECF
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__VI             0x5ECC
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI      0x5ECD
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS__VI             0x5EBE
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2__VI            0x5EBF
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C__VI             0x5ED2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__VI      0x5ED3
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__VI             0x5ED0
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI      0x5ED1
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS__VI             0x5EC0
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2__VI            0x5EC1
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C__VI             0x5ED6
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__VI      0x5ED7
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__VI             0x5ED4
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI      0x5ED5
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS__VI             0x5EC2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2__VI            0x5EC3
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH__VI                0x5EBB
#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL__VI           0x5ED9
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__VI          0x5EC7
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__VI         0x5EC6
#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK__VI        0x5EC5
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__VI      0x5F04
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__VI        0x5EF9
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS__VI            0x5EFA
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__VI        0x5EF8
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__VI       0x5F18
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C__VI             0x5F0A
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__VI      0x5F0B
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__VI             0x5F08
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI      0x5F09
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS__VI             0x5EFC
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2__VI            0x5EFD
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C__VI             0x5F0E
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__VI      0x5F0F
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__VI             0x5F0C
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI      0x5F0D
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS__VI             0x5EFE
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2__VI            0x5EFF
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C__VI             0x5F12
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__VI      0x5F13
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__VI             0x5F10
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI      0x5F11
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS__VI             0x5F00
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2__VI            0x5F01
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C__VI             0x5F16
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__VI      0x5F17
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__VI             0x5F14
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI      0x5F15
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS__VI             0x5F02
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2__VI            0x5F03
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH__VI                0x5EFB
#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL__VI           0x5F19
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__VI          0x5F07
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__VI         0x5F06
#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK__VI        0x5F05
#define mmMCIF_WB_ARBITRATION_CONTROL__VI               0x5E84
#define mmMCIF_WB_BUFMGR_CUR_LINE_R__VI                 0x5E79
#define mmMCIF_WB_BUFMGR_STATUS__VI                     0x5E7A
#define mmMCIF_WB_BUFMGR_SW_CONTROL__VI                 0x5E78
#define mmMCIF_WB_BUFMGR_VCE_CONTROL__VI                0x5E98
#define mmMCIF_WB_BUF_1_ADDR_C__VI                      0x5E8A
#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET__VI               0x5E8B
#define mmMCIF_WB_BUF_1_ADDR_Y__VI                      0x5E88
#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET__VI               0x5E89
#define mmMCIF_WB_BUF_1_STATUS__VI                      0x5E7C
#define mmMCIF_WB_BUF_1_STATUS2__VI                     0x5E7D
#define mmMCIF_WB_BUF_2_ADDR_C__VI                      0x5E8E
#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET__VI               0x5E8F
#define mmMCIF_WB_BUF_2_ADDR_Y__VI                      0x5E8C
#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET__VI               0x5E8D
#define mmMCIF_WB_BUF_2_STATUS__VI                      0x5E7E
#define mmMCIF_WB_BUF_2_STATUS2__VI                     0x5E7F
#define mmMCIF_WB_BUF_3_ADDR_C__VI                      0x5E92
#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET__VI               0x5E93
#define mmMCIF_WB_BUF_3_ADDR_Y__VI                      0x5E90
#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET__VI               0x5E91
#define mmMCIF_WB_BUF_3_STATUS__VI                      0x5E80
#define mmMCIF_WB_BUF_3_STATUS2__VI                     0x5E81
#define mmMCIF_WB_BUF_4_ADDR_C__VI                      0x5E96
#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET__VI               0x5E97
#define mmMCIF_WB_BUF_4_ADDR_Y__VI                      0x5E94
#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET__VI               0x5E95
#define mmMCIF_WB_BUF_4_STATUS__VI                      0x5E82
#define mmMCIF_WB_BUF_4_STATUS2__VI                     0x5E83
#define mmMCIF_WB_BUF_PITCH__VI                         0x5E7B
#define mmMCIF_WB_HVVMID_CONTROL__VI                    0x5E99
#define mmMCIF_WB_TEST_DEBUG_DATA__VI                   0x5E87
#define mmMCIF_WB_TEST_DEBUG_INDEX__VI                  0x5E86
#define mmMCIF_WB_URGENCY_WATERMARK__VI                 0x5E85
#define mmMCIF_WRITE_COMBINE_CONTROL__VI                0x030D
#define mmMC_ARB_ATOMIC__VI                             0x09BE
#define mmMC_ARB_GRUB__VI                               0x09C8
#define mmMC_ARB_GRUB2__VI                              0x0A01
#define mmMC_ARB_GRUB_PRIORITY1_RD__VI                  0x0DD8
#define mmMC_ARB_GRUB_PRIORITY1_WR__VI                  0x0DD9
#define mmMC_ARB_GRUB_PRIORITY2_RD__VI                  0x0DDA
#define mmMC_ARB_GRUB_PRIORITY2_WR__VI                  0x0DDB
#define mmMC_ARB_GRUB_PROMOTE__VI                       0x09CE
#define mmMC_ARB_GRUB_REALTIME_RD__VI                   0x09F9
#define mmMC_ARB_GRUB_REALTIME_WR__VI                   0x09FB
#define mmMC_ARB_PERF_CID__VI                           0x09C6
#define mmMC_ARB_SNOOP__VI                              0x09C7
#define mmMC_BIST_CMD__VI                               0x0A85
#define mmMC_BIST_CNTL__SI__CI                          0x0A05
#define mmMC_BIST_CNTL__VI                              0x0A84
#define mmMC_BIST_DAT__VI                               0x0A86
#define mmMC_BIST_DATA_WORD0__SI__CI                    0x0A0A
#define mmMC_BIST_DATA_WORD0__VI                        0x0A8A
#define mmMC_BIST_DATA_WORD1__SI__CI                    0x0A0B
#define mmMC_BIST_DATA_WORD1__VI                        0x0A8B
#define mmMC_BIST_DATA_WORD2__SI__CI                    0x0A0C
#define mmMC_BIST_DATA_WORD2__VI                        0x0A8C
#define mmMC_BIST_DATA_WORD3__SI__CI                    0x0A0D
#define mmMC_BIST_DATA_WORD3__VI                        0x0A8D
#define mmMC_BIST_DATA_WORD4__SI__CI                    0x0A0E
#define mmMC_BIST_DATA_WORD4__VI                        0x0A8E
#define mmMC_BIST_DATA_WORD5__SI__CI                    0x0A0F
#define mmMC_BIST_DATA_WORD5__VI                        0x0A8F
#define mmMC_BIST_DATA_WORD6__SI__CI                    0x0A10
#define mmMC_BIST_DATA_WORD6__VI                        0x0A90
#define mmMC_BIST_DATA_WORD7__SI__CI                    0x0A11
#define mmMC_BIST_DATA_WORD7__VI                        0x0A91
#define mmMC_BIST_MISMATCH_ADDR__SI__CI                 0x0A13
#define mmMC_BIST_MISMATCH_ADDR__VI                     0x0A93
#define mmMC_BIST_RDATA_WORD0__SI__CI                   0x0A14
#define mmMC_BIST_RDATA_WORD0__VI                       0x0A94
#define mmMC_BIST_RDATA_WORD1__SI__CI                   0x0A15
#define mmMC_BIST_RDATA_WORD1__VI                       0x0A95
#define mmMC_BIST_RDATA_WORD2__SI__CI                   0x0A16
#define mmMC_BIST_RDATA_WORD2__VI                       0x0A96
#define mmMC_BIST_RDATA_WORD3__SI__CI                   0x0A17
#define mmMC_BIST_RDATA_WORD3__VI                       0x0A97
#define mmMC_BIST_RDATA_WORD4__SI__CI                   0x0A18
#define mmMC_BIST_RDATA_WORD4__VI                       0x0A98
#define mmMC_BIST_RDATA_WORD5__SI__CI                   0x0A19
#define mmMC_BIST_RDATA_WORD5__VI                       0x0A99
#define mmMC_BIST_RDATA_WORD6__SI__CI                   0x0A1A
#define mmMC_BIST_RDATA_WORD6__VI                       0x0A9A
#define mmMC_BIST_RDATA_WORD7__SI__CI                   0x0A1B
#define mmMC_BIST_RDATA_WORD7__VI                       0x0A9B
#define mmMC_CG_DATAPORT__SI__CI                        0x0A21
#define mmMC_CG_DATAPORT__VI                            0x0A32
#define mmMC_CITF_CREDITS_ARB_RD2__VI                   0x097E
#define mmMC_DC_INTERFACE_NACK_STATUS__VI               0x0313
#define mmMC_FUS_ARB_GARLIC_CNTL__VI                    0x0A20
#define mmMC_FUS_ARB_GARLIC_ISOC_PRI__VI                0x0A1F
#define mmMC_FUS_ARB_GARLIC_WR_PRI__VI                  0x0A21
#define mmMC_FUS_ARB_GARLIC_WR_PRI2__VI                 0x0A22
#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING__VI            0x0A11
#define mmMC_FUS_DRAM0_CS0_BASE__VI                     0x0A05
#define mmMC_FUS_DRAM0_CS1_BASE__VI                     0x0A07
#define mmMC_FUS_DRAM0_CS2_BASE__VI                     0x0A09
#define mmMC_FUS_DRAM0_CS3_BASE__VI                     0x0A0B
#define mmMC_FUS_DRAM0_CTL_BASE__VI                     0x0A13
#define mmMC_FUS_DRAM0_CTL_LIMIT__VI                    0x0A15
#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING__VI            0x0A12
#define mmMC_FUS_DRAM1_CS0_BASE__VI                     0x0A06
#define mmMC_FUS_DRAM1_CS1_BASE__VI                     0x0A08
#define mmMC_FUS_DRAM1_CS2_BASE__VI                     0x0A0A
#define mmMC_FUS_DRAM1_CS3_BASE__VI                     0x0A0C
#define mmMC_FUS_DRAM1_CTL_BASE__VI                     0x0A14
#define mmMC_FUS_DRAM1_CTL_LIMIT__VI                    0x0A16
#define mmMC_FUS_DRAM_APER_BASE__VI                     0x0A1A
#define mmMC_FUS_DRAM_APER_DEF__VI                      0x0A1E
#define mmMC_FUS_DRAM_APER_TOP__VI                      0x0A1B
#define mmMC_FUS_DRAM_CTL_HIGH_01__VI                   0x0A17
#define mmMC_FUS_DRAM_CTL_HIGH_23__VI                   0x0A18
#define mmMC_FUS_DRAM_MODE__VI                          0x0A19
#define mmMC_GRUB_FEATURES__VI                          0x0A36
#define mmMC_GRUB_PERFCOUNTER0_CFG__VI                  0x07E6
#define mmMC_GRUB_PERFCOUNTER1_CFG__VI                  0x07E7
#define mmMC_GRUB_PERFCOUNTER_HI__VI                    0x07E5
#define mmMC_GRUB_PERFCOUNTER_LO__VI                    0x07E4
#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL__VI             0x07E8
#define mmMC_GRUB_POST_PROBE_DELAY__VI                  0x0A34
#define mmMC_GRUB_PROBE_CREDITS__VI                     0x0A35
#define mmMC_GRUB_PROBE_MAP__VI                         0x0A33
#define mmMC_GRUB_TCB_DATA_HI__VI                       0x0A3A
#define mmMC_GRUB_TCB_DATA_LO__VI                       0x0A39
#define mmMC_GRUB_TCB_INDEX__VI                         0x0A38
#define mmMC_GRUB_TX_CREDITS__VI                        0x0A37
#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS__VI            0x084F
#define mmMC_HUB_RDREQ_ACPG__VI                         0x0881
#define mmMC_HUB_RDREQ_ACPO__VI                         0x0882
#define mmMC_HUB_RDREQ_BYPASS_GBL0__VI                  0x084C
#define mmMC_HUB_RDREQ_DMIF__VI                         0x0862
#define mmMC_HUB_RDREQ_HDP__VI                          0x085A
#define mmMC_HUB_RDREQ_ISP_CCPU__VI                     0x0DE2
#define mmMC_HUB_RDREQ_ISP_MPM__VI                      0x0DE1
#define mmMC_HUB_RDREQ_ISP_SPM__VI                      0x0DE0
#define mmMC_HUB_RDREQ_MCDS__VI                         0x0DE7
#define mmMC_HUB_RDREQ_MCDT__VI                         0x0DE8
#define mmMC_HUB_RDREQ_MCDU__VI                         0x0DE9
#define mmMC_HUB_RDREQ_MCDV__VI                         0x0DEA
#define mmMC_HUB_RDREQ_MCIF__VI                         0x0863
#define mmMC_HUB_RDREQ_RLC__VI                          0x085C
#define mmMC_HUB_RDREQ_SAMMSP__VI                       0x0883
#define mmMC_HUB_RDREQ_SDMA0__VI                        0x0859
#define mmMC_HUB_RDREQ_SDMA1__VI                        0x085B
#define mmMC_HUB_RDREQ_SEM__VI                          0x085D
#define mmMC_HUB_RDREQ_TLS__VI                          0x0861
#define mmMC_HUB_RDREQ_UMC__VI                          0x085F
#define mmMC_HUB_RDREQ_UVD__VI                          0x0860
#define mmMC_HUB_RDREQ_VCE0__VI                         0x085E
#define mmMC_HUB_RDREQ_VCE1__VI                         0x0DFC
#define mmMC_HUB_RDREQ_VCEU0__VI                        0x0865
#define mmMC_HUB_RDREQ_VCEU1__VI                        0x0DFD
#define mmMC_HUB_RDREQ_VMC__VI                          0x0864
#define mmMC_HUB_RDREQ_VP8__VI                          0x0884
#define mmMC_HUB_RDREQ_VP8U__VI                         0x0885
#define mmMC_HUB_RDREQ_XDMAM__VI                        0x0880
#define mmMC_HUB_WDP_ACPG__VI                           0x0885
#define mmMC_HUB_WDP_ACPO__VI                           0x0886
#define mmMC_HUB_WDP_BP2__VI                            0x0DFB
#define mmMC_HUB_WDP_BYPASS_GBL0__VI                    0x084A
#define mmMC_HUB_WDP_BYPASS_GBL1__VI                    0x084B
#define mmMC_HUB_WDP_CREDITS2__VI                       0x0840
#define mmMC_HUB_WDP_CREDITS3__VI                       0x0843
#define mmMC_HUB_WDP_CREDITS_MCDS__VI                   0x0DF7
#define mmMC_HUB_WDP_CREDITS_MCDT__VI                   0x0DF8
#define mmMC_HUB_WDP_CREDITS_MCDU__VI                   0x0DF9
#define mmMC_HUB_WDP_CREDITS_MCDV__VI                   0x0DFA
#define mmMC_HUB_WDP_CREDITS_MCDW__VI                   0x0DF3
#define mmMC_HUB_WDP_CREDITS_MCDX__VI                   0x0DF4
#define mmMC_HUB_WDP_CREDITS_MCDY__VI                   0x0DF5
#define mmMC_HUB_WDP_CREDITS_MCDZ__VI                   0x0DF6
#define mmMC_HUB_WDP_HDP__VI                            0x0877
#define mmMC_HUB_WDP_IH__VI                             0x0870
#define mmMC_HUB_WDP_ISP_CCPU__VI                       0x0DE6
#define mmMC_HUB_WDP_ISP_MPM__VI                        0x0DE5
#define mmMC_HUB_WDP_ISP_MPS__VI                        0x0DE4
#define mmMC_HUB_WDP_ISP_SPM__VI                        0x0DE3
#define mmMC_HUB_WDP_MCDS__VI                           0x0DEB
#define mmMC_HUB_WDP_MCDT__VI                           0x0DEC
#define mmMC_HUB_WDP_MCDU__VI                           0x0DED
#define mmMC_HUB_WDP_MCDV__VI                           0x0DEE
#define mmMC_HUB_WDP_MCDW__VI                           0x0866
#define mmMC_HUB_WDP_MCDX__VI                           0x0867
#define mmMC_HUB_WDP_MCDY__VI                           0x0868
#define mmMC_HUB_WDP_MCDZ__VI                           0x0869
#define mmMC_HUB_WDP_MCIF__VI                           0x086D
#define mmMC_HUB_WDP_RLC__VI                            0x0871
#define mmMC_HUB_WDP_SAMMSP__VI                         0x0887
#define mmMC_HUB_WDP_SDMA0__VI                          0x0878
#define mmMC_HUB_WDP_SDMA1__VI                          0x086B
#define mmMC_HUB_WDP_SEM__VI                            0x0872
#define mmMC_HUB_WDP_SH0__VI                            0x086C
#define mmMC_HUB_WDP_SH1__VI                            0x0874
#define mmMC_HUB_WDP_SIP__VI                            0x086A
#define mmMC_HUB_WDP_SMU__VI                            0x0873
#define mmMC_HUB_WDP_UMC__VI                            0x0875
#define mmMC_HUB_WDP_UVD__VI                            0x0876
#define mmMC_HUB_WDP_VCE0__VI                           0x086E
#define mmMC_HUB_WDP_VCE1__VI                           0x0DFE
#define mmMC_HUB_WDP_VCEU0__VI                          0x087D
#define mmMC_HUB_WDP_VCEU1__VI                          0x0DFF
#define mmMC_HUB_WDP_VIN0__VI                           0x0850
#define mmMC_HUB_WDP_VP8__VI                            0x0888
#define mmMC_HUB_WDP_VP8U__VI                           0x088A
#define mmMC_HUB_WDP_XDMA__VI                           0x087F
#define mmMC_HUB_WDP_XDMAM__VI                          0x087E
#define mmMC_HUB_WDP_XDP__VI                            0x086F
#define mmMC_HUB_WRRET_MCDS__VI                         0x0DEF
#define mmMC_HUB_WRRET_MCDT__VI                         0x0DF0
#define mmMC_HUB_WRRET_MCDU__VI                         0x0DF1
#define mmMC_HUB_WRRET_MCDV__VI                         0x0DF2
#define mmMC_HUB_WRRET_MCDW__VI                         0x0879
#define mmMC_HUB_WRRET_MCDX__VI                         0x087A
#define mmMC_HUB_WRRET_MCDY__VI                         0x087B
#define mmMC_HUB_WRRET_MCDZ__VI                         0x087C
#define mmMC_PMG_CFG__SI__CI                            0x0A84
#define mmMC_PMG_CFG__VI                                0x0A54
#define mmMC_PMG_CMD_EMRS__SI__CI                       0x0A83
#define mmMC_PMG_CMD_EMRS__VI                           0x0A4A
#define mmMC_PMG_CMD_MRS__SI__CI                        0x0AAB
#define mmMC_PMG_CMD_MRS__VI                            0x0A4C
#define mmMC_PMG_CMD_MRS1__SI__CI                       0x0AD1
#define mmMC_PMG_CMD_MRS1__VI                           0x0A4E
#define mmMC_PMG_CMD_MRS2__SI__CI                       0x0AD7
#define mmMC_PMG_CMD_MRS2__VI                           0x0A50
#define mmMC_RPB_TCI_CNTL__VI                           0x095C
#define mmMC_RPB_TCI_CNTL2__VI                          0x095D
#define mmMC_SEQ_CAS_TIMING__SI__CI                     0x0A29
#define mmMC_SEQ_CAS_TIMING__VI                         0x0A2B
#define mmMC_SEQ_CAS_TIMING_LP__SI__CI                  0x0A9C
#define mmMC_SEQ_CAS_TIMING_LP__VI                      0x0A2C
#define mmMC_SEQ_CG__SI__CI                             0x0A9A
#define mmMC_SEQ_CG__VI                                 0x0A7B
#define mmMC_SEQ_CMD__SI__CI                            0x0A31
#define mmMC_SEQ_CMD__VI                                0x0A47
#define mmMC_SEQ_CNTL__SI__CI                           0x0A25
#define mmMC_SEQ_CNTL__VI                               0x0A24
#define mmMC_SEQ_CNTL_2__SI__CI                         0x0AD4
#define mmMC_SEQ_CNTL_2__VI                             0x0A25
#define mmMC_SEQ_CNTL_3__VI                             0x0A26
#define mmMC_SEQ_DRAM__SI__CI                           0x0A26
#define mmMC_SEQ_DRAM__VI                               0x0A27
#define mmMC_SEQ_DRAM_2__SI__CI                         0x0A27
#define mmMC_SEQ_DRAM_2__VI                             0x0A28
#define mmMC_SEQ_FIFO_CTL__SI__CI                       0x0A57
#define mmMC_SEQ_FIFO_CTL__VI                           0x0A5D
#define mmMC_SEQ_IO_DEBUG_DATA__SI__CI                  0x0A92
#define mmMC_SEQ_IO_DEBUG_DATA__VI                      0x0ABD
#define mmMC_SEQ_IO_DEBUG_INDEX__SI__CI                 0x0A91
#define mmMC_SEQ_IO_DEBUG_INDEX__VI                     0x0ABC
#define mmMC_SEQ_IO_RESERVE__VI                         0x0A61
#define mmMC_SEQ_MISC0__SI__CI                          0x0A80
#define mmMC_SEQ_MISC0__VI                              0x0A71
#define mmMC_SEQ_MISC1__SI__CI                          0x0A81
#define mmMC_SEQ_MISC1__VI                              0x0A72
#define mmMC_SEQ_MISC3__SI__CI                          0x0A8B
#define mmMC_SEQ_MISC3__VI                              0x0A74
#define mmMC_SEQ_MISC4__SI__CI                          0x0A8C
#define mmMC_SEQ_MISC4__VI                              0x0A75
#define mmMC_SEQ_MISC5__SI__CI                          0x0A95
#define mmMC_SEQ_MISC5__VI                              0x0A76
#define mmMC_SEQ_MISC6__SI__CI                          0x0A96
#define mmMC_SEQ_MISC6__VI                              0x0A77
#define mmMC_SEQ_MISC7__SI__CI                          0x0A99
#define mmMC_SEQ_MISC7__VI                              0x0A78
#define mmMC_SEQ_MISC8__SI__CI                          0x0A5F
#define mmMC_SEQ_MISC8__VI                              0x0A79
#define mmMC_SEQ_MISC9__SI__CI                          0x0AE7
#define mmMC_SEQ_MISC9__VI                              0x0A7A
#define mmMC_SEQ_MISC_TIMING__SI__CI                    0x0A2A
#define mmMC_SEQ_MISC_TIMING__VI                        0x0A2D
#define mmMC_SEQ_MISC_TIMING2__SI__CI                   0x0A2B
#define mmMC_SEQ_MISC_TIMING2__VI                       0x0A2F
#define mmMC_SEQ_MISC_TIMING2_LP__SI__CI                0x0A9E
#define mmMC_SEQ_MISC_TIMING2_LP__VI                    0x0A30
#define mmMC_SEQ_MISC_TIMING_LP__SI__CI                 0x0A9D
#define mmMC_SEQ_MISC_TIMING_LP__VI                     0x0A2E
#define mmMC_SEQ_PMG_TIMING__SI__CI                     0x0A2C
#define mmMC_SEQ_PMG_TIMING__VI                         0x0A31
#define mmMC_SEQ_PMG_TIMING_LP__SI__CI                  0x0AD3
#define mmMC_SEQ_PMG_TIMING_LP__VI                      0x0A32
#define mmMC_SEQ_RAS_TIMING__SI__CI                     0x0A28
#define mmMC_SEQ_RAS_TIMING__VI                         0x0A29
#define mmMC_SEQ_RAS_TIMING_LP__SI__CI                  0x0A9B
#define mmMC_SEQ_RAS_TIMING_LP__VI                      0x0A2A
#define mmMC_SEQ_RD_CTL_D0__SI__CI                      0x0A2D
#define mmMC_SEQ_RD_CTL_D0__VI                          0x0A33
#define mmMC_SEQ_RD_CTL_D0_LP__SI__CI                   0x0AC7
#define mmMC_SEQ_RD_CTL_D0_LP__VI                       0x0A34
#define mmMC_SEQ_RD_CTL_D1__SI__CI                      0x0A2E
#define mmMC_SEQ_RD_CTL_D1__VI                          0x0A35
#define mmMC_SEQ_RD_CTL_D1_LP__SI__CI                   0x0AC8
#define mmMC_SEQ_RD_CTL_D1_LP__VI                       0x0A36
#define mmMC_SEQ_RESERVE_0_S__SI__CI                    0x0A1E
#define mmMC_SEQ_RESERVE_0_S__VI                        0x0A07
#define mmMC_SEQ_RESERVE_1_S__SI__CI                    0x0A1F
#define mmMC_SEQ_RESERVE_1_S__VI                        0x0A08
#define mmMC_SEQ_RESERVE_M__SI__CI                      0x0A82
#define mmMC_SEQ_RESERVE_M__VI                          0x0A60
#define mmMC_SEQ_SREG_READ__VI                          0x0A7F
#define mmMC_SEQ_SREG_STATUS__VI                        0x0A80
#define mmMC_SEQ_STATUS_M__SI__CI                       0x0A7D
#define mmMC_SEQ_STATUS_M__VI                           0x0A5E
#define mmMC_SEQ_STATUS_S__SI__CI                       0x0A20
#define mmMC_SEQ_STATUS_S__VI                           0x0A05
#define mmMC_SEQ_SUP_CNTL__SI__CI                       0x0A32
#define mmMC_SEQ_SUP_CNTL__VI                           0x0A63
#define mmMC_SEQ_SUP_DEC_STAT__SI__CI                   0x0A88
#define mmMC_SEQ_SUP_DEC_STAT__VI                       0x0A6A
#define mmMC_SEQ_SUP_GP0_STAT__SI__CI                   0x0A8F
#define mmMC_SEQ_SUP_GP0_STAT__VI                       0x0A65
#define mmMC_SEQ_SUP_GP1_STAT__SI__CI                   0x0A90
#define mmMC_SEQ_SUP_GP1_STAT__VI                       0x0A66
#define mmMC_SEQ_SUP_GP2_STAT__SI__CI                   0x0A85
#define mmMC_SEQ_SUP_GP2_STAT__VI                       0x0A67
#define mmMC_SEQ_SUP_GP3_STAT__SI__CI                   0x0A86
#define mmMC_SEQ_SUP_GP3_STAT__VI                       0x0A68
#define mmMC_SEQ_SUP_IR_STAT__SI__CI                    0x0A87
#define mmMC_SEQ_SUP_IR_STAT__VI                        0x0A69
#define mmMC_SEQ_SUP_PGM__SI__CI                        0x0A33
#define mmMC_SEQ_SUP_PGM__VI                            0x0A64
#define mmMC_SEQ_SUP_PGM_STAT__SI__CI                   0x0A89
#define mmMC_SEQ_SUP_PGM_STAT__VI                       0x0A6B
#define mmMC_SEQ_SUP_R_PGM__SI__CI                      0x0A8A
#define mmMC_SEQ_SUP_R_PGM__VI                          0x0A6C
#define mmMC_SEQ_TIMER_RD__SI__CI                       0x0ACA
#define mmMC_SEQ_TIMER_RD__VI                           0x0A7D
#define mmMC_SEQ_TIMER_WR__SI__CI                       0x0AC9
#define mmMC_SEQ_TIMER_WR__VI                           0x0A7C
#define mmMC_SEQ_TRAIN_CAPTURE__SI__CI                  0x0A3E
#define mmMC_SEQ_TRAIN_CAPTURE__VI                      0x0A5B
#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI             0x0A3F
#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR__VI                 0x0A5C
#define mmMC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI              0x0A3A
#define mmMC_SEQ_TRAIN_WAKEUP_CNTL__VI                  0x0A57
#define mmMC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI              0x0A3C
#define mmMC_SEQ_TRAIN_WAKEUP_EDGE__VI                  0x0A58
#define mmMC_SEQ_TRAIN_WAKEUP_MASK__SI__CI              0x0A3D
#define mmMC_SEQ_TRAIN_WAKEUP_MASK__VI                  0x0A59
#define mmMC_SEQ_WR_CTL_D0__SI__CI                      0x0A2F
#define mmMC_SEQ_WR_CTL_D0__VI                          0x0A3B
#define mmMC_SEQ_WR_CTL_D0_LP__SI__CI                   0x0A9F
#define mmMC_SEQ_WR_CTL_D0_LP__VI                       0x0A3C
#define mmMC_SEQ_WR_CTL_D1__SI__CI                      0x0A30
#define mmMC_SEQ_WR_CTL_D1__VI                          0x0A3D
#define mmMC_SEQ_WR_CTL_D1_LP__SI__CI                   0x0AA0
#define mmMC_SEQ_WR_CTL_D1_LP__VI                       0x0A3E
#define mmMC_SHARED_ACTIVE_FCN_ID__VI                   0x081F
#define mmMC_SHARED_CHREMAP2__VI                        0x081C
#define mmMC_SHARED_VF_ENABLE__VI                       0x081D
#define mmMC_SHARED_VIRT_RESET_REQ__VI                  0x081E
#define mmMC_VM_FB_SIZE_OFFSET_VF0__VI                  0xF980
#define mmMC_VM_FB_SIZE_OFFSET_VF1__VI                  0xF981
#define mmMC_VM_FB_SIZE_OFFSET_VF10__VI                 0xF98A
#define mmMC_VM_FB_SIZE_OFFSET_VF11__VI                 0xF98B
#define mmMC_VM_FB_SIZE_OFFSET_VF12__VI                 0xF98C
#define mmMC_VM_FB_SIZE_OFFSET_VF13__VI                 0xF98D
#define mmMC_VM_FB_SIZE_OFFSET_VF14__VI                 0xF98E
#define mmMC_VM_FB_SIZE_OFFSET_VF15__VI                 0xF98F
#define mmMC_VM_FB_SIZE_OFFSET_VF2__VI                  0xF982
#define mmMC_VM_FB_SIZE_OFFSET_VF3__VI                  0xF983
#define mmMC_VM_FB_SIZE_OFFSET_VF4__VI                  0xF984
#define mmMC_VM_FB_SIZE_OFFSET_VF5__VI                  0xF985
#define mmMC_VM_FB_SIZE_OFFSET_VF6__VI                  0xF986
#define mmMC_VM_FB_SIZE_OFFSET_VF7__VI                  0xF987
#define mmMC_VM_FB_SIZE_OFFSET_VF8__VI                  0xF988
#define mmMC_VM_FB_SIZE_OFFSET_VF9__VI                  0xF989
#define mmMC_VM_MARC_BASE_HI_0__VI                      0xF999
#define mmMC_VM_MARC_BASE_HI_1__VI                      0xF99F
#define mmMC_VM_MARC_BASE_HI_2__VI                      0xF9A5
#define mmMC_VM_MARC_BASE_HI_3__VI                      0xF9AB
#define mmMC_VM_MARC_BASE_LO_0__VI                      0xF998
#define mmMC_VM_MARC_BASE_LO_1__VI                      0xF99E
#define mmMC_VM_MARC_BASE_LO_2__VI                      0xF9A4
#define mmMC_VM_MARC_BASE_LO_3__VI                      0xF9AA
#define mmMC_VM_MARC_CNTL__VI                           0xF9B0
#define mmMC_VM_MARC_LEN_HI_0__VI                       0xF99D
#define mmMC_VM_MARC_LEN_HI_1__VI                       0xF9A3
#define mmMC_VM_MARC_LEN_HI_2__VI                       0xF9A9
#define mmMC_VM_MARC_LEN_HI_3__VI                       0xF9AF
#define mmMC_VM_MARC_LEN_LO_0__VI                       0xF99C
#define mmMC_VM_MARC_LEN_LO_1__VI                       0xF9A2
#define mmMC_VM_MARC_LEN_LO_2__VI                       0xF9A8
#define mmMC_VM_MARC_LEN_LO_3__VI                       0xF9AE
#define mmMC_VM_MARC_RELOC_HI_0__VI                     0xF99B
#define mmMC_VM_MARC_RELOC_HI_1__VI                     0xF9A1
#define mmMC_VM_MARC_RELOC_HI_2__VI                     0xF9A7
#define mmMC_VM_MARC_RELOC_HI_3__VI                     0xF9AD
#define mmMC_VM_MARC_RELOC_LO_0__VI                     0xF99A
#define mmMC_VM_MARC_RELOC_LO_1__VI                     0xF9A0
#define mmMC_VM_MARC_RELOC_LO_2__VI                     0xF9A6
#define mmMC_VM_MARC_RELOC_LO_3__VI                     0xF9AC
#define mmMC_VM_MB_L1_TLB1_DEBUG__VI                    0x0892
#define mmMC_VM_MB_L1_TLS0_CNTL0__VI                    0xF9B1
#define mmMC_VM_MB_L1_TLS0_CNTL1__VI                    0xF9B4
#define mmMC_VM_MB_L1_TLS0_CNTL2__VI                    0xF9B7
#define mmMC_VM_MB_L1_TLS0_CNTL3__VI                    0xF9BA
#define mmMC_VM_MB_L1_TLS0_CNTL4__VI                    0xF9BD
#define mmMC_VM_MB_L1_TLS0_CNTL5__VI                    0xF9C0
#define mmMC_VM_MB_L1_TLS0_CNTL6__VI                    0xF9C3
#define mmMC_VM_MB_L1_TLS0_CNTL7__VI                    0xF9C6
#define mmMC_VM_MB_L1_TLS0_CNTL8__VI                    0xF9C9
#define mmMC_VM_MB_L1_TLS0_END_ADDR0__VI                0xF9B3
#define mmMC_VM_MB_L1_TLS0_END_ADDR1__VI                0xF9B6
#define mmMC_VM_MB_L1_TLS0_END_ADDR2__VI                0xF9B9
#define mmMC_VM_MB_L1_TLS0_END_ADDR3__VI                0xF9BC
#define mmMC_VM_MB_L1_TLS0_END_ADDR4__VI                0xF9BF
#define mmMC_VM_MB_L1_TLS0_END_ADDR5__VI                0xF9C2
#define mmMC_VM_MB_L1_TLS0_END_ADDR6__VI                0xF9C5
#define mmMC_VM_MB_L1_TLS0_END_ADDR7__VI                0xF9C8
#define mmMC_VM_MB_L1_TLS0_END_ADDR8__VI                0xF9CB
#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__VI    0xF9CD
#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VI  0xF9CC
#define mmMC_VM_MB_L1_TLS0_START_ADDR0__VI              0xF9B2
#define mmMC_VM_MB_L1_TLS0_START_ADDR1__VI              0xF9B5
#define mmMC_VM_MB_L1_TLS0_START_ADDR2__VI              0xF9B8
#define mmMC_VM_MB_L1_TLS0_START_ADDR3__VI              0xF9BB
#define mmMC_VM_MB_L1_TLS0_START_ADDR4__VI              0xF9BE
#define mmMC_VM_MB_L1_TLS0_START_ADDR5__VI              0xF9C1
#define mmMC_VM_MB_L1_TLS0_START_ADDR6__VI              0xF9C4
#define mmMC_VM_MB_L1_TLS0_START_ADDR7__VI              0xF9C7
#define mmMC_VM_MB_L1_TLS0_START_ADDR8__VI              0xF9CA
#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2__VI               0xF995
#define mmMC_VM_NB_MMIOBASE__VI                         0xF990
#define mmMC_VM_NB_MMIOLIMIT__VI                        0xF991
#define mmMC_VM_NB_PCI_ARB__VI                          0xF993
#define mmMC_VM_NB_PCI_CTRL__VI                         0xF992
#define mmMC_VM_NB_TOP_OF_DRAM3__VI                     0xF997
#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1__VI                0xF994
#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2__VI               0xF996
#define mmMC_XBAR_FIFO_MON_CNTL0__VI                    0x0C8F
#define mmMC_XBAR_FIFO_MON_CNTL1__VI                    0x0C90
#define mmMC_XBAR_FIFO_MON_CNTL2__VI                    0x0C91
#define mmMC_XBAR_FIFO_MON_MAX_THSH__VI                 0x0C96
#define mmMC_XBAR_FIFO_MON_RSLT0__VI                    0x0C92
#define mmMC_XBAR_FIFO_MON_RSLT1__VI                    0x0C93
#define mmMC_XBAR_FIFO_MON_RSLT2__VI                    0x0C94
#define mmMC_XBAR_FIFO_MON_RSLT3__VI                    0x0C95
#define mmMICROSECOND_TIME_BASE_DIV__VI                 0x013B
#define mmMILLISECOND_TIME_BASE_DIV__VI                 0x0130
#define mmMP_FPS_CNT__VI                                0x0235
#define mmMVP_AFR_FLIP_FIFO_CNTL__VI                    0x1AE1
#define mmMVP_AFR_FLIP_MODE__VI                         0x1AE0
#define mmMVP_BLACK_KEYER__VI                           0x02B2
#define mmMVP_CONTROL1__VI                              0x02AC
#define mmMVP_CONTROL2__VI                              0x02AD
#define mmMVP_CONTROL3__VI                              0x02B6
#define mmMVP_CRC_CNTL__VI                              0x02B3
#define mmMVP_CRC_RESULT_BLUE_GREEN__VI                 0x02B4
#define mmMVP_CRC_RESULT_RED__VI                        0x02B5
#define mmMVP_DEBUG__VI                                 0x02BB
#define mmMVP_FIFO_CONTROL__VI                          0x02AE
#define mmMVP_FIFO_STATUS__VI                           0x02AF
#define mmMVP_FLIP_LINE_NUM_INSERT__VI                  0x1AE2
#define mmMVP_INBAND_CNTL_CAP__VI                       0x02B1
#define mmMVP_RECEIVE_CNT_CNTL1__VI                     0x02B7
#define mmMVP_RECEIVE_CNT_CNTL2__VI                     0x02B8
#define mmMVP_SLAVE_STATUS__VI                          0x02B0
#define mmMVP_TEST_DEBUG_DATA__VI                       0x02BA
#define mmMVP_TEST_DEBUG_INDEX__VI                      0x02B9
#define mmOUTPUT_CSC_C11_C12__VI                        0x1A3D
#define mmOUTPUT_CSC_C11_C12_A__VI                      0x46B7
#define mmOUTPUT_CSC_C11_C12_B__VI                      0x46BD
#define mmOUTPUT_CSC_C13_C14__VI                        0x1A3E
#define mmOUTPUT_CSC_C13_C14_A__VI                      0x46B8
#define mmOUTPUT_CSC_C13_C14_B__VI                      0x46BE
#define mmOUTPUT_CSC_C21_C22__VI                        0x1A3F
#define mmOUTPUT_CSC_C21_C22_A__VI                      0x46B9
#define mmOUTPUT_CSC_C21_C22_B__VI                      0x46BF
#define mmOUTPUT_CSC_C23_C24__VI                        0x1A40
#define mmOUTPUT_CSC_C23_C24_A__VI                      0x46BA
#define mmOUTPUT_CSC_C23_C24_B__VI                      0x46C0
#define mmOUTPUT_CSC_C31_C32__VI                        0x1A41
#define mmOUTPUT_CSC_C31_C32_A__VI                      0x46BB
#define mmOUTPUT_CSC_C31_C32_B__VI                      0x46C1
#define mmOUTPUT_CSC_C33_C34__VI                        0x1A42
#define mmOUTPUT_CSC_C33_C34_A__VI                      0x46BC
#define mmOUTPUT_CSC_C33_C34_B__VI                      0x46C2
#define mmOUTPUT_CSC_CONTROL__VI                        0x1A3C
#define mmOUT_CLAMP_CONTROL_B_CB__VI                    0x1A9D
#define mmOUT_CLAMP_CONTROL_G_Y__VI                     0x1A9C
#define mmOUT_CLAMP_CONTROL_R_CR__VI                    0x1A52
#define mmOUT_ROUND_CONTROL__VI                         0x1A51
#define mmOVL_SECONDARY_SURFACE_ADDRESS__VI             0x1A92
#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI        0x1A94
#define mmOVL_STEREOSYNC_FLIP__VI                       0x1A93
#define mmPCIE_EFUSE__VI                                0x0FC0
#define mmPCIE_EFUSE2__VI                               0x0FC1
#define mmPCIE_EFUSE3__VI                               0x0FC2
#define mmPCIE_EFUSE4__VI                               0x0FC3
#define mmPCIE_EFUSE5__VI                               0x0FC4
#define mmPCIE_EFUSE6__VI                               0x0FC5
#define mmPCIE_EFUSE7__VI                               0x0FC6
#define mmPERFCOUNTER_CNTL__VI                          0x0170
#define mmPERFCOUNTER_STATE__VI                         0x0171
#define mmPERFMON_CNTL__VI                              0x0173
#define mmPERFMON_CNTL2__VI                             0x017A
#define mmPERFMON_CVALUE_INT_MISC__VI                   0x0172
#define mmPERFMON_CVALUE_LOW__VI                        0x0174
#define mmPERFMON_HI__VI                                0x0175
#define mmPERFMON_LOW__VI                               0x0176
#define mmPERFMON_TEST_DEBUG_DATA__VI                   0x0178
#define mmPERFMON_TEST_DEBUG_INDEX__VI                  0x0177
#define mmPHY_AUX_CNTL__VI                              0x4897
#define mmPIPE0_ARBITRATION_CONTROL3__VI                0x02FA
#define mmPIPE0_DMIF_BUFFER_CONTROL__VI                 0x0321
#define mmPIPE0_MAX_REQUESTS__VI                        0x0305
#define mmPIPE0_PG_CONFIG__VI                           0x02C0
#define mmPIPE0_PG_ENABLE__VI                           0x02C1
#define mmPIPE0_PG_STATUS__VI                           0x02C2
#define mmPIPE1_ARBITRATION_CONTROL3__VI                0x02FB
#define mmPIPE1_DMIF_BUFFER_CONTROL__VI                 0x0322
#define mmPIPE1_MAX_REQUESTS__VI                        0x0306
#define mmPIPE1_PG_CONFIG__VI                           0x02C3
#define mmPIPE1_PG_ENABLE__VI                           0x02C4
#define mmPIPE1_PG_STATUS__VI                           0x02C5
#define mmPIPE2_ARBITRATION_CONTROL3__VI                0x02FC
#define mmPIPE2_DMIF_BUFFER_CONTROL__VI                 0x0323
#define mmPIPE2_MAX_REQUESTS__VI                        0x0307
#define mmPIPE2_PG_CONFIG__VI                           0x02C6
#define mmPIPE2_PG_ENABLE__VI                           0x02C7
#define mmPIPE2_PG_STATUS__VI                           0x02C8
#define mmPIPE3_ARBITRATION_CONTROL3__VI                0x02FD
#define mmPIPE3_DMIF_BUFFER_CONTROL__VI                 0x0324
#define mmPIPE3_MAX_REQUESTS__VI                        0x0308
#define mmPIPE3_PG_CONFIG__VI                           0x02C9
#define mmPIPE3_PG_ENABLE__VI                           0x02CA
#define mmPIPE3_PG_STATUS__VI                           0x02CB
#define mmPIPE4_ARBITRATION_CONTROL3__VI                0x02FE
#define mmPIPE4_DMIF_BUFFER_CONTROL__VI                 0x0325
#define mmPIPE4_MAX_REQUESTS__VI                        0x0309
#define mmPIPE4_PG_CONFIG__VI                           0x02CC
#define mmPIPE4_PG_ENABLE__VI                           0x02CD
#define mmPIPE4_PG_STATUS__VI                           0x02CE
#define mmPIPE5_ARBITRATION_CONTROL3__VI                0x02FF
#define mmPIPE5_DMIF_BUFFER_CONTROL__VI                 0x0326
#define mmPIPE5_MAX_REQUESTS__VI                        0x030A
#define mmPIPE5_PG_CONFIG__VI                           0x02CF
#define mmPIPE5_PG_ENABLE__VI                           0x02D0
#define mmPIPE5_PG_STATUS__VI                           0x02D1
#define mmPIPE6_ARBITRATION_CONTROL3__VI                0x032A
#define mmPIPE6_MAX_REQUESTS__VI                        0x032C
#define mmPIPE7_ARBITRATION_CONTROL3__VI                0x032B
#define mmPIPE7_MAX_REQUESTS__VI                        0x032D
#define mmPIXCLK0_RESYNC_CNTL__VI                       0x013A
#define mmPIXCLK1_RESYNC_CNTL__VI                       0x0138
#define mmPIXCLK2_RESYNC_CNTL__VI                       0x0139
#define mmPLL_ANALOG__VI                                0x1708
#define mmPLL_ANALOG_CNTL__VI                           0x1711
#define mmPLL_CNTL__VI                                  0x1707
#define mmPLL_DEBUG_CNTL__VI                            0x170B
#define mmPLL_DS_CNTL__VI                               0x1705
#define mmPLL_FB_DIV__VI                                0x1701
#define mmPLL_IDCLK_CNTL__VI                            0x1706
#define mmPLL_MACRO_CNTL_RESERVED0__VI                  0x1700
#define mmPLL_MACRO_CNTL_RESERVED1__VI                  0x1701
#define mmPLL_MACRO_CNTL_RESERVED10__VI                 0x170A
#define mmPLL_MACRO_CNTL_RESERVED11__VI                 0x170B
#define mmPLL_MACRO_CNTL_RESERVED12__VI                 0x170C
#define mmPLL_MACRO_CNTL_RESERVED13__VI                 0x170D
#define mmPLL_MACRO_CNTL_RESERVED14__VI                 0x170E
#define mmPLL_MACRO_CNTL_RESERVED15__VI                 0x170F
#define mmPLL_MACRO_CNTL_RESERVED16__VI                 0x1710
#define mmPLL_MACRO_CNTL_RESERVED17__VI                 0x1711
#define mmPLL_MACRO_CNTL_RESERVED18__VI                 0x1712
#define mmPLL_MACRO_CNTL_RESERVED19__VI                 0x1713
#define mmPLL_MACRO_CNTL_RESERVED2__VI                  0x1702
#define mmPLL_MACRO_CNTL_RESERVED20__VI                 0x1714
#define mmPLL_MACRO_CNTL_RESERVED21__VI                 0x1715
#define mmPLL_MACRO_CNTL_RESERVED22__VI                 0x1716
#define mmPLL_MACRO_CNTL_RESERVED23__VI                 0x1717
#define mmPLL_MACRO_CNTL_RESERVED24__VI                 0x1718
#define mmPLL_MACRO_CNTL_RESERVED25__VI                 0x1719
#define mmPLL_MACRO_CNTL_RESERVED26__VI                 0x171A
#define mmPLL_MACRO_CNTL_RESERVED27__VI                 0x171B
#define mmPLL_MACRO_CNTL_RESERVED28__VI                 0x171C
#define mmPLL_MACRO_CNTL_RESERVED29__VI                 0x171D
#define mmPLL_MACRO_CNTL_RESERVED3__VI                  0x1703
#define mmPLL_MACRO_CNTL_RESERVED30__VI                 0x171E
#define mmPLL_MACRO_CNTL_RESERVED31__VI                 0x171F
#define mmPLL_MACRO_CNTL_RESERVED32__VI                 0x1720
#define mmPLL_MACRO_CNTL_RESERVED33__VI                 0x1721
#define mmPLL_MACRO_CNTL_RESERVED34__VI                 0x1722
#define mmPLL_MACRO_CNTL_RESERVED35__VI                 0x1723
#define mmPLL_MACRO_CNTL_RESERVED36__VI                 0x1724
#define mmPLL_MACRO_CNTL_RESERVED37__VI                 0x1725
#define mmPLL_MACRO_CNTL_RESERVED38__VI                 0x1726
#define mmPLL_MACRO_CNTL_RESERVED39__VI                 0x1727
#define mmPLL_MACRO_CNTL_RESERVED4__VI                  0x1704
#define mmPLL_MACRO_CNTL_RESERVED40__VI                 0x1728
#define mmPLL_MACRO_CNTL_RESERVED41__VI                 0x1729
#define mmPLL_MACRO_CNTL_RESERVED5__VI                  0x1705
#define mmPLL_MACRO_CNTL_RESERVED6__VI                  0x1706
#define mmPLL_MACRO_CNTL_RESERVED7__VI                  0x1707
#define mmPLL_MACRO_CNTL_RESERVED8__VI                  0x1708
#define mmPLL_MACRO_CNTL_RESERVED9__VI                  0x1709
#define mmPLL_POST_DIV__VI                              0x1702
#define mmPLL_REF_DIV__VI                               0x1700
#define mmPLL_SS_AMOUNT_DSFRAC__VI                      0x1703
#define mmPLL_SS_CNTL__VI                               0x1704
#define mmPLL_UNLOCK_DETECT_CNTL__VI                    0x170A
#define mmPLL_UPDATE_CNTL__VI                           0x170D
#define mmPLL_UPDATE_LOCK__VI                           0x170C
#define mmPLL_VREG_CNTL__VI                             0x1709
#define mmPLL_XOR_LOCK__VI                              0x1710
#define mmPPLL_DEBUG_MUX_CNTL__VI                       0x1721
#define mmPPLL_DIV_UPDATE_DEBUG__VI                     0x171F
#define mmPPLL_SPARE0__VI                               0x1722
#define mmPPLL_SPARE1__VI                               0x1723
#define mmPPLL_STATUS_DEBUG__VI                         0x1720
#define mmPRESCALE_CONTROL__VI                          0x46B2
#define mmPRESCALE_GRPH_CONTROL__VI                     0x1A2D
#define mmPRESCALE_OVL_CONTROL__VI                      0x1A31
#define mmPRESCALE_VALUES_B__VI                         0x46B5
#define mmPRESCALE_VALUES_G__VI                         0x46B4
#define mmPRESCALE_VALUES_GRPH_B__VI                    0x1A30
#define mmPRESCALE_VALUES_GRPH_G__VI                    0x1A2F
#define mmPRESCALE_VALUES_GRPH_R__VI                    0x1A2E
#define mmPRESCALE_VALUES_OVL_CB__VI                    0x1A32
#define mmPRESCALE_VALUES_OVL_CR__VI                    0x1A34
#define mmPRESCALE_VALUES_OVL_Y__VI                     0x1A33
#define mmPRESCALE_VALUES_R__VI                         0x46B3
#define mmRAS_TA_SIGNATURE1__VI                         0x33A0
#define mmRBBMIF_STATUS__VI                             0x0315
#define mmRBBMIF_STATUS_FLAG__VI                        0x0327
#define mmRBBMIF_TIMEOUT__VI                            0x0314
#define mmRBBMIF_TIMEOUT_DIS__VI                        0x0316
#define mmREFCLK_CGTT_BLK_CTRL_REG__VI                  0x010B
#define mmREFCLK_CNTL__VI                               0x0109
#define mmREGAMMA_CNTLA_END_CNTL1__VI                   0x1AA6
#define mmREGAMMA_CNTLA_END_CNTL2__VI                   0x1AA7
#define mmREGAMMA_CNTLA_REGION_0_1__VI                  0x1AA8
#define mmREGAMMA_CNTLA_REGION_10_11__VI                0x1AAD
#define mmREGAMMA_CNTLA_REGION_12_13__VI                0x1AAE
#define mmREGAMMA_CNTLA_REGION_14_15__VI                0x1AAF
#define mmREGAMMA_CNTLA_REGION_2_3__VI                  0x1AA9
#define mmREGAMMA_CNTLA_REGION_4_5__VI                  0x1AAA
#define mmREGAMMA_CNTLA_REGION_6_7__VI                  0x1AAB
#define mmREGAMMA_CNTLA_REGION_8_9__VI                  0x1AAC
#define mmREGAMMA_CNTLA_SLOPE_CNTL__VI                  0x1AA5
#define mmREGAMMA_CNTLA_START_CNTL__VI                  0x1AA4
#define mmREGAMMA_CNTLB_END_CNTL1__VI                   0x1AB2
#define mmREGAMMA_CNTLB_END_CNTL2__VI                   0x1AB3
#define mmREGAMMA_CNTLB_REGION_0_1__VI                  0x1AB4
#define mmREGAMMA_CNTLB_REGION_10_11__VI                0x1AB9
#define mmREGAMMA_CNTLB_REGION_12_13__VI                0x1ABA
#define mmREGAMMA_CNTLB_REGION_14_15__VI                0x1ABB
#define mmREGAMMA_CNTLB_REGION_2_3__VI                  0x1AB5
#define mmREGAMMA_CNTLB_REGION_4_5__VI                  0x1AB6
#define mmREGAMMA_CNTLB_REGION_6_7__VI                  0x1AB7
#define mmREGAMMA_CNTLB_REGION_8_9__VI                  0x1AB8
#define mmREGAMMA_CNTLB_SLOPE_CNTL__VI                  0x1AB1
#define mmREGAMMA_CNTLB_START_CNTL__VI                  0x1AB0
#define mmREGAMMA_CONTROL__VI                           0x1AA0
#define mmREGAMMA_LUT_DATA__VI                          0x1AA2
#define mmREGAMMA_LUT_INDEX__VI                         0x1AA1
#define mmREGAMMA_LUT_WRITE_EN_MASK__VI                 0x1AA3
#define mmREMAP_HDP_MEM_FLUSH_CNTL__VI                  0x1426
#define mmREMAP_HDP_REG_FLUSH_CNTL__VI                  0x1427
#define mmRLC_AUTO_PG_CTRL__VI                          0xEC55
#define mmRLC_CAPTURE_GPU_CLOCK_COUNT__VI               0xEC26
#define mmRLC_CGCG_CGLS_CTRL__VI                        0xEC49
#define mmRLC_CGCG_RAMP_CTRL__VI                        0xEC4A
#define mmRLC_CGTT_MGCG_OVERRIDE__VI                    0xEC48
#define mmRLC_CNTL__SI__CI                              0x30C0
#define mmRLC_CNTL__VI                                  0xEC00
#define mmRLC_CP_RESPONSE0__VI                          0xECA5
#define mmRLC_CP_RESPONSE1__VI                          0xECA6
#define mmRLC_CP_RESPONSE2__VI                          0xECA7
#define mmRLC_CP_RESPONSE3__VI                          0xECA8
#define mmRLC_CP_SCHEDULERS__VI                         0xECAA
#define mmRLC_CSIB_ADDR_HI__VI                          0xECA3
#define mmRLC_CSIB_ADDR_LO__VI                          0xECA2
#define mmRLC_CSIB_LENGTH__VI                           0xECA4
#define mmRLC_CU_STATUS__VI                             0xEC4E
#define mmRLC_DEBUG__VI                                 0xEC02
#define mmRLC_DEBUG_SELECT__VI                          0xEC01
#define mmRLC_DRIVER_CPDMA_STATUS__VI                   0xEC1E
#define mmRLC_DYN_PG_REQUEST__VI                        0xEC4C
#define mmRLC_DYN_PG_STATUS__VI                         0xEC4B
#define mmRLC_GPM_CU_PD_TIMEOUT__VI                     0xEC6B
#define mmRLC_GPM_DEBUG__VI                             0xEC21
#define mmRLC_GPM_DEBUG_SELECT__VI                      0xEC20
#define mmRLC_GPM_GENERAL_0__VI                         0xEC63
#define mmRLC_GPM_GENERAL_1__VI                         0xEC64
#define mmRLC_GPM_GENERAL_2__VI                         0xEC65
#define mmRLC_GPM_GENERAL_3__VI                         0xEC66
#define mmRLC_GPM_GENERAL_4__VI                         0xEC67
#define mmRLC_GPM_GENERAL_5__VI                         0xEC68
#define mmRLC_GPM_GENERAL_6__VI                         0xEC69
#define mmRLC_GPM_GENERAL_7__VI                         0xEC6A
#define mmRLC_GPM_INT_DISABLE_TH0__VI                   0xEC7C
#define mmRLC_GPM_INT_DISABLE_TH1__VI                   0xEC7D
#define mmRLC_GPM_INT_FORCE_TH0__VI                     0xEC7E
#define mmRLC_GPM_INT_FORCE_TH1__VI                     0xEC7F
#define mmRLC_GPM_LOG_ADDR__VI                          0xEC76
#define mmRLC_GPM_LOG_CONT__VI                          0xEC7B
#define mmRLC_GPM_LOG_SIZE__VI                          0xEC77
#define mmRLC_GPM_PERF_COUNT_0__VI                      0xEC6F
#define mmRLC_GPM_PERF_COUNT_1__VI                      0xEC70
#define mmRLC_GPM_SCRATCH_ADDR__VI                      0xEC6C
#define mmRLC_GPM_SCRATCH_DATA__VI                      0xEC6D
#define mmRLC_GPM_STAT__VI                              0xEC40
#define mmRLC_GPM_THREAD_ENABLE__VI                     0xEC45
#define mmRLC_GPM_THREAD_PRIORITY__VI                   0xEC44
#define mmRLC_GPM_THREAD_RESET__VI                      0xEC28
#define mmRLC_GPM_UCODE_ADDR__VI                        0xF83C
#define mmRLC_GPM_UCODE_DATA__VI                        0xF83D
#define mmRLC_GPM_VMID_THREAD0__VI                      0xEC46
#define mmRLC_GPM_VMID_THREAD1__VI                      0xEC47
#define mmRLC_GPM_VMID_THREAD2__VI                      0xFB41
#define mmRLC_GPR_REG1__VI                              0xEC79
#define mmRLC_GPR_REG2__VI                              0xEC7A
#define mmRLC_GPU_CLOCK_32__VI                          0xEC42
#define mmRLC_GPU_CLOCK_32_RES_SEL__VI                  0xEC41
#define mmRLC_GPU_CLOCK_COUNT_LSB__VI                   0xEC24
#define mmRLC_GPU_CLOCK_COUNT_MSB__VI                   0xEC25
#define mmRLC_GPU_IOV_ACTIVE_FCN_ID__VI                 0xFB40
#define mmRLC_GPU_IOV_CFG_REG1__VI                      0xFB01
#define mmRLC_GPU_IOV_CFG_REG10__VI                     0xFB22
#define mmRLC_GPU_IOV_CFG_REG11__VI                     0xFB23
#define mmRLC_GPU_IOV_CFG_REG12__VI                     0xFB24
#define mmRLC_GPU_IOV_CFG_REG13__VI                     0xFB25
#define mmRLC_GPU_IOV_CFG_REG14__VI                     0xFB26
#define mmRLC_GPU_IOV_CFG_REG15__VI                     0xFB27
#define mmRLC_GPU_IOV_CFG_REG2__VI                      0xFB02
#define mmRLC_GPU_IOV_CFG_REG6__VI                      0xFB06
#define mmRLC_GPU_IOV_CFG_REG8__VI                      0xFB08
#define mmRLC_GPU_IOV_CFG_REG9__VI                      0xFB21
#define mmRLC_GPU_IOV_F32_CNTL__VI                      0xFB46
#define mmRLC_GPU_IOV_F32_RESET__VI                     0xFB47
#define mmRLC_GPU_IOV_INT_DISABLE__VI                   0xFB4E
#define mmRLC_GPU_IOV_INT_FORCE__VI                     0xFB4F
#define mmRLC_GPU_IOV_RLC_RESPONSE__VI                  0xFB4D
#define mmRLC_GPU_IOV_SCH_0__VI                         0xFB52
#define mmRLC_GPU_IOV_SCH_1__VI                         0xFB53
#define mmRLC_GPU_IOV_SCH_2__VI                         0xFB54
#define mmRLC_GPU_IOV_SCH_3__VI                         0xFB55
#define mmRLC_GPU_IOV_SCH_INT__VI                       0xFB56
#define mmRLC_GPU_IOV_SCRATCH_ADDR__VI                  0xFB44
#define mmRLC_GPU_IOV_SCRATCH_DATA__VI                  0xFB45
#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS__VI             0xFB50
#define mmRLC_GPU_IOV_SDMA0_STATUS__VI                  0xFB48
#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS__VI             0xFB51
#define mmRLC_GPU_IOV_SDMA1_STATUS__VI                  0xFB49
#define mmRLC_GPU_IOV_SMU_RESPONSE__VI                  0xFB4A
#define mmRLC_GPU_IOV_UCODE_ADDR__VI                    0xFB42
#define mmRLC_GPU_IOV_UCODE_DATA__VI                    0xFB43
#define mmRLC_GPU_IOV_VF_ENABLE__VI                     0xFB00
#define mmRLC_GPU_IOV_VIRT_RESET_REQ__VI                0xFB4C
#define mmRLC_HYP_GPM_UCODE_ADDR__VI                    0xF83C
#define mmRLC_HYP_GPM_UCODE_DATA__VI                    0xF83D
#define mmRLC_JUMP_TABLE_RESTORE__VI                    0xEC1E
#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__VI              0xEC50
#define mmRLC_LB_CNTL__VI                               0xEC19
#define mmRLC_LB_CNTR_INIT__VI                          0xEC1B
#define mmRLC_LB_CNTR_MAX__VI                           0xEC12
#define mmRLC_LB_INIT_CU_MASK__VI                       0xEC4F
#define mmRLC_LB_PARAMS__VI                             0xEC51
#define mmRLC_LOAD_BALANCE_CNTR__VI                     0xEC1C
#define mmRLC_MAX_PG_CU__VI                             0xEC54
#define mmRLC_MC_CNTL__VI                               0xEC03
#define mmRLC_MEM_SLP_CNTL__VI                          0xEC06
#define mmRLC_MGCG_CTRL__VI                             0xEC1A
#define mmRLC_PERFMON_CLK_CNTL__VI                      0xDCBF
#define mmRLC_PG_ALWAYS_ON_CU_MASK__VI                  0xEC53
#define mmRLC_PG_CNTL__VI                               0xEC43
#define mmRLC_PG_DELAY__VI                              0xEC4D
#define mmRLC_PG_DELAY_2__VI                            0xEC1F
#define mmRLC_PG_DELAY_3__VI                            0xEC78
#define mmRLC_RLCV_COMMAND__VI                          0xEC0A
#define mmRLC_RLCV_SAFE_MODE__VI                        0xEC08
#define mmRLC_ROM_CNTL__VI                              0xF836
#define mmRLC_SAFE_MODE__VI                             0xEC05
#define mmRLC_SAVE_AND_RESTORE_BASE__VI                 0xEC1D
#define mmRLC_SERDES_CU_MASTER_BUSY__VI                 0xEC61
#define mmRLC_SERDES_NONCU_MASTER_BUSY__VI              0xEC62
#define mmRLC_SERDES_RD_DATA_0__VI                      0xEC5A
#define mmRLC_SERDES_RD_DATA_1__VI                      0xEC5B
#define mmRLC_SERDES_RD_DATA_2__VI                      0xEC5C
#define mmRLC_SERDES_RD_MASTER_INDEX__VI                0xEC59
#define mmRLC_SERDES_WR_CTRL__VI                        0xEC5F
#define mmRLC_SERDES_WR_CU_MASTER_MASK__VI              0xEC5D
#define mmRLC_SERDES_WR_DATA__VI                        0xEC60
#define mmRLC_SERDES_WR_NONCU_MASTER_MASK__VI           0xEC5E
#define mmRLC_SMU_COMMAND__VI                           0xECA9
#define mmRLC_SMU_GRBM_REG_SAVE_CTRL__VI                0xEC56
#define mmRLC_SMU_MESSAGE__VI                           0xEC76
#define mmRLC_SMU_PG_CTRL__VI                           0xEC57
#define mmRLC_SMU_PG_WAKE_UP_CTRL__VI                   0xEC58
#define mmRLC_SMU_SAFE_MODE__VI                         0xEC09
#define mmRLC_SOFT_RESET_GPU__VI                        0xEC05
#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__VI         0xDCA1
#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__VI         0xDCA2
#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__VI         0xDC9F
#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__VI         0xDCA0
#define mmRLC_SPM_DEBUG__VI                             0xEC75
#define mmRLC_SPM_DEBUG_SELECT__VI                      0xEC74
#define mmRLC_SPM_INT_CNTL__VI                          0xEC72
#define mmRLC_SPM_INT_STATUS__VI                        0xEC73
#define mmRLC_SPM_VMID__VI                              0xEC71
#define mmRLC_SRM_ARAM_ADDR__VI                         0xEC83
#define mmRLC_SRM_ARAM_DATA__VI                         0xEC84
#define mmRLC_SRM_CNTL__VI                              0xEC80
#define mmRLC_SRM_DEBUG__VI                             0xEC82
#define mmRLC_SRM_DEBUG_SELECT__VI                      0xEC81
#define mmRLC_SRM_DRAM_ADDR__VI                         0xEC85
#define mmRLC_SRM_DRAM_DATA__VI                         0xEC86
#define mmRLC_SRM_GPM_ABORT__VI                         0xEC9C
#define mmRLC_SRM_GPM_COMMAND__VI                       0xEC87
#define mmRLC_SRM_GPM_COMMAND_STATUS__VI                0xEC88
#define mmRLC_SRM_INDEX_CNTL_ADDR_0__VI                 0xEC8B
#define mmRLC_SRM_INDEX_CNTL_ADDR_1__VI                 0xEC8C
#define mmRLC_SRM_INDEX_CNTL_ADDR_2__VI                 0xEC8D
#define mmRLC_SRM_INDEX_CNTL_ADDR_3__VI                 0xEC8E
#define mmRLC_SRM_INDEX_CNTL_ADDR_4__VI                 0xEC8F
#define mmRLC_SRM_INDEX_CNTL_ADDR_5__VI                 0xEC90
#define mmRLC_SRM_INDEX_CNTL_ADDR_6__VI                 0xEC91
#define mmRLC_SRM_INDEX_CNTL_ADDR_7__VI                 0xEC92
#define mmRLC_SRM_INDEX_CNTL_DATA_0__VI                 0xEC93
#define mmRLC_SRM_INDEX_CNTL_DATA_1__VI                 0xEC94
#define mmRLC_SRM_INDEX_CNTL_DATA_2__VI                 0xEC95
#define mmRLC_SRM_INDEX_CNTL_DATA_3__VI                 0xEC96
#define mmRLC_SRM_INDEX_CNTL_DATA_4__VI                 0xEC97
#define mmRLC_SRM_INDEX_CNTL_DATA_5__VI                 0xEC98
#define mmRLC_SRM_INDEX_CNTL_DATA_6__VI                 0xEC99
#define mmRLC_SRM_INDEX_CNTL_DATA_7__VI                 0xEC9A
#define mmRLC_SRM_RLCV_COMMAND__VI                      0xEC89
#define mmRLC_SRM_RLCV_COMMAND_STATUS__VI               0xEC8A
#define mmRLC_SRM_STAT__VI                              0xEC9B
#define mmRLC_STAT__VI                                  0xEC04
#define mmRLC_STATIC_PG_STATUS__VI                      0xEC6E
#define mmRLC_THREAD1_DELAY__VI                         0xEC52
#define mmRLC_UCODE_CNTL__VI                            0xEC27
#define mmSAM_IH_EXT_ERR_INTR__VI                       0x8810
#define mmSAM_IH_EXT_ERR_INTR_STATUS__VI                0x8812
#define mmSCL0_SCL_DEBUG2__VI                           0x1B69
#define mmSCL0_SCL_HORZ_FILTER_CONTROL__VI              0x1B48
#define mmSCL0_SCL_HORZ_FILTER_INIT__VI                 0x1B4A
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO__VI          0x1B49
#define mmSCL0_SCL_MODE__VI                             0x1B42
#define mmSCL0_SCL_ROUND_OFFSET__VI                     0x1B4F
#define mmSCL0_SCL_VERT_FILTER_CONTROL__VI              0x1B4B
#define mmSCL0_SCL_VERT_FILTER_INIT__VI                 0x1B4D
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT__VI             0x1B4E
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO__VI          0x1B4C
#define mmSCL0_VIEWPORT_START_SECONDARY__VI             0x1B5B
#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT__VI              0x1D5E
#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM__VI              0x1D5F
#define mmSCL1_SCL_ALU_CONTROL__VI                      0x1D54
#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL__VI           0x1D47
#define mmSCL1_SCL_BYPASS_CONTROL__VI                   0x1D45
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS__VI         0x1D55
#define mmSCL1_SCL_COEF_RAM_SELECT__VI                  0x1D40
#define mmSCL1_SCL_COEF_RAM_TAP_DATA__VI                0x1D41
#define mmSCL1_SCL_CONTROL__VI                          0x1D44
#define mmSCL1_SCL_DEBUG__VI                            0x1D6A
#define mmSCL1_SCL_DEBUG2__VI                           0x1D69
#define mmSCL1_SCL_F_SHARP_CONTROL__VI                  0x1D53
#define mmSCL1_SCL_HORZ_FILTER_CONTROL__VI              0x1D48
#define mmSCL1_SCL_HORZ_FILTER_INIT__VI                 0x1D4A
#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO__VI          0x1D49
#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL__VI         0x1D46
#define mmSCL1_SCL_MODE__VI                             0x1D42
#define mmSCL1_SCL_MODE_CHANGE_DET1__VI                 0x1D60
#define mmSCL1_SCL_MODE_CHANGE_DET2__VI                 0x1D61
#define mmSCL1_SCL_MODE_CHANGE_DET3__VI                 0x1D62
#define mmSCL1_SCL_MODE_CHANGE_MASK__VI                 0x1D63
#define mmSCL1_SCL_ROUND_OFFSET__VI                     0x1D4F
#define mmSCL1_SCL_TAP_CONTROL__VI                      0x1D43
#define mmSCL1_SCL_TEST_DEBUG_DATA__VI                  0x1D6C
#define mmSCL1_SCL_TEST_DEBUG_INDEX__VI                 0x1D6B
#define mmSCL1_SCL_UPDATE__VI                           0x1D51
#define mmSCL1_SCL_VERT_FILTER_CONTROL__VI              0x1D4B
#define mmSCL1_SCL_VERT_FILTER_INIT__VI                 0x1D4D
#define mmSCL1_SCL_VERT_FILTER_INIT_BOT__VI             0x1D4E
#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO__VI          0x1D4C
#define mmSCL1_VIEWPORT_SIZE__VI                        0x1D5D
#define mmSCL1_VIEWPORT_START__VI                       0x1D5C
#define mmSCL1_VIEWPORT_START_SECONDARY__VI             0x1D5B
#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT__VI              0x1F5E
#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM__VI              0x1F5F
#define mmSCL2_SCL_ALU_CONTROL__VI                      0x1F54
#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL__VI           0x1F47
#define mmSCL2_SCL_BYPASS_CONTROL__VI                   0x1F45
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS__VI         0x1F55
#define mmSCL2_SCL_COEF_RAM_SELECT__VI                  0x1F40
#define mmSCL2_SCL_COEF_RAM_TAP_DATA__VI                0x1F41
#define mmSCL2_SCL_CONTROL__VI                          0x1F44
#define mmSCL2_SCL_DEBUG__VI                            0x1F6A
#define mmSCL2_SCL_DEBUG2__VI                           0x1F69
#define mmSCL2_SCL_F_SHARP_CONTROL__VI                  0x1F53
#define mmSCL2_SCL_HORZ_FILTER_CONTROL__VI              0x1F48
#define mmSCL2_SCL_HORZ_FILTER_INIT__VI                 0x1F4A
#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO__VI          0x1F49
#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL__VI         0x1F46
#define mmSCL2_SCL_MODE__VI                             0x1F42
#define mmSCL2_SCL_MODE_CHANGE_DET1__VI                 0x1F60
#define mmSCL2_SCL_MODE_CHANGE_DET2__VI                 0x1F61
#define mmSCL2_SCL_MODE_CHANGE_DET3__VI                 0x1F62
#define mmSCL2_SCL_MODE_CHANGE_MASK__VI                 0x1F63
#define mmSCL2_SCL_ROUND_OFFSET__VI                     0x1F4F
#define mmSCL2_SCL_TAP_CONTROL__VI                      0x1F43
#define mmSCL2_SCL_TEST_DEBUG_DATA__VI                  0x1F6C
#define mmSCL2_SCL_TEST_DEBUG_INDEX__VI                 0x1F6B
#define mmSCL2_SCL_UPDATE__VI                           0x1F51
#define mmSCL2_SCL_VERT_FILTER_CONTROL__VI              0x1F4B
#define mmSCL2_SCL_VERT_FILTER_INIT__VI                 0x1F4D
#define mmSCL2_SCL_VERT_FILTER_INIT_BOT__VI             0x1F4E
#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO__VI          0x1F4C
#define mmSCL2_VIEWPORT_SIZE__VI                        0x1F5D
#define mmSCL2_VIEWPORT_START__VI                       0x1F5C
#define mmSCL2_VIEWPORT_START_SECONDARY__VI             0x1F5B
#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT__VI              0x415E
#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM__VI              0x415F
#define mmSCL3_SCL_ALU_CONTROL__VI                      0x4154
#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL__VI           0x4147
#define mmSCL3_SCL_BYPASS_CONTROL__VI                   0x4145
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS__VI         0x4155
#define mmSCL3_SCL_COEF_RAM_SELECT__VI                  0x4140
#define mmSCL3_SCL_COEF_RAM_TAP_DATA__VI                0x4141
#define mmSCL3_SCL_CONTROL__VI                          0x4144
#define mmSCL3_SCL_DEBUG__VI                            0x416A
#define mmSCL3_SCL_DEBUG2__VI                           0x4169
#define mmSCL3_SCL_F_SHARP_CONTROL__VI                  0x4153
#define mmSCL3_SCL_HORZ_FILTER_CONTROL__VI              0x4148
#define mmSCL3_SCL_HORZ_FILTER_INIT__VI                 0x414A
#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO__VI          0x4149
#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL__VI         0x4146
#define mmSCL3_SCL_MODE__VI                             0x4142
#define mmSCL3_SCL_MODE_CHANGE_DET1__VI                 0x4160
#define mmSCL3_SCL_MODE_CHANGE_DET2__VI                 0x4161
#define mmSCL3_SCL_MODE_CHANGE_DET3__VI                 0x4162
#define mmSCL3_SCL_MODE_CHANGE_MASK__VI                 0x4163
#define mmSCL3_SCL_ROUND_OFFSET__VI                     0x414F
#define mmSCL3_SCL_TAP_CONTROL__VI                      0x4143
#define mmSCL3_SCL_TEST_DEBUG_DATA__VI                  0x416C
#define mmSCL3_SCL_TEST_DEBUG_INDEX__VI                 0x416B
#define mmSCL3_SCL_UPDATE__VI                           0x4151
#define mmSCL3_SCL_VERT_FILTER_CONTROL__VI              0x414B
#define mmSCL3_SCL_VERT_FILTER_INIT__VI                 0x414D
#define mmSCL3_SCL_VERT_FILTER_INIT_BOT__VI             0x414E
#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO__VI          0x414C
#define mmSCL3_VIEWPORT_SIZE__VI                        0x415D
#define mmSCL3_VIEWPORT_START__VI                       0x415C
#define mmSCL3_VIEWPORT_START_SECONDARY__VI             0x415B
#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT__VI              0x435E
#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM__VI              0x435F
#define mmSCL4_SCL_ALU_CONTROL__VI                      0x4354
#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL__VI           0x4347
#define mmSCL4_SCL_BYPASS_CONTROL__VI                   0x4345
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS__VI         0x4355
#define mmSCL4_SCL_COEF_RAM_SELECT__VI                  0x4340
#define mmSCL4_SCL_COEF_RAM_TAP_DATA__VI                0x4341
#define mmSCL4_SCL_CONTROL__VI                          0x4344
#define mmSCL4_SCL_DEBUG__VI                            0x436A
#define mmSCL4_SCL_DEBUG2__VI                           0x4369
#define mmSCL4_SCL_F_SHARP_CONTROL__VI                  0x4353
#define mmSCL4_SCL_HORZ_FILTER_CONTROL__VI              0x4348
#define mmSCL4_SCL_HORZ_FILTER_INIT__VI                 0x434A
#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO__VI          0x4349
#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL__VI         0x4346
#define mmSCL4_SCL_MODE__VI                             0x4342
#define mmSCL4_SCL_MODE_CHANGE_DET1__VI                 0x4360
#define mmSCL4_SCL_MODE_CHANGE_DET2__VI                 0x4361
#define mmSCL4_SCL_MODE_CHANGE_DET3__VI                 0x4362
#define mmSCL4_SCL_MODE_CHANGE_MASK__VI                 0x4363
#define mmSCL4_SCL_ROUND_OFFSET__VI                     0x434F
#define mmSCL4_SCL_TAP_CONTROL__VI                      0x4343
#define mmSCL4_SCL_TEST_DEBUG_DATA__VI                  0x436C
#define mmSCL4_SCL_TEST_DEBUG_INDEX__VI                 0x436B
#define mmSCL4_SCL_UPDATE__VI                           0x4351
#define mmSCL4_SCL_VERT_FILTER_CONTROL__VI              0x434B
#define mmSCL4_SCL_VERT_FILTER_INIT__VI                 0x434D
#define mmSCL4_SCL_VERT_FILTER_INIT_BOT__VI             0x434E
#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO__VI          0x434C
#define mmSCL4_VIEWPORT_SIZE__VI                        0x435D
#define mmSCL4_VIEWPORT_START__VI                       0x435C
#define mmSCL4_VIEWPORT_START_SECONDARY__VI             0x435B
#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT__VI              0x455E
#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM__VI              0x455F
#define mmSCL5_SCL_ALU_CONTROL__VI                      0x4554
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL__VI           0x4547
#define mmSCL5_SCL_BYPASS_CONTROL__VI                   0x4545
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS__VI         0x4555
#define mmSCL5_SCL_COEF_RAM_SELECT__VI                  0x4540
#define mmSCL5_SCL_COEF_RAM_TAP_DATA__VI                0x4541
#define mmSCL5_SCL_CONTROL__VI                          0x4544
#define mmSCL5_SCL_DEBUG__VI                            0x456A
#define mmSCL5_SCL_DEBUG2__VI                           0x4569
#define mmSCL5_SCL_F_SHARP_CONTROL__VI                  0x4553
#define mmSCL5_SCL_HORZ_FILTER_CONTROL__VI              0x4548
#define mmSCL5_SCL_HORZ_FILTER_INIT__VI                 0x454A
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO__VI          0x4549
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL__VI         0x4546
#define mmSCL5_SCL_MODE__VI                             0x4542
#define mmSCL5_SCL_MODE_CHANGE_DET1__VI                 0x4560
#define mmSCL5_SCL_MODE_CHANGE_DET2__VI                 0x4561
#define mmSCL5_SCL_MODE_CHANGE_DET3__VI                 0x4562
#define mmSCL5_SCL_MODE_CHANGE_MASK__VI                 0x4563
#define mmSCL5_SCL_ROUND_OFFSET__VI                     0x454F
#define mmSCL5_SCL_TAP_CONTROL__VI                      0x4543
#define mmSCL5_SCL_TEST_DEBUG_DATA__VI                  0x456C
#define mmSCL5_SCL_TEST_DEBUG_INDEX__VI                 0x456B
#define mmSCL5_SCL_UPDATE__VI                           0x4551
#define mmSCL5_SCL_VERT_FILTER_CONTROL__VI              0x454B
#define mmSCL5_SCL_VERT_FILTER_INIT__VI                 0x454D
#define mmSCL5_SCL_VERT_FILTER_INIT_BOT__VI             0x454E
#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO__VI          0x454C
#define mmSCL5_VIEWPORT_SIZE__VI                        0x455D
#define mmSCL5_VIEWPORT_START__VI                       0x455C
#define mmSCL5_VIEWPORT_START_SECONDARY__VI             0x455B
#define mmSCLK_CGTT_BLK_CTRL_REG__VI                    0x0136
#define mmSCLV_ALU_CONTROL__VI                          0x4685
#define mmSCLV_AUTOMATIC_MODE_CONTROL__VI               0x4676
#define mmSCLV_COEF_RAM_SELECT__VI                      0x4670
#define mmSCLV_COEF_RAM_TAP_DATA__VI                    0x4671
#define mmSCLV_CONTROL__VI                              0x4674
#define mmSCLV_DEBUG__VI                                0x4693
#define mmSCLV_DEBUG2__VI                               0x4692
#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT__VI              0x468C
#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM__VI              0x468D
#define mmSCLV_HORZ_FILTER_CONTROL__VI                  0x4677
#define mmSCLV_HORZ_FILTER_INIT__VI                     0x4679
#define mmSCLV_HORZ_FILTER_INIT_C__VI                   0x467B
#define mmSCLV_HORZ_FILTER_SCALE_RATIO__VI              0x4678
#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C__VI            0x467A
#define mmSCLV_MANUAL_REPLICATE_CONTROL__VI             0x4675
#define mmSCLV_MODE__VI                                 0x4672
#define mmSCLV_MODE_CHANGE_DET1__VI                     0x468E
#define mmSCLV_MODE_CHANGE_DET2__VI                     0x468F
#define mmSCLV_MODE_CHANGE_DET3__VI                     0x4690
#define mmSCLV_MODE_CHANGE_MASK__VI                     0x4691
#define mmSCLV_ROUND_OFFSET__VI                         0x4683
#define mmSCLV_TAP_CONTROL__VI                          0x4673
#define mmSCLV_TEST_DEBUG_DATA__VI                      0x4695
#define mmSCLV_TEST_DEBUG_INDEX__VI                     0x4694
#define mmSCLV_UPDATE__VI                               0x4684
#define mmSCLV_VERT_FILTER_CONTROL__VI                  0x467C
#define mmSCLV_VERT_FILTER_INIT__VI                     0x467E
#define mmSCLV_VERT_FILTER_INIT_BOT__VI                 0x467F
#define mmSCLV_VERT_FILTER_INIT_BOT_C__VI               0x4682
#define mmSCLV_VERT_FILTER_INIT_C__VI                   0x4681
#define mmSCLV_VERT_FILTER_SCALE_RATIO__VI              0x467D
#define mmSCLV_VERT_FILTER_SCALE_RATIO_C__VI            0x4680
#define mmSCLV_VIEWPORT_SIZE__VI                        0x4688
#define mmSCLV_VIEWPORT_SIZE_C__VI                      0x468B
#define mmSCLV_VIEWPORT_START__VI                       0x4686
#define mmSCLV_VIEWPORT_START_C__VI                     0x4689
#define mmSCLV_VIEWPORT_START_SECONDARY__VI             0x4687
#define mmSCLV_VIEWPORT_START_SECONDARY_C__VI           0x468A
#define mmSCL_DEBUG2__VI                                0x1B69
#define mmSCL_HORZ_FILTER_CONTROL__VI                   0x1B48
#define mmSCL_HORZ_FILTER_INIT__VI                      0x1B4A
#define mmSCL_HORZ_FILTER_SCALE_RATIO__VI               0x1B49
#define mmSCL_MODE__VI                                  0x1B42
#define mmSCL_ROUND_OFFSET__VI                          0x1B4F
#define mmSCL_VERT_FILTER_CONTROL__VI                   0x1B4B
#define mmSCL_VERT_FILTER_INIT__VI                      0x1B4D
#define mmSCL_VERT_FILTER_INIT_BOT__VI                  0x1B4E
#define mmSCL_VERT_FILTER_SCALE_RATIO__VI               0x1B4C
#define mmSDMA0_ACTIVE_FCN_ID__VI                       0x341F
#define mmSDMA0_ATOMIC_CNTL__VI                         0x342E
#define mmSDMA0_ATOMIC_PREOP_HI__VI                     0x3430
#define mmSDMA0_ATOMIC_PREOP_LO__VI                     0x342F
#define mmSDMA0_BA_THRESHOLD__VI                        0x342B
#define mmSDMA0_CONTEXT_REG_TYPE0__VI                   0x3478
#define mmSDMA0_CONTEXT_REG_TYPE1__VI                   0x3479
#define mmSDMA0_CONTEXT_REG_TYPE2__VI                   0x347A
#define mmSDMA0_EDC_CONFIG__VI                          0x341A
#define mmSDMA0_GFX_CSA_ADDR_HI__VI                     0x34AD
#define mmSDMA0_GFX_CSA_ADDR_LO__VI                     0x34AC
#define mmSDMA0_GFX_DOORBELL__VI                        0x3492
#define mmSDMA0_GFX_DOORBELL_LOG__VI                    0x34A9
#define mmSDMA0_GFX_DUMMY_REG__VI                       0x34B1
#define mmSDMA0_GFX_IB_SUB_REMAIN__VI                   0x34AF
#define mmSDMA0_GFX_MIDCMD_CNTL__VI                     0x34C7
#define mmSDMA0_GFX_MIDCMD_DATA0__VI                    0x34C1
#define mmSDMA0_GFX_MIDCMD_DATA1__VI                    0x34C2
#define mmSDMA0_GFX_MIDCMD_DATA2__VI                    0x34C3
#define mmSDMA0_GFX_MIDCMD_DATA3__VI                    0x34C4
#define mmSDMA0_GFX_MIDCMD_DATA4__VI                    0x34C5
#define mmSDMA0_GFX_MIDCMD_DATA5__VI                    0x34C6
#define mmSDMA0_GFX_PREEMPT__VI                         0x34B0
#define mmSDMA0_GFX_WATERMARK__VI                       0x34AA
#define mmSDMA0_ID__VI                                  0x342C
#define mmSDMA0_PERFCOUNTER0_RESULT__VI                 0x9001
#define mmSDMA0_PERFCOUNTER1_RESULT__VI                 0x9002
#define mmSDMA0_PERFMON_CNTL__VI                        0x9000
#define mmSDMA0_PERF_REG_TYPE0__VI                      0x3477
#define mmSDMA0_POWER_CNTL_IDLE__VI                     0x342C
#define mmSDMA0_PUB_REG_TYPE0__VI                       0x347C
#define mmSDMA0_PUB_REG_TYPE1__VI                       0x347D
#define mmSDMA0_RD_BURST_CNTL__VI                       0x340F
#define mmSDMA0_RLC0_CSA_ADDR_HI__VI                    0x352D
#define mmSDMA0_RLC0_CSA_ADDR_LO__VI                    0x352C
#define mmSDMA0_RLC0_DUMMY_REG__VI                      0x3531
#define mmSDMA0_RLC0_IB_SUB_REMAIN__VI                  0x352F
#define mmSDMA0_RLC0_MIDCMD_CNTL__VI                    0x3547
#define mmSDMA0_RLC0_MIDCMD_DATA0__VI                   0x3541
#define mmSDMA0_RLC0_MIDCMD_DATA1__VI                   0x3542
#define mmSDMA0_RLC0_MIDCMD_DATA2__VI                   0x3543
#define mmSDMA0_RLC0_MIDCMD_DATA3__VI                   0x3544
#define mmSDMA0_RLC0_MIDCMD_DATA4__VI                   0x3545
#define mmSDMA0_RLC0_MIDCMD_DATA5__VI                   0x3546
#define mmSDMA0_RLC0_PREEMPT__VI                        0x3530
#define mmSDMA0_RLC0_WATERMARK__VI                      0x352A
#define mmSDMA0_RLC1_CSA_ADDR_HI__VI                    0x35AD
#define mmSDMA0_RLC1_CSA_ADDR_LO__VI                    0x35AC
#define mmSDMA0_RLC1_DUMMY_REG__VI                      0x35B1
#define mmSDMA0_RLC1_IB_SUB_REMAIN__VI                  0x35AF
#define mmSDMA0_RLC1_MIDCMD_CNTL__VI                    0x35C7
#define mmSDMA0_RLC1_MIDCMD_DATA0__VI                   0x35C1
#define mmSDMA0_RLC1_MIDCMD_DATA1__VI                   0x35C2
#define mmSDMA0_RLC1_MIDCMD_DATA2__VI                   0x35C3
#define mmSDMA0_RLC1_MIDCMD_DATA3__VI                   0x35C4
#define mmSDMA0_RLC1_MIDCMD_DATA4__VI                   0x35C5
#define mmSDMA0_RLC1_MIDCMD_DATA5__VI                   0x35C6
#define mmSDMA0_RLC1_PREEMPT__VI                        0x35B0
#define mmSDMA0_RLC1_WATERMARK__VI                      0x35AA
#define mmSDMA0_STATUS2_REG__VI                         0x341E
#define mmSDMA0_VERSION__VI                             0x342D
#define mmSDMA0_VF_ENABLE__VI                           0x342A
#define mmSDMA0_VIRT_RESET_REQ__VI                      0x3421
#define mmSDMA0_VM_CNTL__VI                             0x341B
#define mmSDMA0_VM_CTX_CNTL__VI                         0x3420
#define mmSDMA0_VM_CTX_HI__VI                           0x341D
#define mmSDMA0_VM_CTX_LO__VI                           0x341C
#define mmSDMA1_ACTIVE_FCN_ID__VI                       0x361F
#define mmSDMA1_ATOMIC_CNTL__VI                         0x362E
#define mmSDMA1_ATOMIC_PREOP_HI__VI                     0x3630
#define mmSDMA1_ATOMIC_PREOP_LO__VI                     0x362F
#define mmSDMA1_BA_THRESHOLD__VI                        0x362B
#define mmSDMA1_CONTEXT_REG_TYPE0__VI                   0x3678
#define mmSDMA1_CONTEXT_REG_TYPE1__VI                   0x3679
#define mmSDMA1_CONTEXT_REG_TYPE2__VI                   0x367A
#define mmSDMA1_EDC_CONFIG__VI                          0x361A
#define mmSDMA1_GFX_CSA_ADDR_HI__VI                     0x36AD
#define mmSDMA1_GFX_CSA_ADDR_LO__VI                     0x36AC
#define mmSDMA1_GFX_DOORBELL__VI                        0x3692
#define mmSDMA1_GFX_DOORBELL_LOG__VI                    0x36A9
#define mmSDMA1_GFX_DUMMY_REG__VI                       0x36B1
#define mmSDMA1_GFX_IB_SUB_REMAIN__VI                   0x36AF
#define mmSDMA1_GFX_MIDCMD_CNTL__VI                     0x36C7
#define mmSDMA1_GFX_MIDCMD_DATA0__VI                    0x36C1
#define mmSDMA1_GFX_MIDCMD_DATA1__VI                    0x36C2
#define mmSDMA1_GFX_MIDCMD_DATA2__VI                    0x36C3
#define mmSDMA1_GFX_MIDCMD_DATA3__VI                    0x36C4
#define mmSDMA1_GFX_MIDCMD_DATA4__VI                    0x36C5
#define mmSDMA1_GFX_MIDCMD_DATA5__VI                    0x36C6
#define mmSDMA1_GFX_PREEMPT__VI                         0x36B0
#define mmSDMA1_GFX_WATERMARK__VI                       0x36AA
#define mmSDMA1_ID__VI                                  0x362C
#define mmSDMA1_PERFCOUNTER0_RESULT__VI                 0x9011
#define mmSDMA1_PERFCOUNTER1_RESULT__VI                 0x9012
#define mmSDMA1_PERFMON_CNTL__VI                        0x9010
#define mmSDMA1_PERF_REG_TYPE0__VI                      0x3677
#define mmSDMA1_POWER_CNTL_IDLE__VI                     0x362C
#define mmSDMA1_PUB_REG_TYPE0__VI                       0x367C
#define mmSDMA1_PUB_REG_TYPE1__VI                       0x367D
#define mmSDMA1_RD_BURST_CNTL__VI                       0x360F
#define mmSDMA1_RLC0_CSA_ADDR_HI__VI                    0x372D
#define mmSDMA1_RLC0_CSA_ADDR_LO__VI                    0x372C
#define mmSDMA1_RLC0_DUMMY_REG__VI                      0x3731
#define mmSDMA1_RLC0_IB_SUB_REMAIN__VI                  0x372F
#define mmSDMA1_RLC0_MIDCMD_CNTL__VI                    0x3747
#define mmSDMA1_RLC0_MIDCMD_DATA0__VI                   0x3741
#define mmSDMA1_RLC0_MIDCMD_DATA1__VI                   0x3742
#define mmSDMA1_RLC0_MIDCMD_DATA2__VI                   0x3743
#define mmSDMA1_RLC0_MIDCMD_DATA3__VI                   0x3744
#define mmSDMA1_RLC0_MIDCMD_DATA4__VI                   0x3745
#define mmSDMA1_RLC0_MIDCMD_DATA5__VI                   0x3746
#define mmSDMA1_RLC0_PREEMPT__VI                        0x3730
#define mmSDMA1_RLC0_WATERMARK__VI                      0x372A
#define mmSDMA1_RLC1_CSA_ADDR_HI__VI                    0x37AD
#define mmSDMA1_RLC1_CSA_ADDR_LO__VI                    0x37AC
#define mmSDMA1_RLC1_DUMMY_REG__VI                      0x37B1
#define mmSDMA1_RLC1_IB_SUB_REMAIN__VI                  0x37AF
#define mmSDMA1_RLC1_MIDCMD_CNTL__VI                    0x37C7
#define mmSDMA1_RLC1_MIDCMD_DATA0__VI                   0x37C1
#define mmSDMA1_RLC1_MIDCMD_DATA1__VI                   0x37C2
#define mmSDMA1_RLC1_MIDCMD_DATA2__VI                   0x37C3
#define mmSDMA1_RLC1_MIDCMD_DATA3__VI                   0x37C4
#define mmSDMA1_RLC1_MIDCMD_DATA4__VI                   0x37C5
#define mmSDMA1_RLC1_MIDCMD_DATA5__VI                   0x37C6
#define mmSDMA1_RLC1_PREEMPT__VI                        0x37B0
#define mmSDMA1_RLC1_WATERMARK__VI                      0x37AA
#define mmSDMA1_STATUS2_REG__VI                         0x361E
#define mmSDMA1_VERSION__VI                             0x362D
#define mmSDMA1_VF_ENABLE__VI                           0x362A
#define mmSDMA1_VIRT_RESET_REQ__VI                      0x3621
#define mmSDMA1_VM_CNTL__VI                             0x361B
#define mmSDMA1_VM_CTX_CNTL__VI                         0x3620
#define mmSDMA1_VM_CTX_HI__VI                           0x361D
#define mmSDMA1_VM_CTX_LO__VI                           0x361C
#define mmSEM_ACTIVE_FCN_ID__VI                         0x0F97
#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA__VI            0x0F9F
#define mmSEM_PERFCOUNTER0_RESULT__VI                   0x0F92
#define mmSEM_PERFCOUNTER1_RESULT__VI                   0x0F93
#define mmSEM_PERFMON_CNTL__VI                          0x0F91
#define mmSEM_VF_ENABLE__VI                             0x0F95
#define mmSEM_VIRT_RESET_REQ__VI                        0x0F98
#define mmSE_CAC_CGTT_CLK_CTRL__VI                      0x3293
#define mmSMBCLK_PAD_CNTL__VI                           0x15ED
#define mmSMBDAT_PAD_CNTL__VI                           0x15EC
#define mmSMBUS_BACO_DUMMY__VI                          0x15EB
#define mmSMC_MSG_ARG_11__VI                            0x0093
#define mmSMU_BIF_VDDGFX_PWR_STATUS__VI                 0x14F8
#define mmSMU_CONTROL__VI                               0x012D
#define mmSMU_IND_DATA_0__VI                            0x01A7
#define mmSMU_IND_DATA_1__VI                            0x01A9
#define mmSMU_IND_DATA_2__VI                            0x01AB
#define mmSMU_IND_DATA_3__VI                            0x01AD
#define mmSMU_IND_DATA_4__VI                            0x01AF
#define mmSMU_IND_DATA_5__VI                            0x01B1
#define mmSMU_IND_DATA_6__VI                            0x01B3
#define mmSMU_IND_DATA_7__VI                            0x01B5
#define mmSMU_IND_INDEX_0__VI                           0x01A6
#define mmSMU_IND_INDEX_1__VI                           0x01A8
#define mmSMU_IND_INDEX_2__VI                           0x01AA
#define mmSMU_IND_INDEX_3__VI                           0x01AC
#define mmSMU_IND_INDEX_4__VI                           0x01AE
#define mmSMU_IND_INDEX_5__VI                           0x01B0
#define mmSMU_IND_INDEX_6__VI                           0x01B2
#define mmSMU_IND_INDEX_7__VI                           0x01B4
#define mmSMU_INTERRUPT_CONTROL__VI                     0x012E
#define mmSMU_MP1_RLC2MP_RESP__VI                       0x01F4
#define mmSMU_MP1_SRBM2P_MSG_5__VI                      0x01C5
#define mmSMU_RLC_RESPONSE__VI                          0xEC07
#define mmSM_CONTROL2__VI                               0x1B6E
#define mmSPI_COMPUTE_WF_CTX_SAVE__VI                   0x31FC
#define mmSPI_CONFIG_CNTL_2__VI                         0x2451
#define mmSPI_DSM_CNTL__VI                              0x2443
#define mmSPI_EDC_CNT__VI                               0x2444
#define mmSPI_GFX_CNTL__VI                              0x243C
#define mmSPI_RESOURCE_RESERVE_CU_12__VI                0x31F4
#define mmSPI_RESOURCE_RESERVE_CU_13__VI                0x31F5
#define mmSPI_RESOURCE_RESERVE_CU_14__VI                0x31F6
#define mmSPI_RESOURCE_RESERVE_CU_15__VI                0x31F7
#define mmSPI_RESOURCE_RESERVE_EN_CU_12__VI             0x31F8
#define mmSPI_RESOURCE_RESERVE_EN_CU_13__VI             0x31F9
#define mmSPI_RESOURCE_RESERVE_EN_CU_14__VI             0x31FA
#define mmSPI_RESOURCE_RESERVE_EN_CU_15__VI             0x31FB
#define mmSPI_START_PHASE__VI                           0x243B
#define mmSQC_ATC_EDC_GATCL1_CNT__VI                    0x23B3
#define mmSQC_DSM_CNTL__VI                              0x230F
#define mmSQC_EDC_CNT__VI                               0x23A0
#define mmSQC_GATCL1_CNTL__VI                           0x23B2
#define mmSQC_WRITEBACK__VI                             0xC349
#define mmSQ_DSM_CNTL__VI                               0x2306
#define mmSQ_EDC_DED_CNT__VI                            0x23A2
#define mmSQ_EDC_INFO__VI                               0x23A3
#define mmSQ_EDC_SEC_CNT__VI                            0x23A1
#define mmSQ_M0_GPR_IDX_WORD__VI                        0x23D2
#define mmSQ_SMEM_0__VI                                 0x237F
#define mmSQ_SMEM_1__VI                                 0x237F
#define mmSQ_THREAD_TRACE_BASE__SI__CI                  0x2380
#define mmSQ_THREAD_TRACE_BASE__VI                      0xC330
#define mmSQ_THREAD_TRACE_BASE2__VI                     0xC337
#define mmSQ_THREAD_TRACE_CTRL__SI__CI                  0x238F
#define mmSQ_THREAD_TRACE_CTRL__VI                      0xC335
#define mmSQ_THREAD_TRACE_HIWATER__SI__CI               0x2392
#define mmSQ_THREAD_TRACE_HIWATER__VI                   0xC33B
#define mmSQ_THREAD_TRACE_MASK__SI__CI                  0x2382
#define mmSQ_THREAD_TRACE_MASK__VI                      0xC332
#define mmSQ_THREAD_TRACE_MODE__SI__CI                  0x238E
#define mmSQ_THREAD_TRACE_MODE__VI                      0xC336
#define mmSQ_THREAD_TRACE_PERF_MASK__SI__CI             0x2384
#define mmSQ_THREAD_TRACE_PERF_MASK__VI                 0xC334
#define mmSQ_THREAD_TRACE_SIZE__SI__CI                  0x2381
#define mmSQ_THREAD_TRACE_SIZE__VI                      0xC331
#define mmSQ_THREAD_TRACE_STATUS__SI__CI                0x238D
#define mmSQ_THREAD_TRACE_STATUS__VI                    0xC33A
#define mmSQ_THREAD_TRACE_TOKEN_MASK__SI__CI            0x2383
#define mmSQ_THREAD_TRACE_TOKEN_MASK__VI                0xC333
#define mmSQ_THREAD_TRACE_TOKEN_MASK2__VI               0xC338
#define mmSQ_THREAD_TRACE_WPTR__SI__CI                  0x238C
#define mmSQ_THREAD_TRACE_WPTR__VI                      0xC339
#define mmSQ_VOP_DPP__VI                                0x237F
#define mmSQ_VOP_SDWA__VI                               0x237F
#define mmSQ_WREXEC_EXEC_HI__VI                         0x23B1
#define mmSQ_WREXEC_EXEC_LO__VI                         0x23B1
#define mmSRBM_CAM_DATA__SI__CI                         0x0397
#define mmSRBM_CAM_DATA__VI                             0xFE35
#define mmSRBM_CAM_INDEX__SI__CI                        0x0396
#define mmSRBM_CAM_INDEX__VI                            0xFE34
#define mmSRBM_CREDIT_RECOVER__VI                       0x039D
#define mmSRBM_CREDIT_RECOVER_CNTL__VI                  0x039C
#define mmSRBM_CREDIT_RESET__VI                         0x039E
#define mmSRBM_DEBUG_SNAPSHOT2__VI                      0x03AD
#define mmSRBM_DSM_TRIG_CNTL0__VI                       0x03AF
#define mmSRBM_DSM_TRIG_CNTL1__VI                       0x03B0
#define mmSRBM_DSM_TRIG_MASK0__VI                       0x03B1
#define mmSRBM_DSM_TRIG_MASK1__VI                       0x03B2
#define mmSRBM_FIREWALL_ERROR_ADDR__VI                  0x03AC
#define mmSRBM_FIREWALL_ERROR_SRC__VI                   0x03AB
#define mmSRBM_GFX_CNTL_DATA__VI                        0xFA2F
#define mmSRBM_GFX_CNTL_SELECT__VI                      0xFA2E
#define mmSRBM_ISP_CLKEN_CNTL__VI                       0x03B9
#define mmSRBM_ISP_DOMAIN_ADDR0__VI                     0xFA20
#define mmSRBM_ISP_DOMAIN_ADDR1__VI                     0xFA21
#define mmSRBM_ISP_DOMAIN_ADDR2__VI                     0xFA22
#define mmSRBM_MC_DOMAIN_ADDR0__VI                      0xFA00
#define mmSRBM_MC_DOMAIN_ADDR1__VI                      0xFA01
#define mmSRBM_MC_DOMAIN_ADDR2__VI                      0xFA02
#define mmSRBM_MC_DOMAIN_ADDR3__VI                      0xFA03
#define mmSRBM_MC_DOMAIN_ADDR4__VI                      0xFA04
#define mmSRBM_MC_DOMAIN_ADDR5__VI                      0xFA05
#define mmSRBM_MC_DOMAIN_ADDR6__VI                      0xFA06
#define mmSRBM_PERFCOUNTER0_HI__SI__CI                  0x0704
#define mmSRBM_PERFCOUNTER0_HI__VI                      0x7C04
#define mmSRBM_PERFCOUNTER0_LO__SI__CI                  0x0703
#define mmSRBM_PERFCOUNTER0_LO__VI                      0x7C03
#define mmSRBM_PERFCOUNTER0_SELECT__SI__CI              0x0701
#define mmSRBM_PERFCOUNTER0_SELECT__VI                  0x7C01
#define mmSRBM_PERFCOUNTER1_HI__SI__CI                  0x0706
#define mmSRBM_PERFCOUNTER1_HI__VI                      0x7C06
#define mmSRBM_PERFCOUNTER1_LO__SI__CI                  0x0705
#define mmSRBM_PERFCOUNTER1_LO__VI                      0x7C05
#define mmSRBM_PERFCOUNTER1_SELECT__SI__CI              0x0702
#define mmSRBM_PERFCOUNTER1_SELECT__VI                  0x7C02
#define mmSRBM_PERFMON_CNTL__SI__CI                     0x0700
#define mmSRBM_PERFMON_CNTL__VI                         0x7C00
#define mmSRBM_READ_CNTL__VI                            0x0392
#define mmSRBM_READ_ERROR2__VI                          0x03AE
#define mmSRBM_SAM_DOMAIN_ADDR0__VI                     0xFA1C
#define mmSRBM_SAM_DOMAIN_ADDR1__VI                     0xFA1D
#define mmSRBM_SAM_DOMAIN_ADDR2__VI                     0xFA1E
#define mmSRBM_SDMA_DOMAIN_ADDR0__VI                    0xFA10
#define mmSRBM_SDMA_DOMAIN_ADDR1__VI                    0xFA11
#define mmSRBM_SDMA_DOMAIN_ADDR2__VI                    0xFA12
#define mmSRBM_SDMA_DOMAIN_ADDR3__VI                    0xFA13
#define mmSRBM_STATUS3__VI                              0x0395
#define mmSRBM_SYS_DOMAIN_ADDR0__VI                     0xFA08
#define mmSRBM_SYS_DOMAIN_ADDR1__VI                     0xFA09
#define mmSRBM_SYS_DOMAIN_ADDR2__VI                     0xFA0A
#define mmSRBM_SYS_DOMAIN_ADDR3__VI                     0xFA0B
#define mmSRBM_SYS_DOMAIN_ADDR4__VI                     0xFA0C
#define mmSRBM_SYS_DOMAIN_ADDR5__VI                     0xFA0D
#define mmSRBM_SYS_DOMAIN_ADDR6__VI                     0xFA0E
#define mmSRBM_UVD_DOMAIN_ADDR0__VI                     0xFA14
#define mmSRBM_UVD_DOMAIN_ADDR1__VI                     0xFA15
#define mmSRBM_UVD_DOMAIN_ADDR2__VI                     0xFA16
#define mmSRBM_VCE_DOMAIN_ADDR0__VI                     0xFA18
#define mmSRBM_VCE_DOMAIN_ADDR1__VI                     0xFA19
#define mmSRBM_VCE_DOMAIN_ADDR2__VI                     0xFA1A
#define mmSRBM_VF_ENABLE__VI                            0xFA30
#define mmSRBM_VIRT_CNTL__VI                            0xFA31
#define mmSRBM_VIRT_RESET_REQ__VI                       0xFA32
#define mmSRBM_VP8_CLKEN_CNTL__VI                       0x03BA
#define mmSRBM_VP8_DOMAIN_ADDR0__VI                     0xFA24
#define mmSWRST_COMMAND_0__VI                           0x14A2
#define mmSWRST_COMMAND_1__VI                           0x14A3
#define mmSWRST_COMMAND_STATUS__VI                      0x14A0
#define mmSWRST_CONTROL_0__VI                           0x14A4
#define mmSWRST_CONTROL_1__VI                           0x14A5
#define mmSWRST_CONTROL_2__VI                           0x14A6
#define mmSWRST_CONTROL_3__VI                           0x14A7
#define mmSWRST_CONTROL_4__VI                           0x14A8
#define mmSWRST_CONTROL_5__VI                           0x14A9
#define mmSWRST_CONTROL_6__VI                           0x14AA
#define mmSWRST_EP_COMMAND_0__VI                        0x14AB
#define mmSWRST_EP_CONTROL_0__VI                        0x14AC
#define mmSWRST_GENERAL_CONTROL__VI                     0x14A1
#define mmSX_BLEND_OPT_CONTROL__VI                      0xA1D7
#define mmSX_BLEND_OPT_EPSILON__VI                      0xA1D6
#define mmSX_MRT0_BLEND_OPT__VI                         0xA1D8
#define mmSX_MRT1_BLEND_OPT__VI                         0xA1D9
#define mmSX_MRT2_BLEND_OPT__VI                         0xA1DA
#define mmSX_MRT3_BLEND_OPT__VI                         0xA1DB
#define mmSX_MRT4_BLEND_OPT__VI                         0xA1DC
#define mmSX_MRT5_BLEND_OPT__VI                         0xA1DD
#define mmSX_MRT6_BLEND_OPT__VI                         0xA1DE
#define mmSX_MRT7_BLEND_OPT__VI                         0xA1DF
#define mmSX_PS_DOWNCONVERT__VI                         0xA1D5
#define mmSYMCLKA_CLOCK_ENABLE__VI                      0x0160
#define mmSYMCLKB_CLOCK_ENABLE__VI                      0x0161
#define mmSYMCLKC_CLOCK_ENABLE__VI                      0x0162
#define mmSYMCLKD_CLOCK_ENABLE__VI                      0x0163
#define mmSYMCLKE_CLOCK_ENABLE__VI                      0x0164
#define mmSYMCLKF_CLOCK_ENABLE__VI                      0x0165
#define mmSYMCLKG_CLOCK_ENABLE__VI                      0x0117
#define mmSYS_GRBM_GFX_INDEX_DATA__VI                   0xFA2D
#define mmSYS_GRBM_GFX_INDEX_SELECT__VI                 0xFA2C
#define mmTCC_DSM_CNTL__VI                              0x2B85
#define mmTCC_EDC_CNT__VI                               0x2B82
#define mmTCC_EXE_DISABLE__VI                           0x2B84
#define mmTCP_ATC_EDC_GATCL1_CNT__VI                    0x32B1
#define mmTCP_CNTL2__VI                                 0x32B4
#define mmTCP_DSM_CNTL__VI                              0x32B3
#define mmTCP_EDC_CNT__VI                               0x2B17
#define mmTCP_GATCL1_CNTL__VI                           0x32B0
#define mmTCP_GATCL1_DSM_CNTL__VI                       0x32B2
#define mmTD_DSM_CNTL__VI                               0x252F
#define mmTMDS_CNTL__VI                                 0x4A6B
#define mmTMDS_CONTROL0_FEEDBACK__VI                    0x4A6D
#define mmTMDS_CONTROL_CHAR__VI                         0x4A6C
#define mmTMDS_CTL0_1_GEN_CNTL__VI                      0x4A75
#define mmTMDS_CTL2_3_GEN_CNTL__VI                      0x4A76
#define mmTMDS_CTL_BITS__VI                             0x4A72
#define mmTMDS_DCBALANCER_CONTROL__VI                   0x4A73
#define mmTMDS_DEBUG__VI                                0x4A71
#define mmTMDS_STEREOSYNC_CTL_SEL__VI                   0x4A6E
#define mmTMDS_SYNC_CHAR_PATTERN_0_1__VI                0x4A6F
#define mmTMDS_SYNC_CHAR_PATTERN_2_3__VI                0x4A70
#define mmUNIPHYA_CHANNEL_XBAR_CNTL__VI                 0x4806
#define mmUNIPHYA_LINK_CNTL__VI                         0x4805
#define mmUNIPHYB_CHANNEL_XBAR_CNTL__VI                 0x4808
#define mmUNIPHYB_LINK_CNTL__VI                         0x4807
#define mmUNIPHYC_CHANNEL_XBAR_CNTL__VI                 0x480A
#define mmUNIPHYC_LINK_CNTL__VI                         0x4809
#define mmUNIPHYD_CHANNEL_XBAR_CNTL__VI                 0x480C
#define mmUNIPHYD_LINK_CNTL__VI                         0x480B
#define mmUNIPHYE_CHANNEL_XBAR_CNTL__VI                 0x480E
#define mmUNIPHYE_LINK_CNTL__VI                         0x480D
#define mmUNIPHYF_CHANNEL_XBAR_CNTL__VI                 0x4810
#define mmUNIPHYF_LINK_CNTL__VI                         0x480F
#define mmUNIPHYG_CHANNEL_XBAR_CNTL__VI                 0x4812
#define mmUNIPHYG_LINK_CNTL__VI                         0x4811
#define mmUNIPHY_ANG_BIST_CNTL__VI                      0x48CC
#define mmUNIPHY_DATA_SYNCHRONIZATION__VI               0x48CA
#define mmUNIPHY_DEBUG__VI                              0x48D6
#define mmUNIPHY_IMPCAL_LINKA__VI                       0x4838
#define mmUNIPHY_IMPCAL_LINKB__VI                       0x4839
#define mmUNIPHY_IMPCAL_LINKC__VI                       0x483F
#define mmUNIPHY_IMPCAL_LINKD__VI                       0x4840
#define mmUNIPHY_IMPCAL_LINKE__VI                       0x4843
#define mmUNIPHY_IMPCAL_LINKF__VI                       0x4844
#define mmUNIPHY_IMPCAL_PERIOD__VI                      0x483A
#define mmUNIPHY_IMPCAL_PSW_AB__VI                      0x483E
#define mmUNIPHY_IMPCAL_PSW_CD__VI                      0x4842
#define mmUNIPHY_IMPCAL_PSW_EF__VI                      0x4846
#define mmUNIPHY_MACRO_CNTL_RESERVED0__VI               0x48C0
#define mmUNIPHY_MACRO_CNTL_RESERVED1__VI               0x48C1
#define mmUNIPHY_MACRO_CNTL_RESERVED10__VI              0x48CA
#define mmUNIPHY_MACRO_CNTL_RESERVED11__VI              0x48CB
#define mmUNIPHY_MACRO_CNTL_RESERVED12__VI              0x48CC
#define mmUNIPHY_MACRO_CNTL_RESERVED13__VI              0x48CD
#define mmUNIPHY_MACRO_CNTL_RESERVED14__VI              0x48CE
#define mmUNIPHY_MACRO_CNTL_RESERVED15__VI              0x48CF
#define mmUNIPHY_MACRO_CNTL_RESERVED16__VI              0x48D0
#define mmUNIPHY_MACRO_CNTL_RESERVED17__VI              0x48D1
#define mmUNIPHY_MACRO_CNTL_RESERVED18__VI              0x48D2
#define mmUNIPHY_MACRO_CNTL_RESERVED19__VI              0x48D3
#define mmUNIPHY_MACRO_CNTL_RESERVED2__VI               0x48C2
#define mmUNIPHY_MACRO_CNTL_RESERVED20__VI              0x48D4
#define mmUNIPHY_MACRO_CNTL_RESERVED21__VI              0x48D5
#define mmUNIPHY_MACRO_CNTL_RESERVED22__VI              0x48D6
#define mmUNIPHY_MACRO_CNTL_RESERVED23__VI              0x48D7
#define mmUNIPHY_MACRO_CNTL_RESERVED24__VI              0x48D8
#define mmUNIPHY_MACRO_CNTL_RESERVED25__VI              0x48D9
#define mmUNIPHY_MACRO_CNTL_RESERVED26__VI              0x48DA
#define mmUNIPHY_MACRO_CNTL_RESERVED27__VI              0x48DB
#define mmUNIPHY_MACRO_CNTL_RESERVED28__VI              0x48DC
#define mmUNIPHY_MACRO_CNTL_RESERVED29__VI              0x48DD
#define mmUNIPHY_MACRO_CNTL_RESERVED3__VI               0x48C3
#define mmUNIPHY_MACRO_CNTL_RESERVED30__VI              0x48DE
#define mmUNIPHY_MACRO_CNTL_RESERVED31__VI              0x48DF
#define mmUNIPHY_MACRO_CNTL_RESERVED4__VI               0x48C4
#define mmUNIPHY_MACRO_CNTL_RESERVED5__VI               0x48C5
#define mmUNIPHY_MACRO_CNTL_RESERVED6__VI               0x48C6
#define mmUNIPHY_MACRO_CNTL_RESERVED7__VI               0x48C7
#define mmUNIPHY_MACRO_CNTL_RESERVED8__VI               0x48C8
#define mmUNIPHY_MACRO_CNTL_RESERVED9__VI               0x48C9
#define mmUNIPHY_PLL_CONTROL1__VI                       0x48C6
#define mmUNIPHY_PLL_CONTROL2__VI                       0x48C7
#define mmUNIPHY_PLL_FBDIV__VI                          0x48C5
#define mmUNIPHY_PLL_SS_CNTL__VI                        0x48C9
#define mmUNIPHY_PLL_SS_STEP_SIZE__VI                   0x48C8
#define mmUNIPHY_POWER_CONTROL__VI                      0x48C4
#define mmUNIPHY_REG_TEST_OUTPUT__VI                    0x48CB
#define mmUNIPHY_REG_TEST_OUTPUT2__VI                   0x48CD
#define mmUNIPHY_TPG_CONTROL__VI                        0x48D4
#define mmUNIPHY_TPG_SEED__VI                           0x48D5
#define mmUNIPHY_TX_CONTROL1__VI                        0x48C0
#define mmUNIPHY_TX_CONTROL2__VI                        0x48C1
#define mmUNIPHY_TX_CONTROL3__VI                        0x48C2
#define mmUNIPHY_TX_CONTROL4__VI                        0x48C3
#define mmUNP_CRC_CONTROL__VI                           0x4630
#define mmUNP_CRC_CURRENT__VI                           0x4632
#define mmUNP_CRC_LAST__VI                              0x4633
#define mmUNP_CRC_MASK__VI                              0x4631
#define mmUNP_DEBUG__VI                                 0x4636
#define mmUNP_DEBUG2__VI                                0x4637
#define mmUNP_GRPH_CONTROL__VI                          0x4601
#define mmUNP_GRPH_CONTROL_EXP__VI                      0x4603
#define mmUNP_GRPH_DFQ_CONTROL__VI                      0x4629
#define mmUNP_GRPH_DFQ_STATUS__VI                       0x462A
#define mmUNP_GRPH_ENABLE__VI                           0x4600
#define mmUNP_GRPH_FLIP_RATE_CNTL__VI                   0x462F
#define mmUNP_GRPH_INTERRUPT_CONTROL__VI                0x462C
#define mmUNP_GRPH_INTERRUPT_STATUS__VI                 0x462B
#define mmUNP_GRPH_PITCH_C__VI                          0x4617
#define mmUNP_GRPH_PITCH_L__VI                          0x4616
#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__VI 0x460B
#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI 0x460D
#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI 0x460C
#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__VI 0x460A
#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__VI        0x4607
#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__VI   0x4609
#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__VI   0x4608
#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__VI        0x4606
#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__VI 0x4613
#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI 0x4615
#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI 0x4614
#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__VI 0x4612
#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__VI      0x460F
#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__VI 0x4611
#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__VI 0x4610
#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__VI      0x460E
#define mmUNP_GRPH_STEREOSYNC_FLIP__VI                  0x462E
#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__VI     0x4628
#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__VI     0x4627
#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C__VI          0x4626
#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L__VI          0x4625
#define mmUNP_GRPH_SURFACE_OFFSET_X_C__VI               0x4619
#define mmUNP_GRPH_SURFACE_OFFSET_X_L__VI               0x4618
#define mmUNP_GRPH_SURFACE_OFFSET_Y_C__VI               0x461B
#define mmUNP_GRPH_SURFACE_OFFSET_Y_L__VI               0x461A
#define mmUNP_GRPH_SWAP_CNTL__VI                        0x4605
#define mmUNP_GRPH_UPDATE__VI                           0x4624
#define mmUNP_GRPH_X_END_C__VI                          0x4621
#define mmUNP_GRPH_X_END_L__VI                          0x4620
#define mmUNP_GRPH_X_START_C__VI                        0x461D
#define mmUNP_GRPH_X_START_L__VI                        0x461C
#define mmUNP_GRPH_Y_END_C__VI                          0x4623
#define mmUNP_GRPH_Y_END_L__VI                          0x4622
#define mmUNP_GRPH_Y_START_C__VI                        0x461F
#define mmUNP_GRPH_Y_START_L__VI                        0x461E
#define mmUNP_HW_ROTATION__VI                           0x4635
#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK__VI             0x4634
#define mmUNP_TEST_DEBUG_DATA__VI                       0x4639
#define mmUNP_TEST_DEBUG_INDEX__VI                      0x4638
#define mmUVD_CGC_UDEC_STATUS__VI                       0x3D2D
#define mmUVD_JPEG_ADDR_CONFIG__VI                      0x3A1F
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH__VI             0x3C66
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW__VI              0x3C67
#define mmUVD_LMI_RBC_IB_VMID__VI                       0x3DA1
#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH__VI             0x3C68
#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW__VI              0x3C69
#define mmUVD_LMI_RBC_RB_VMID__VI                       0x3DA3
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__VI         0x3C5E
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__VI          0x3C5F
#define mmUVD_MIF_CURR_ADDR_CONFIG__VI                  0x3992
#define mmUVD_MIF_RECON1_ADDR_CONFIG__VI                0x39C5
#define mmUVD_MIF_REF_ADDR_CONFIG__VI                   0x3993
#define mmUVD_PGFSM_CONFIG__VI                          0x38C0
#define mmUVD_PGFSM_READ_TILE1__VI                      0x38C2
#define mmUVD_PGFSM_READ_TILE2__VI                      0x38C3
#define mmUVD_PGFSM_READ_TILE3__VI                      0x38C5
#define mmUVD_PGFSM_READ_TILE4__VI                      0x38C6
#define mmUVD_PGFSM_READ_TILE5__VI                      0x38C8
#define mmUVD_PGFSM_READ_TILE6__VI                      0x38EE
#define mmUVD_PGFSM_READ_TILE7__VI                      0x38EF
#define mmUVD_POWER_STATUS__VI                          0x38C4
#define mmUVD_SUVD_CGC_CTRL__VI                         0x3BE6
#define mmUVD_SUVD_CGC_GATE__VI                         0x3BE4
#define mmUVD_SUVD_CGC_STATUS__VI                       0x3BE5
#define mmUVD_UDEC_ADDR_CONFIG__VI                      0x3BD3
#define mmUVD_UDEC_DBW_ADDR_CONFIG__VI                  0x3BD5
#define mmUVD_UDEC_DB_ADDR_CONFIG__VI                   0x3BD4
#define mmVCE_LMI_CACHE_CTRL__VI                        0x85BD
#define mmVCE_LMI_CTRL__VI                              0x85A6
#define mmVCE_LMI_CTRL2__VI                             0x859D
#define mmVCE_LMI_SWAP_CNTL__VI                         0x85AD
#define mmVCE_LMI_SWAP_CNTL1__VI                        0x85AE
#define mmVCE_LMI_SWAP_CNTL2__VI                        0x85B3
#define mmVCE_LMI_SWAP_CNTL3__VI                        0x859E
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR__VI              0x8597
#define mmVCE_RB_ARB_CTRL__VI                           0x809F
#define mmVCE_RB_BASE_HI__VI                            0x8061
#define mmVCE_RB_BASE_HI2__VI                           0x805C
#define mmVCE_RB_BASE_HI3__VI                           0x80D5
#define mmVCE_RB_BASE_LO__VI                            0x8060
#define mmVCE_RB_BASE_LO2__VI                           0x805B
#define mmVCE_RB_BASE_LO3__VI                           0x80D4
#define mmVCE_RB_RPTR__VI                               0x8063
#define mmVCE_RB_RPTR2__VI                              0x805E
#define mmVCE_RB_RPTR3__VI                              0x80D7
#define mmVCE_RB_SIZE__VI                               0x8062
#define mmVCE_RB_SIZE2__VI                              0x805D
#define mmVCE_RB_SIZE3__VI                              0x80D6
#define mmVCE_RB_WPTR__VI                               0x8064
#define mmVCE_RB_WPTR2__VI                              0x805F
#define mmVCE_RB_WPTR3__VI                              0x80D8
#define mmVCE_SOFT_RESET__VI                            0x8048
#define mmVCE_STATUS__VI                                0x8001
#define mmVCE_SYS_INT_ACK__VI                           0x8541
#define mmVCE_SYS_INT_EN__VI                            0x8540
#define mmVCE_SYS_INT_STATUS__VI                        0x8541
#define mmVCE_UENC_DMA_DCLK_CTRL__VI                    0x8390
#define mmVCE_VCPU_CACHE_OFFSET0__VI                    0x8009
#define mmVCE_VCPU_CACHE_OFFSET1__VI                    0x800B
#define mmVCE_VCPU_CACHE_OFFSET2__VI                    0x800D
#define mmVCE_VCPU_CACHE_SIZE0__VI                      0x800A
#define mmVCE_VCPU_CACHE_SIZE1__VI                      0x800C
#define mmVCE_VCPU_CACHE_SIZE2__VI                      0x800E
#define mmVCE_VCPU_CNTL__VI                             0x8005
#define mmVGA25_PPLL_ANALOG__VI                         0x171B
#define mmVGA25_PPLL_FB_DIV__VI                         0x1715
#define mmVGA25_PPLL_POST_DIV__VI                       0x1718
#define mmVGA25_PPLL_REF_DIV__VI                        0x1712
#define mmVGA28_PPLL_ANALOG__VI                         0x171C
#define mmVGA28_PPLL_FB_DIV__VI                         0x1716
#define mmVGA28_PPLL_POST_DIV__VI                       0x1719
#define mmVGA28_PPLL_REF_DIV__VI                        0x1713
#define mmVGA41_PPLL_ANALOG__VI                         0x171D
#define mmVGA41_PPLL_FB_DIV__VI                         0x1717
#define mmVGA41_PPLL_POST_DIV__VI                       0x171A
#define mmVGA41_PPLL_REF_DIV__VI                        0x1714
#define mmVGT_DISPATCH_DRAW_INDEX__VI                   0xA2DD
#define mmVGT_TESS_DISTRIBUTION__VI                     0xA2D4
#define mmVIEWPORT_START_SECONDARY__VI                  0x1B5B
#define mmVM_INIT_STATUS__VI                            0x14D3
#define mmVM_L2_BANK_SELECT_RESERVED_CID__VI            0x0579
#define mmVM_L2_BANK_SELECT_RESERVED_CID2__VI           0x057A
#define mmVM_L2_CNTL4__VI                               0x0578
#define mmWB_DBG_MODE__VI                               0x5E31
#define mmWB_DEBUG_CTRL__VI                             0x5E30
#define mmWB_EC_CONFIG__VI                              0x5E19
#define mmWB_ENABLE__VI                                 0x5E18
#define mmWB_HW_DEBUG__VI                               0x5E32
#define mmWB_SOFT_RESET__VI                             0x5E36
#define mmWD_QOS__VI                                    0x2242
#define mmXDMA_AON_TEST_DEBUG_DATA__VI                  0x03FD
#define mmXDMA_AON_TEST_DEBUG_INDEX__VI                 0x03FC
#define mmXDMA_CLOCK_GATING_CNTL__VI                    0x03E4
#define mmXDMA_IF_BIF_STATUS__VI                        0x03E7
#define mmXDMA_IF_STATUS__VI                            0x03E9
#define mmXDMA_INTERRUPT__VI                            0x03E3
#define mmXDMA_LOCAL_SURFACE_TILING1__VI                0x03E1
#define mmXDMA_LOCAL_SURFACE_TILING2__VI                0x03E2
#define mmXDMA_MC_PCIE_CLIENT_CONFIG__VI                0x03E0
#define mmXDMA_MEM_POWER_CNTL__VI                       0x03E6
#define mmXDMA_MSTR_CACHE__VI                           0x040A
#define mmXDMA_MSTR_CACHE_BASE_ADDR__VI                 0x0408
#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI            0x0409
#define mmXDMA_MSTR_CHANNEL_DIM__VI                     0x0402
#define mmXDMA_MSTR_CHANNEL_START__VI                   0x040B
#define mmXDMA_MSTR_CMD_URGENT_CNTL__VI                 0x03F2
#define mmXDMA_MSTR_CNTL__VI                            0x03EC
#define mmXDMA_MSTR_HEIGHT__VI                          0x0403
#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__VI         0x03EF
#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__VI    0x03F0
#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH__VI             0x03F1
#define mmXDMA_MSTR_MEM_CLIENT_CONFIG__VI               0x03EE
#define mmXDMA_MSTR_MEM_NACK_STATUS__VI                 0x03F6
#define mmXDMA_MSTR_MEM_URGENT_CNTL__VI                 0x03F3
#define mmXDMA_MSTR_PCIE_NACK_STATUS__VI                0x03F5
#define mmXDMA_MSTR_PERFMEAS_CNTL__VI                   0x040F
#define mmXDMA_MSTR_PERFMEAS_STATUS__VI                 0x040E
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE__VI           0x040A
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR__VI 0x0408
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI 0x0409
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM__VI     0x0402
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START__VI   0x040B
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT__VI          0x0403
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL__VI   0x040F
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS__VI 0x040E
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL__VI       0x0400
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND__VI    0x0401
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI 0x0406
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI 0x0407
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE__VI 0x0404
#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI 0x0405
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE__VI           0x041A
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR__VI 0x0418
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI 0x0419
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM__VI     0x0412
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START__VI   0x041B
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT__VI          0x0413
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL__VI   0x041F
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS__VI 0x041E
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL__VI       0x0410
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND__VI    0x0411
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI 0x0416
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI 0x0417
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE__VI 0x0414
#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI 0x0415
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE__VI           0x042A
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR__VI 0x0428
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI 0x0429
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM__VI     0x0422
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START__VI   0x042B
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT__VI          0x0423
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL__VI   0x042F
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS__VI 0x042E
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL__VI       0x0420
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND__VI    0x0421
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI 0x0426
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI 0x0427
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE__VI 0x0424
#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI 0x0425
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE__VI           0x043A
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR__VI 0x0438
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI 0x0439
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM__VI     0x0432
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START__VI   0x043B
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT__VI          0x0433
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL__VI   0x043F
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS__VI 0x043E
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL__VI       0x0430
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND__VI    0x0431
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI 0x0436
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI 0x0437
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE__VI 0x0434
#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI 0x0435
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE__VI           0x044A
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR__VI 0x0448
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI 0x0449
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM__VI     0x0442
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START__VI   0x044B
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT__VI          0x0443
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL__VI   0x044F
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS__VI 0x044E
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL__VI       0x0440
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND__VI    0x0441
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI 0x0446
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI 0x0447
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE__VI 0x0444
#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI 0x0445
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE__VI           0x045A
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR__VI 0x0458
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI 0x0459
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM__VI     0x0452
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START__VI   0x045B
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT__VI          0x0453
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL__VI   0x045F
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS__VI 0x045E
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL__VI       0x0450
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND__VI    0x0451
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI 0x0456
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI 0x0457
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE__VI 0x0454
#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI 0x0455
#define mmXDMA_MSTR_PIPE_CNTL__VI                       0x0400
#define mmXDMA_MSTR_READ_COMMAND__VI                    0x0401
#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS__VI              0x0406
#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI         0x0407
#define mmXDMA_MSTR_REMOTE_SURFACE_BASE__VI             0x0404
#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI        0x0405
#define mmXDMA_MSTR_STATUS__VI                          0x03ED
#define mmXDMA_MSTR_VSYNC_GSL_CHECK__VI                 0x03F7
#define mmXDMA_PERF_MEAS_STATUS__VI                     0x03E8
#define mmXDMA_PG_CONTROL__VI                           0x03F9
#define mmXDMA_PG_STATUS__VI                            0x03FB
#define mmXDMA_PG_WDATA__VI                             0x03FA
#define mmXDMA_RBBMIF_RDWR_CNTL__VI                     0x03F8
#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL__VI   0x0470
#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS__VI 0x0471
#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI 0x0472
#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL__VI   0x0478
#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS__VI 0x0479
#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI 0x047A
#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL__VI   0x0480
#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS__VI 0x0481
#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI 0x0482
#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL__VI   0x0488
#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS__VI 0x0489
#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI 0x048A
#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL__VI   0x0490
#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS__VI 0x0491
#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI 0x0492
#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL__VI   0x0498
#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS__VI 0x0499
#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI 0x049A
#define mmXDMA_SLV_CHANNEL_CNTL__VI                     0x0470
#define mmXDMA_SLV_CNTL__VI                             0x0460
#define mmXDMA_SLV_MEM_CLIENT_CONFIG__VI                0x0461
#define mmXDMA_SLV_MEM_NACK_STATUS__VI                  0x0469
#define mmXDMA_SLV_PCIE_NACK_STATUS__VI                 0x0468
#define mmXDMA_SLV_RDRET_BUF_STATUS__VI                 0x046A
#define mmXDMA_SLV_READ_LATENCY_AVE__VI                 0x0467
#define mmXDMA_SLV_READ_LATENCY_MINMAX__VI              0x0466
#define mmXDMA_SLV_READ_LATENCY_TIMER__VI               0x046B
#define mmXDMA_SLV_READ_URGENT_CNTL__VI                 0x0463
#define mmXDMA_SLV_REMOTE_GPU_ADDRESS__VI               0x0471
#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI          0x0472
#define mmXDMA_SLV_SLS_PITCH__VI                        0x0462
#define mmXDMA_SLV_WB_RATE_CNTL__VI                     0x0465
#define mmXDMA_SLV_WRITE_URGENT_CNTL__VI                0x0464
#define mmXDMA_TEST_DEBUG_DATA__VI                      0x03EB
#define mmXDMA_TEST_DEBUG_INDEX__VI                     0x03EA
#define offset_HEADER__VI
#define pciMSI_MASK__VI                                 0x002B
#define pciMSI_MASK_64__VI                              0x002C
#define pciMSI_PENDING__VI                              0x002C
#define pciMSI_PENDING_64__VI                           0x002D
#define pciPCIE_ARI_CAP__VI                             0x00CB
#define pciPCIE_ARI_CNTL__VI                            0x00CB
#define pciPCIE_ARI_ENH_CAP_LIST__VI                    0x00CA
#define pciPCIE_LTR_CAP__VI                             0x00C9
#define pciPCIE_LTR_ENH_CAP_LIST__VI                    0x00C8
#define pciPCIE_MC_ADDR0__VI                            0x00BE
#define pciPCIE_MC_ADDR1__VI                            0x00BF
#define pciPCIE_MC_BLOCK_ALL0__VI                       0x00C2
#define pciPCIE_MC_BLOCK_ALL1__VI                       0x00C3
#define pciPCIE_MC_BLOCK_UNTRANSLATED_0__VI             0x00C4
#define pciPCIE_MC_BLOCK_UNTRANSLATED_1__VI             0x00C5
#define pciPCIE_MC_CAP__VI                              0x00BD
#define pciPCIE_MC_CNTL__VI                             0x00BD
#define pciPCIE_MC_ENH_CAP_LIST__VI                     0x00BC
#define pciPCIE_MC_RCV0__VI                             0x00C0
#define pciPCIE_MC_RCV1__VI                             0x00C1
#define pciPCIE_SRIOV_CAP__VI                           0x00CD
#define pciPCIE_SRIOV_CONTROL__VI                       0x00CE
#define pciPCIE_SRIOV_ENH_CAP_LIST__VI                  0x00CC
#define pciPCIE_SRIOV_FIRST_VF_OFFSET__VI               0x00D1
#define pciPCIE_SRIOV_FUNC_DEP_LINK__VI                 0x00D0
#define pciPCIE_SRIOV_INITIAL_VFS__VI                   0x00CF
#define pciPCIE_SRIOV_NUM_VFS__VI                       0x00D0
#define pciPCIE_SRIOV_STATUS__VI                        0x00CE
#define pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI           0x00D3
#define pciPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI              0x00D4
#define pciPCIE_SRIOV_TOTAL_VFS__VI                     0x00CF
#define pciPCIE_SRIOV_VF_BASE_ADDR_0__VI                0x00D5
#define pciPCIE_SRIOV_VF_BASE_ADDR_1__VI                0x00D6
#define pciPCIE_SRIOV_VF_BASE_ADDR_2__VI                0x00D7
#define pciPCIE_SRIOV_VF_BASE_ADDR_3__VI                0x00D8
#define pciPCIE_SRIOV_VF_BASE_ADDR_4__VI                0x00D9
#define pciPCIE_SRIOV_VF_BASE_ADDR_5__VI                0x00DA
#define pciPCIE_SRIOV_VF_DEVICE_ID__VI                  0x00D2
#define pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI 0x00DB
#define pciPCIE_SRIOV_VF_STRIDE__VI                     0x00D1
#define pciPCIE_TPH_REQR_CAP__VI                        0x00B9
#define pciPCIE_TPH_REQR_CNTL__VI                       0x00BA
#define pciPCIE_TPH_REQR_ENH_CAP_LIST__VI               0x00B8
#define pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI 0x0100
#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI          0x0101
#define pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI 0x0105

#endif // __SI__CI__VIoffset_HEADER
